JPH09167150A - Single chip microcomputer and test device/method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify an 1 chip microcomputer test and to reduce cost. SOLUTION: A mode setting means 30 sets a one chip microcomputer 40 to a CPU (1) mode. At the CPU (1) mode, data can be transferred between a terminal 23B and a data bus 26 and data can be transferred between a terminal 23A and a peripheral circuit 25A. A mode setting means 30' sets a one chip microcomputer 40' to a CPU (2) mode. At the CPU (2) mode, data can be transferred between a terminal 23A' and the data bus 26, and data can be transferred between a terminal 23B' and a peripheral circuit 25B'. Data is given from the memory part 42 of a test controller 41 to the terminals 23B and 23A' and data is outputted from the terminals 23A and 23B'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit having an emulator function for a single chip microcomputer.

[0002]

2. Description of the Related Art Conventionally, a single-chip microcomputer (hereinafter, single-chip microcomputer) including a storage circuit (hereinafter, memory) such as ROM and RAM and its peripheral circuits requires a program for operation.

Usually, a program is stored in a memory and instructions are executed according to the contents of the program. A single-chip microcomputer requires a software development tool called an emulator in order to check the program operation and debug.

The emulator has a memory (ROM) for storing a program for executing instructions and a memory (RAM) for holding data externally, and a program counter for designating the contents of the memory and these addresses. It is necessary to be able to confirm the contents.

For this reason, conventionally, there is a method of making an emulator variation chip separately from the product (single chip microcomputer) and a method of providing a test circuit in the product and performing an operation equivalent to that of the variation chip. .

Since the present invention is a method relating to the latter,
The conventional test circuit will be described below. FIG.
1 shows a configuration of a main part of a conventional single-chip microcomputer.

The data input / output terminals 11A and 11B of the single-chip microcomputer 10 are connected to the switching circuit 12 respectively.
It is connected to A and 12B. The switching circuit 12A is
It is connected to the data bus 14 via the peripheral circuit 13A or directly and is also connected to the switching circuit 15. The switching circuit 15 is connected to the memory 16 and the data bus 14.

The mode setting terminals 18A and 18B are connected to the mode setting means 19 for setting the mode at the time of testing the single chip microcomputer 10. The instruction clock is applied to the clock input terminal 20.

The switching circuit 12A switches between input / output of the peripheral circuit 13A and input / output of the data bus 14. The switching circuit 12B switches between the input / output of the peripheral circuit 13B and the input / output of the data bus 14. Also, the switching circuit 1
Reference numeral 5 switches the input / output of the external memory and the input / output of the internal memory.

FIG. 5 shows a state of a conventional single-chip microcomputer test. In this test method,
The emulator is configured by using three single-chip microcomputers and setting the mode of each single-chip microcomputer.

That is, in the single chip microcomputer 10,
Based on the mode setting signal from the test controller 21, the mode setting means 19 selects the CPU mode. The CPU mode is a memory unit (external memory) of the test control device 21.
In this mode, the data of No. 22 is led to the data bus 14 via the data input / output terminal 11A, the CPU 17 processes the data, and the data is output to the data input / output terminal 11B. is there.

In the single chip microcomputer 10 ', the mode setting means 19' selects the I / O1 mode based on the mode setting signal from the test controller 21. I / O1
The mode guides the input data to the data bus 14 'via the data input / output terminal 11A', and to the data input / output terminal 11B 'via the peripheral circuit 13B'. Is the mode of outputting.

In the single-chip microcomputer 10 '', the mode is set based on the mode setting signal from the test controller 21.
The mode setting means 19 ″ selects the I / O2 mode. I /
In the O2 mode, input data is input / output terminal 11B '.
It leads to the data bus 14 'via', and the peripheral circuit 13A
In this mode, the data is output to the data input / output terminal 11A ″ via ″.

The functions of the I / O1 mode and the I / O2 mode are the same, but a terminal for inputting data and a data input are provided.
The terminals for outputting the data are different. In the I / O1 mode and the I / O2 mode, the CPU inside the single-chip microcomputer does not need to function, so the data bus 14
It is separated from ‘14’.

As described above, the emulator operation is enabled by setting the three modes, and all the functions of the single-chip microcomputer are tested. With this emulator configuration, a chip set in the I / O1 mode or I / O2 mode is accessed and data is input / output only when an instruction for operating a peripheral circuit is executed. For this reason,
A chip set in the CPU mode outputs an instruction input / output switching signal, a command code, and the like to control the internal circuit of the chip set in the I / O1 mode / I / O2 mode.

In FIG. 5, solid lines in the single-chip microcomputer indicate circuits and signal lines actually used, and broken lines in the single-chip microcomputer indicate circuits and signal lines not used.

[0017]

In the conventional test circuit combining the three modes, the chip set to the CPU mode is set to the I / O1 mode and the I / O2 mode when the control instruction of the peripheral circuit is executed. Two chips have to be controlled.

Therefore, it takes time to transfer control signals such as input / output switching signals and instruction codes between the three chips, and these must be processed within one instruction cycle.

For example, as shown in FIG. 6, when the instruction execution period (1) of the CPU is divided into the actual execution period (2) of the CPU instruction and the other operation period (3), the other operation period It is sufficient to send the control signal (4) between chips using (3), but as shown in FIG. 7, the actual execution period (2) of the CPU instruction uses the entire instruction execution period (1) of the CPU. If it is, the control signal (4) between chips is set to an execution period (3) shorter than the normal CPU instruction execution period (1).
Must be entered.

That is, in the case of FIG. 7, the microcomputer must be designed to operate at a higher speed than the actual operation. Further, in the case of a CPU that requires high-speed processing, there is a delay in data and control signals between the CPU mode chip and the I / O1 mode chip and between the CPU mode chip and the I / O2 mode chip. It cannot be ignored.

This makes it impossible to construct an emulator compatible with a high-speed CPU. Further, there are many signal switching control portions, which causes an increase in test circuits and a chip cost.

The present invention has been made to solve the above-mentioned drawbacks, and its purpose is to simplify a control signal and to provide a high-speed CP.
It is to provide a low-cost single-chip microcomputer compatible with U.

[0023]

In order to achieve the above object, the single-chip micro computer of the present invention comprises:
A CPU for exchanging data between the data bus and the data bus, first and second peripheral circuits, and exchanging data between the first input / output terminal and the first peripheral circuit. And a data between the first input / output terminal and the data bus.
A first switching circuit for switching transmission / reception of data;
A second switching circuit for switching data transmission / reception between the input / output terminal and the second peripheral circuit and data transmission / reception between the second input / output terminal and the data bus; and the first switching circuit. And mode setting means for controlling the operation of the second switching circuit.

The test apparatus of the present invention is set in a state where data can be transferred between the first input / output terminal of the single-chip microcomputer and the data bus, and the single-chip microcomputer is set to a state in which data can be transferred. Means for setting a state in which data can be transferred between the second input / output terminal and the first peripheral circuit, and data is supplied to the first or second input / output terminal of the single chip microcomputer. Means and a CPU of the single-chip micro-computer, the first or second of the single-chip micro-computer.
And means for inspecting the data output from the input / output terminal.

According to the test method of the present invention, the data can be transferred between the first input / output terminal of the single-chip microcomputer and the data bus, and the single-chip microcomputer is set. Set the state in which data can be transferred between the second input / output terminal of the data and the first peripheral circuit,
Data is applied to the first or second input / output terminal of the single-chip micro computer, processed by the CPU of the single-chip micro computer, and the first or second input of the single-chip micro computer is performed. It is equipped with a series of steps of inspecting the data output from the output terminal.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION A single-chip microcomputer of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows a configuration of a main part of a microcomputer according to an embodiment of the present invention.

The data input / output terminals 23A and 23B of the single chip microcomputer 40 are connected to the switching circuit 24, respectively.
It is connected to A and 24B. The switching circuit 24A is
It is connected to the data bus 26 via the peripheral circuit 25A or via the switching circuit 27. Switching circuit 24B
Are connected to the data bus 26 via the peripheral circuit 25B or via the switching circuit 27.

The switching circuit 27 is connected to the internal memory 28 and also to the data bus 26. Mode
The mode setting terminal 31 is connected to the mode setting means 30 for setting the mode at the time of testing the single chip microcomputer 40. The instruction clock is the clock input terminal 32.
Is applied to

The switching circuit 24A switches between the input / output of the peripheral circuit 25A and the input / output of the data bus 26. The switching circuit 24B switches between input / output of the peripheral circuit 25B and input / output of the data bus 26. In addition, the switching circuit 2
Reference numeral 7 switches between input / output of a data input / output terminal and input / output of an internal memory.

FIG. 2 shows a state during a single chip microcomputer test of the present invention. In the test method of the present invention, two single chip microcomputers are used and the emulator is configured by setting the mode of each single chip microcomputer.

That is, in the single chip microcomputer 40,
Based on the mode setting signal from the test controller 41, the mode setting means 30 selects the CPU1 mode. CPU
In one mode, the data of the memory section (external memory) 42 of the test control device 41 is led to the data bus 26 via the data input / output terminal 23B, and the CPU 29 processes the data, and the peripheral circuit. In this mode, the data is output to the data input / output terminal 23A via 25A.

In the single chip microcomputer 40 ', the mode setting means 30' selects the CPU2 mode based on the mode setting signal from the test controller 41. CPU2
The mode guides the data of the memory section (external memory) 42 of the test control device 41 to the data bus 26 'via the data input / output terminal 23A', and the CPU 29 'processes the data. In this mode, the data is output to the data input / output terminal 23B 'via the peripheral circuit 25B'.

The functions of the CPU1 mode and the CPU2 mode are the same, but a terminal for inputting data and a data
The terminals for outputting the data are different. in this way,
The emulator operation is enabled by setting two modes, and all functions of the single chip microcomputer are tested.

In FIG. 2, solid lines in the single-chip microcomputer indicate circuits and signal lines actually used, and broken lines in the single-chip microcomputer indicate circuits and signal lines not used.

According to the test circuit for a single-chip microcomputer having the above-mentioned configuration, there are two types of terminals for accessing the external memory, which allows the two chips to simultaneously input / output external memory data from different terminals. The emulator is configured by operating the two CPUs in the same way.

That is, as shown in FIG. 3, since the control signal between the two chips can be eliminated, it is possible to use the entire CPU instruction execution period (1) as the CPU instruction actual execution period (2). it can. That is, at the time of test, the CPU can be operated at the same speed as in normal time, so that high-speed C
It is possible to realize an emulator that is compatible with PU.

[0037]

As described above, the single-chip microcomputer of the present invention has the following effects. By using the two chips and setting the mode of each chip, the CPUs of the respective chips are simultaneously operated to control the peripheral circuits. For this reason,
It is not necessary to provide a control signal between the two chips, and the operation speed of the CPU in the emulator composed of the two chips can be made the same as in the normal operation, and the emulator corresponding to the high speed CPU can be configured.

Further, since various control signals are not necessary, the switching circuit can be reduced, the chip cost can be reduced, and since the configuration can be made with two chips, the emulator board can be downsized, which is significant. Cost reduction is possible.

[Brief description of the drawings]

FIG. 1 is a diagram showing a single-chip micro computer for an embodiment of the present invention.

FIG. 2 is a diagram showing how the microcomputer of FIG. 1 is tested.

FIG. 3 is a diagram showing a relationship between an instruction execution period and an instruction actual execution period of the CPU of the present invention.

FIG. 4 is a diagram showing a conventional single-chip micro computer.

FIG. 5 is a diagram showing a state at the time of testing the microcomputer of FIG.

FIG. 6 is a diagram showing the relationship between the instruction execution period and the instruction actual execution period of a conventional CPU.

FIG. 7 is a diagram showing a relationship between an instruction execution period and an instruction actual execution period of a conventional CPU.

[Explanation of symbols]

10, 40: Single chip microcomputer, 11A, 11B, 23A, 23B: Data input / output terminal, 12A, 12B, 15, 24A, 24B, 27: Switching circuit, 13A, 13B, 25A, 25B: Peripheral circuit, 14 , 26: data bus, 16, 28: memory, 17, 29: CPU, 18A, 18B, 31: mode setting terminal, 19, 30: mode setting means, 20, 32: instruction clock terminal, 21 , 41: test control device, 22, 42: memory unit.

Claims (3)

[Claims] 1. A data bus, a CPU for exchanging data between the data bus and the first and second peripheral circuits, and a first input / output terminal and the first peripheral circuit. A first switching circuit for switching data transmission / reception and data transmission / reception between the first input / output terminal and the data bus, and data between the second input / output terminal and the second peripheral circuit. A second for switching between data transfer and data transfer between the second input / output terminal and the data bus
A single-chip microcomputer having a switching circuit and mode setting means for controlling the operations of the first and second switching circuits. 2. A single chip micro computer is set to a state in which data can be transferred between a first input / output terminal and a data bus, and the second input of the single chip micro computer is set. Between the output terminal and the first peripheral circuit
Means for setting a state in which data can be transferred and received, means for supplying data to the first or second input / output terminal of the single-chip micro computer, and processing by the CPU of the single-chip micro computer. And a means for inspecting the data output from the first or second input / output terminal of the single-chip micro computer. 3. A single chip micro computer is set to a state in which data can be transferred between the first input / output terminal and a data bus, and the second input of the single chip micro computer is set. Between the output terminal and the first peripheral circuit
Data transfer to and from the single chip micro computer, data is applied to the first or second input / output terminal of the single chip micro computer, and the data is processed by the CPU of the single chip micro computer. A test method comprising inspecting data output from a first or second input / output terminal of a microcomputer.