JPH09162376A - Dielectric isolation substrate manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the isolation voltage drop at isolating grooves. SOLUTION: A first insulation film 2 and semiconductor layer 3 are laminated on a support substrate 1, second insulation film 4 to be a buffer layer is laminated on a main face of the layer 3, trenches 9 are cut through this layer 3 to reach the film 2, sixth insulation film 10 is formed on the trenches 9 to be isolating grooves, and trenches are filled with a filler layer 11. Since the corners 40 of the layer 3 are covered with the layer 10, no drop of the isolation voltage never occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power IC in which a low breakdown voltage drive control circuit and a high breakdown voltage element are integrated in one chip.
And a method for manufacturing a dielectric isolation substrate for forming a semiconductor device in which a plurality of high breakdown voltage elements are integrated in one chip.

[0002]

2. Description of the Related Art A conventional method for manufacturing a dielectric isolation substrate is shown in the order of steps from FIGS. First on the support substrate 31
An SOI (Silicon) having a semiconductor layer 33 via an insulating film 32
(on insulator) The etching mask layer 34 is formed on the substrate, and patterning (including etching of the photoresist here) is performed using a photoresist (not shown) to open the etching mask layer 34 (FIG. 1).
4). Using this as a mask, a trench 35, which serves as an isolation groove reaching the first insulating film 32 from the surface of the semiconductor layer 33, is formed by a reactive ion etching (RIE) method (dry etching method) (FIG. 15). At this time, the semiconductor layer 3
3 has a thickness of about 10 μm and the trench 35 has a groove width of 2 to 6
μm. Next, the etching mask layer 34 is removed with a hydrofluoric acid aqueous solution (FIG. 16). At this time, the trench 35
Although the first insulating film 32 at the bottom of the is also slightly etched, it is omitted in this figure. After that, an eighth insulating film 36 (a sixth insulating film 10 of an example described later) which is a second insulating film is formed by thermal oxidation.
Is formed (FIG. 17), and the trench 35 is filled with the filling layer 37 (FIG. 18). At this time, the filling layer 37 is also deposited on the eighth insulating film 36 other than the trench 35. The thickness of the eighth insulating layer 36 is 1 μm, and the filling layer 37 is
Polycrystalline silicon is used for and its thickness is 1 to 3.5.
μm. Further, the filling layer 37 deposited on the surface is etched back (removed by etching) by the plasma etching method to expose the eighth insulating film 36 (FIG. 1).
9). Then, using the patterned photoresist as a mask, the eighth insulating film 36 in the trench 35 and its vicinity is left with a hydrofluoric acid aqueous solution, and the eighth insulating film 35 in the other regions is removed to remove the element forming region. The semiconductor layer 33 is exposed to complete the dielectric isolation substrate (FIG. 20).

[0003]

In the step of removing the eighth insulating film 36 shown in FIG. 20, the upper portion of the trench 35 must be covered with photoresist to leave the eighth insulating film 36 in this region. However, since the adhesiveness between the photoresist and the eighth insulating film 36 is not always good, the etching liquid permeates from the interface between the photoresist and the eighth insulating film 36 when etching with a hydrofluoric acid aqueous solution, and
The insulating layer 36 is etched to expose the surface of the semiconductor layer 33 and the corner portion 40 (in the circle) of the semiconductor layer 33 above the trench 35 (FIG. 21). For this reason trench 3
There is a problem that the insulation breakdown voltage between the opposing semiconductor layers 33 separated in step 5, that is, the separation breakdown voltage decreases. According to the experiment, compared with the case where the corner portion 40 is covered with the eighth insulating film 36, the isolation breakdown voltage is 700 V to 400 V when exposed.
It drops below V. When a high breakdown voltage element and a low breakdown voltage control circuit are integrated on a single chip, this separation breakdown voltage decreases
It is difficult to increase the breakdown voltage, and the originally required function of the control circuit cannot be obtained, which causes a problem that reliability is lowered.

An object of the present invention is to solve the above-mentioned problems and to provide a method for manufacturing a dielectric isolation substrate capable of producing a highly reliable semiconductor device which can obtain an isolation breakdown voltage as designed.

[0005]

In order to achieve the above object, a first insulating film and a semiconductor layer are laminated on a supporting substrate, and a second insulating film serving as a buffer layer is formed on the main surface of the semiconductor layer.
A third insulating film that serves as an oxidation resistant layer that prevents the semiconductor layer from being oxidized, a fourth insulating film that serves as an etching stop layer, and an element region defining layer that defines a planar region for forming the device are laminated respectively in a pre-process and a post-process. A step of leaving the element region defining layer in the region where the film is formed, a step of covering the fourth insulating film and the element region defining layer with a fifth insulating film serving as an etching mask layer, and forming a separation groove in the semiconductor layer. A step of forming a hole penetrating each of the fifth insulating film, the fourth insulating film, the third insulating film, and the second insulating film, and a step of forming a separation groove reaching the first insulating film in the semiconductor layer, A step of removing the fifth insulating film, a step of removing the third insulating film using the element region defining layer as a mask, and a step of forming a sixth insulating film on the sidewall of the isolation trench and the exposed portion of the second insulating film. And a packing layer to fill the separation groove. A step of, the process comprising a step of leaving a packed bed separation grooves.

After the step of leaving the filling layer in the isolation trench, a step of oxidizing the surface of the filling layer and a step of removing the third insulating film and the fourth insulating film may be added. The semiconductor layer is formed of single crystal silicon, the second insulating film and the fourth insulating film are formed of a silicon oxide film, the third insulating film is formed of a silicon nitride film, and the element region defining layer and the filling layer are multi-layered. It is preferably formed of crystalline silicon.

By adopting this manufacturing method, the corner portion of the semiconductor layer can be surely covered with the sixth insulating film, and the isolation breakdown voltage in the isolation trench portion can be prevented from lowering.

[0008]

1 to 12 show a manufacturing method according to an embodiment of the present invention, which will be described in the order of steps. A second insulating film 4 serving as a buffer layer on the main surface of the semiconductor layer 3 formed on the supporting substrate 1 via the first insulating film 2, a third insulating film 5 serving as an oxidation resistant layer for preventing the semiconductor layer from being oxidized, A fourth insulating film 6 serving as an etching stop layer and an element region defining layer 7 that defines a planar region for device formation are laminated (FIG. 1). In this embodiment, a single crystal silicon plate is used for the support substrate 1, the semiconductor layer 3 is formed of single crystal silicon to a thickness of 10 μm, the first insulating film 2 is formed of silicon oxide to a thickness of 2 μm, The insulating film 4 is formed of silicon oxide to a thickness of 35 nm, and the third insulating film 5 is formed of silicon nitride under reduced pressure CV.
Formed by depositing to a thickness of 0.12 μm by the D method,
The insulating film 6 is made of silicon oxide with a low pressure CVD method of 0.12 μm.
The element region defining layer 7 is formed by depositing polycrystalline silicon to a thickness of 0.3 μm by the low pressure CVD method.

Next, the device region defining layer 7 is formed on the surface of the fourth insulating film 6 on the semiconductor layer 3 in the region where the device is formed by patterning using a photoresist and dry etching.
Remain (FIG. 2). The fifth insulating film 8 (etch mask layer), which serves as an etching mask when forming the trench to be the isolation groove, is formed by depositing silicon oxide of 1.5 μm by the low pressure CVD method (FIG. 3). The region 9a where the trench is to be formed is patterned by using a photoresist, and the fifth insulating film 8 and the fourth insulating film 6 and the third insulating film 5 and the second insulating film 4 are respectively subjected to the reactive ion etching method (RIE method). ) To open (Fig. 4). The opening width at this time is about 2 μm.

Next, a trench 9 reaching the first insulating film 2 is formed by the reactive ion etching method using the opened fifth insulating film 8 as a mask (FIG. 5). The fifth insulating film 8 is removed by a hydrofluoric acid aqueous solution or a dry etching method (FIG. 6). At this time, the fourth insulating film 6 other than immediately below the element region defining layer 7 is also removed. Next, the element region defining layer 7
Using the fourth insulating film 6 as a mask, the third insulating film 5 is removed with a hot phosphoric acid solution heated to 130 ° C., and the third insulating film 5 is left only in the element formation region. After that, the element region defining layer 7 is removed by the reactive ion etching method (FIG. 7). At this time, both the third insulating film 5 and the element region defining layer 7 may be removed at the same time by using dry etching conditions having low selectivity with the device region defining layer 7. At this time the third
The substantial etching mask of the insulating film 5 is the silicon oxide film used as the fourth insulating film 6.

Next, the sixth insulating film 10 is selectively formed on the semiconductor layer 3 from which the third insulating film 5 has been removed by the thermal oxidation method (FIG. 8). The thickness of the sixth insulating film 10 is 0.8 to 1.0.
μm. A filling layer 11 is deposited in a thickness of 0.5 to 1.0 μm to fill the void in the trench 9 (FIG. 9). The filling layer 11 is made of polycrystalline silicon by the low pressure CVD method, which has excellent step coverage. Then, the filling layer 11 is left only in the trench 9 and its upper portion by patterning using a photoresist, and the filling layer 11 deposited on other regions is removed (FIG. 10).

Next, the remaining packed bed 1 is formed by a thermal oxidation method.
1 is oxidized to form the seventh insulating film 12 (see FIG. 1).
1). Finally, the fourth insulating film 6 on the surface is removed by a hydrofluoric acid aqueous solution or dry etching, and further the third insulating film 5 is removed by a dry etching method (FIG. 12). At this time, the surface layer of the seventh insulating film 12 is also etched and thinned.

Thereafter, in accordance with the element forming process, for example, each element element and wiring forming a high breakdown voltage IC are formed (see FIG. 1).
3). In the figure, as an example, p-channel MOSFET 17
And the n-channel MOSFET 18 is formed.
The gate electrode 14 is covered with the interlayer insulating film 13, the metal electrode 15 is formed on the source region, and the surface thereof is covered with the final protective film 16. Although not shown, the drain electrode is formed on the same side as the metal electrode 15 (source electrode).

As described above, in the manufacturing method of the present invention, since the sixth insulating film 10 is selectively formed, the corner portion 40 of the semiconductor layer adjacent to the isolation trench described above is formed.
(Circle in FIG. 12) is not exposed and is always covered with the sixth insulating film 10. Therefore, the isolation breakdown voltage is 7 as designed.
00V was obtained. The sixth insulating film 10 can also be used as an insulating film (for example, an interlayer insulating film) that covers regions other than the active regions of the element elements formed in the semiconductor layer 3.

In this embodiment, the step of manufacturing the dielectric isolation substrate and the impurity diffusion step of forming each element element are separated, but if the desired diffusion depth and surface concentration as the element element can be obtained, the isolation step is performed. Before forming the trench 9 which is a groove, a step of ion-implanting impurities for forming element elements may be performed.

[0016]

According to the present invention, the sixth insulating film is formed on the wall surface of the trench portion which is the separation groove and the corner portion of the semiconductor layer adjacent thereto by the selective oxidation method, so that the corner portion can be surely formed. And the isolation withstand voltage as designed can be obtained. Therefore, by using the dielectric isolation substrate manufactured by this manufacturing method, the required functions can be obtained as designed even when the high breakdown voltage element and the low breakdown voltage control circuit are integrated on one chip, and the semiconductor device of the semiconductor device can be manufactured. High reliability can be achieved. Further, it is possible to increase the breakdown voltage of the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a process diagram showing a manufacturing method according to an embodiment of the present invention.

FIG. 2 is a process drawing showing the manufacturing method following FIG.

FIG. 3 is a process drawing showing the manufacturing method following FIG.

FIG. 4 is a process drawing showing the manufacturing method following FIG.

FIG. 5 is a process drawing showing the manufacturing method following FIG.

FIG. 6 is a process drawing showing the manufacturing method following FIG. 5;

FIG. 7 is a process drawing showing the manufacturing method following FIG. 6;

FIG. 8 is a process drawing showing the manufacturing method following FIG.

FIG. 9 is a process drawing showing the manufacturing method following FIG. 8;

FIG. 10 is a process drawing showing the manufacturing method following FIG. 9;

11 is a process drawing showing the manufacturing method following FIG. 10. FIG.

FIG. 12 is a process drawing showing the manufacturing method following FIG. 11.

FIG. 13 is a cross-sectional view of a main part where element elements are formed.

FIG. 14 is a process diagram showing a conventional manufacturing method.

FIG. 15 is a process drawing showing the manufacturing method following FIG.

16 is a process drawing showing the manufacturing method following FIG. 15. FIG.

FIG. 17 is a process drawing showing the manufacturing method following FIG. 16;

FIG. 18 is a process drawing showing the manufacturing method following FIG. 17;

FIG. 19 is a process drawing showing the manufacturing method following FIG. 18;

FIG. 20 is a process drawing showing the manufacturing method following FIG. 19;

FIG. 21 is a view in which a corner portion of a semiconductor layer is exposed by a conventional manufacturing method.

[Explanation of symbols]

 1 Support Substrate 2 First Insulating Film 3 Semiconductor Layer 4 Second Insulating Film 5 Third Insulating Film 6 Fourth Insulating Film 7 Element Area Defining Layer 8 Fifth Insulating Film 9 Trench 10 Sixth Insulating Film 11 Filling Layer 12 Seventh Insulation Film 13 Interlayer insulating film 14 Gate electrode 15 Metal electrode 16 Final protective film 17 p-channel MOSFET 18 n-channel MOSFET 31 Support substrate 32 First insulating film 33 Semiconductor layer 34 Etching mask layer 35 Trench 36 Eighth insulating film 37 Filling layer 40 Semiconductor Layer corners

Claims (3)

[Claims] 1. A first insulating film and a semiconductor layer are laminated on a supporting substrate, a second insulating film serving as a buffer layer on the main surface of the semiconductor layer, and a third insulating serving as an oxidation resistant layer for preventing the semiconductor layer from being oxidized. A film, a fourth insulating film serving as an etching stop layer, and a device region defining layer that defines a planar region for device formation, respectively, and a process of leaving the device region defining layer in a region where a device is formed in a subsequent process. A step of covering the fourth insulating film and the element region defining layer with a fifth insulating film serving as an etching mask layer, and a fifth insulating film, a fourth insulating film, and a third insulating film for forming isolation trenches in the semiconductor layer. A step of forming a hole penetrating each of the insulating film and the second insulating film, a step of forming a separation groove reaching the first insulating film in the semiconductor layer, a step of removing the fifth insulating film, and an element region defining layer As a mask
A step of removing the insulating film, a step of forming a sixth insulating film on the side wall of the isolation groove and the exposed portion of the second insulating film, a step of depositing a filling layer for filling the isolation groove, A method of manufacturing a dielectric isolation substrate, comprising the step of leaving a filling layer. 2. After the step of leaving the filling layer in the separation groove,
The step of oxidizing the surface of the filling layer, the third insulating film, and the fourth
The method for manufacturing a dielectric isolation substrate according to claim 1, further comprising the step of removing the insulating film. 3. A semiconductor layer is formed of single crystal silicon, a second insulating film and a fourth insulating film are formed of a silicon oxide film, a third insulating film is formed of a silicon nitride film, an element region defining layer and a filling layer. 2. The method for manufacturing a dielectric isolation substrate according to claim 1, wherein the layer is made of polycrystalline silicon.