JPH0916123A - Image display device - Google Patents
Image display deviceInfo
- Publication number
- JPH0916123A JPH0916123A JP7168428A JP16842895A JPH0916123A JP H0916123 A JPH0916123 A JP H0916123A JP 7168428 A JP7168428 A JP 7168428A JP 16842895 A JP16842895 A JP 16842895A JP H0916123 A JPH0916123 A JP H0916123A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- thin film
- image display
- tft
- light emission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、画像表示装置に係り、
例えば有機ＥＬ画像表示装置のような、エレクトロルミ
ネセンス（ＥＬ）画像表示装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device,
The present invention relates to an electroluminescence (EL) image display device such as an organic EL image display device.
【０００２】[0002]
【従来の技術】図５、図６は従来例を示した図である。
以下、これらの図面に基づいて従来例を説明する。2. Description of the Related Art FIGS. 5 and 6 are views showing a conventional example.
Hereinafter, a conventional example will be described with reference to these drawings.
【０００３】図５（Ａ）は、パネルブロック図であり、
ディスプレイ（表示）パネル１０には、ディスプレイ画
面１１、Ｘ軸のシフトレジスタ１２、Ｙ軸のシフトレジ
スタ１３が設けてある。FIG. 5 (A) is a panel block diagram.
The display panel 10 is provided with a display screen 11, an X-axis shift register 12, and a Y-axis shift register 13.
【０００４】ディスプレイ画面１１には、ＥＬ電源が供
給されており、またＸ軸のシフトレジスタ１２には、シ
フトレジスタ電源の供給とＸ軸同期信号の入力が行われ
る。さらにＹ軸のシフトレジスタ１３には、シフトレジ
スタ電源の供給とＹ軸同期信号の入力が行われる。ま
た、Ｘ軸のシフトレジスタ１２の出力部に画像データ信
号の出力が設けてある。The display screen 11 is supplied with EL power, and the X-axis shift register 12 is supplied with shift register power and input with an X-axis synchronizing signal. Furthermore, the Y-axis shift register 13 is supplied with a shift register power supply and input with a Y-axis synchronizing signal. Further, an output of the X-axis shift register 12 is provided with an output of an image data signal.
【０００５】図５（Ｂ）は、図５（Ａ）のＡ部の拡大説
明図であり、ディスプレイ画面１１の一画素（点線の四
角で示す）は、トランジスタが２個、コンデンサが１
個、ＥＬ素子が１個より構成されている。FIG. 5B is an enlarged explanatory view of a portion A of FIG. 5A. One pixel (indicated by a dotted square) of the display screen 11 has two transistors and one capacitor.
And one EL element.
【０００６】この１画素の発光動作は、例えば、Ｙ軸の
シフトレジスタ１３で選択信号Ｙ１の出力があり、また
Ｘ軸のシフトレジスタ１２で選択信号Ｘ１の出力があっ
た場合、トランジスタＴｙ１１とトランジスタＴｘ１が
オンとなる。For example, when the Y-axis shift register 13 outputs the selection signal Y1 and the X-axis shift register 12 outputs the selection signal X1, the light emission operation of one pixel is performed by the transistor Ty11 and the transistor Ty11. Tx1 is turned on.
【０００７】このため、画像データ（映像信号）Ｄｉ
は、非線形素子（ＢＩＡＳ ＴＦＴ）Ｍ１１である薄膜
トランジスタのゲートに入力される。これにより、この
ゲート電圧に応じた電流がＥＬ電源から非線形素子Ｍ１
１のドレイン、ソース間に流れ、ＥＬ素子ＥＬ１１が発
光する。Therefore, the image data (video signal) Di
Is input to the gate of a thin film transistor which is a non-linear element (BIAS TFT) M11. As a result, a current corresponding to the gate voltage is supplied from the EL power source to the non-linear element M1.
It flows between the drain and the source of No. 1 and the EL element EL11 emits light.
【０００８】次のタイミングでは、Ｘ軸のシフトレジス
タ１２は、選択信号Ｘ１の出力をオフとし、選択信号Ｘ
２を出力することになるが、非線形素子Ｍ１１のゲート
電圧は、コンデンサＣ１１で保持されるため、次にこの
画素が選択されるまでＥＬ素子ＥＬ１１の前記発光は、
持続することになる。At the next timing, the X-axis shift register 12 turns off the output of the selection signal X1 and the selection signal X1.
However, since the gate voltage of the non-linear element M11 is held by the capacitor C11, the light emission of the EL element EL11 continues until the next pixel is selected.
It will continue.
【０００９】図６に一画素を抜き出して示す如く、一画
素毎のＥＬ素子を発光制御用の非線形素子（ＢＩＡＳ
ＴＦＴ）Ｍに直列接続し、この非線形素子（ＢＩＡＳ
ＴＦＴ）Ｍのゲート電極に信号保持用のキャパシタＣを
接続する。As shown by extracting one pixel in FIG. 6, an EL element for each pixel is a non-linear element (BIAS) for controlling light emission.
This nonlinear element (BIAS)
A signal holding capacitor C is connected to the gate electrode of TFT) M.
【００１０】そしてこの信号保持用のキャパシタＣにデ
ータ書き込み用の非線形素子（ＳＥＬＥＣＴ−ＳＷ用Ｔ
ＦＴ）Ｔｙを接続し、このデータ書き込み用の非線形素
子（ＳＥＬＥＣＴ−ＳＷ用ＴＦＴ）ＴｙにＹ座標選択信
号ＹｎとＸ座標選択信号により選択された画像データ
（映像信号）Ｄｉを印加する。A non-linear element for writing data (SELECT-SW T for the signal holding capacitor C is provided.
FT) Ty is connected and the image data (video signal) Di selected by the Y coordinate selection signal Yn and the X coordinate selection signal is applied to the non-linear element (SELECT-SW TFT) Ty for writing data.
【００１１】この画像データＤｉにより前記信号保持用
のキャパシタＣに電荷を蓄積し、この信号保持用のキャ
パシタＣに蓄積された電圧により前記発光制御用の非線
形素子（ＢＩＡＳ ＴＦＴ）Ｍに流れる電流を制御する
ことにより、ＥＬ素子の発光強度が決定される。（“Ａ
６×６−in 20−lpi Electroluminescent DisplayPan
el ”T.P.BRODY,FANG CHEN LUO,et.al.IEEE Trans.Elec
tron Devices,Vol.ED-22,No.9,Sept.1975、p739〜p749
参照）The image data Di accumulates charges in the signal holding capacitor C, and the voltage stored in the signal holding capacitor C causes a current to flow in the emission control nonlinear element (BIAS TFT) M. By controlling, the emission intensity of the EL element is determined. ("A
6 x 6-in 20-lpi Electroluminescent DisplayPan
el ”TPBRODY, FANG CHEN LUO, et.al.IEEE Trans.Elec
tron Devices, Vol.ED-22, No.9, Sept.1975, p739 ~ p749
reference)
【００１２】[0012]
【発明が解決しようとする課題】ところが、発光制御用
の非線形素子（ＢＩＡＳ ＴＦＴ）Ｍに流れる電流と、
キャパシタＣに蓄積された電圧との特性関係は必ずしも
一次比例の関係ではない。このため入力された映像信号
の大きさとＥＬ素子の発光輝度との関係が直線的でない
ため、入力映像信号に忠実にＥＬ素子の発光輝度が得ら
れないため、映像信号の大きさに忠実な発光輝度の再現
が難しかった。However, a current flowing through a non-linear element (BIAS TFT) M for controlling light emission,
The characteristic relationship with the voltage accumulated in the capacitor C is not necessarily linearly proportional. For this reason, since the relationship between the size of the input video signal and the light emission brightness of the EL element is not linear, the light emission brightness of the EL element cannot be obtained faithfully to the input video signal. It was difficult to reproduce the brightness.
【００１３】例えばこの非線形素子Ｍが電界効果トラン
ジスタ（ＴＦＴ）の場合、これに流れる電流は飽和領域
で次式のものとなる。 Ｉｄｓ＝（１／２）（Ｗ／Ｌ）μ0 Ｃ0 （Ｖｇｓ−Ｖｔ
ｈ）2 Ｉｄｓ ＴＦＴに流れる電流 Ｖｇｓ ゲートソース間電圧（キャパシタに蓄積された
電圧） Ｃ0 単位面積当りのゲート容量 μ0 移動度 Ｗ ＴＦＴのゲートのチャネル幅 Ｌ ＴＦＴのゲートのチャネル長 Ｖｔｈ ＴＦＴの閾値電圧 前記式より明らかな如く、ＩｄｓとＶｇｓとは比例関係
でなく、このため映像信号に比例した発光輝度を得るこ
とができなかった。For example, when the non-linear element M is a field effect transistor (TFT), the current flowing through it is in the saturation region and given by the following equation. Ids = (1/2) (W / L) μ 0 C 0 (Vgs-Vt
h) 2 Ids Current flowing in TFT Vgs Gate-source voltage (voltage accumulated in capacitor) C 0 Gate capacitance per unit area μ 0 Mobility W TFT gate channel width L TFT gate channel length Vth TFT Threshold Voltage As is clear from the above equation, Ids and Vgs are not in a proportional relationship, and therefore, it was not possible to obtain a light emission luminance in proportion to a video signal.
【００１４】本発明は、前記従来の課題を解決し、入力
電圧と非線形素子に流れる電流を一次比例関係にするこ
とで、入力映像信号に忠実な薄膜画素素子の輝度を得る
ことを目的とする。An object of the present invention is to solve the above-mentioned conventional problems and to obtain the luminance of a thin film pixel element faithful to an input video signal by making the input voltage and the current flowing through the non-linear element linearly proportional. .
【００１５】[0015]
【課題を解決するための手段】この目的を達成するた
め、本発明では図１（Ａ）に示す如く、この発光制御用
の非線形素子（ＢＩＡＳ ＴＦＴ）Ｍと任意の固定電位
ＣＯＭとの間に、電流−電圧特性が一次比例特性を有す
る負荷素子として抵抗Ｒｓを接続する。In order to achieve this object, according to the present invention, as shown in FIG. 1 (A), between the non-linear element (BIAS TFT) M for controlling light emission and an arbitrary fixed potential COM. , A resistor Rs is connected as a load element whose current-voltage characteristic has a linearly proportional characteristic.
【００１６】[0016]
【作用】前記一次比例特性を有する負荷素子としてソー
ス抵抗Ｒｓを接続したので、下記の如く負帰還が非線形
素子（ＢＩＡＳ ＴＦＴ）Ｍに係り、非線形素子Ｍに流
れる電流ＩｄｓとキャパシタＣに蓄積された電圧Ｖｇと
の間に一次比例特性の関係が得られる。Since the source resistance Rs is connected as the load element having the first-order proportional characteristic, the negative feedback is related to the non-linear element (BIAS TFT) M and accumulated in the current Ids flowing in the non-linear element M and the capacitor C as follows. A linear proportional relationship is obtained with the voltage Vg.
【００１７】即ち、図１（Ａ）において、非線形素子Ｍ
のゲート電圧Ｖｇが変化すると非線形素子Ｍに流れる電
流Ｉｄｓが変化し、Ｉｄｓ・Ｒｓつまり、非線形素子Ｍ
のソース電極と固定電位である共通電位ＣＯＭ間の電位
Ｖｓが変化する。これにもとづきＶｇ−ＶｓつまりＶｇ
ｓが変化し、非線形素子Ｍに流れる電流が変化する。こ
れにより負帰還が係りゲート電圧Ｖｇが大きくなったと
き、Ｉｄｓは増加するものの、ソースフォロア回路を構
成しているため負帰還が係りＶｇ−Ｉｄｓ特性は一次比
例特性が得られる。That is, in FIG. 1A, the nonlinear element M
When the gate voltage Vg of the non-linear element M changes, the current Ids flowing in the non-linear element M changes, and Ids · Rs, that is, the non-linear element M
The potential Vs between the source electrode and the common potential COM, which is a fixed potential, changes. Based on this, Vg-Vs, that is, Vg
s changes, and the current flowing through the nonlinear element M changes. As a result, when the negative feedback is involved and the gate voltage Vg is increased, Ids is increased, but since the source follower circuit is configured, the negative feedback is involved and the Vg-Ids characteristic is a linear proportional characteristic.
【００１８】[0018]
【実施例】本発明の一実施例を図１に基づき説明する。
本発明では、図１（Ａ）に示す如く、ＥＬ素子に直列接
続された発光制御用の非線形素子（ＢＩＡＳ ＴＦＴ）
Ｍと共通電位ＣＯＭとの間に、電流−電圧特性が一次比
例特性を有する負荷素子として抵抗Ｒｓを接続する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIG.
In the present invention, as shown in FIG. 1 (A), a non-linear element (BIAS TFT) for light emission control, which is connected in series with an EL element.
A resistor Rs is connected between M and the common potential COM as a load element whose current-voltage characteristic has a linear proportional characteristic.
【００１９】これにより、非線形素子Ｍのゲート電圧Ｖ
ｇ、つまりコンデンサＣの充電電圧が大きくなるとき、
図１（Ｂ）に示す如く、この非線形素子Ｍに流れる電流
Ｉｄｓが増加する。この電流Ｉｄｓが増大することによ
り抵抗Ｒｓにおける電圧降下が大きくなり、ソース電位
Ｖｓが上昇する。As a result, the gate voltage V of the nonlinear element M is
g, that is, when the charging voltage of the capacitor C increases,
As shown in FIG. 1B, the current Ids flowing through the non-linear element M increases. As the current Ids increases, the voltage drop across the resistor Rs increases and the source potential Vs rises.
【００２０】これにより下記の式で得られるソースゲー
ト間電圧Ｖｇｓ、Ｖｇｓ＝Ｖｇ−Ｖｓも、ソース電位Ｖ
ｓが上昇するため小さくなり、これによりＢＩＡＳ Ｔ
ＦＴに流れる電流Ｉｄｓが減少する。このようにして負
帰還がＢＩＡＳ ＴＦＴにかかるので、Ｉｄｓ対Ｖｇ特
性は一次比例の関係を持つ範囲を得ることができる。As a result, the source-gate voltages Vgs and Vgs = Vg-Vs obtained by the following equation are also calculated as the source potential V
As s rises, it becomes smaller, which causes BIAS T
The current Ids flowing through the FT decreases. In this way, since negative feedback is applied to the BIAS TFT, it is possible to obtain a range in which the Ids vs. Vg characteristic has a linearly proportional relationship.
【００２１】この場合、前記発光制御用の非線形素子
（ＢＩＡＳ ＴＦＴ）Ｍのソース電極と任意の共通電位
ＣＯＭの間に、発光制御用の非線形素子の相互コンダク
タンスの逆数よりも十分に大きな抵抗〔１０倍以上〜１
Ｔ（テラ＝１０12）Ω以下〕を配したことにより負帰還
が係り、発光制御用の非線形素子Ｍに流れる電流Ｉｄｓ
とキャパシタＣに蓄積された電圧との間に一次比例の関
係を持つ範囲を作ることができる。In this case, a resistance [10] sufficiently larger than the reciprocal of the mutual conductance of the nonlinear element for light emission control is provided between the source electrode of the nonlinear element for light emission control (BIAS TFT) M and an arbitrary common potential COM. More than twice ~ 1
T (tera = 10 12 ΩΩ or less), negative feedback is involved, and the current Ids flowing through the nonlinear element M for light emission control
It is possible to create a range having a linearly proportional relationship between and the voltage stored in the capacitor C.
【００２２】例えばこの非線形素子Ｍが電界効果トラン
ジスタ（ＴＦＴ：薄膜トランジスタ）の場合、ソース電
位ＶｓとこのＴＦＴに流れる電流Ｉｄｓは、飽和領域で
次式の通りとなる。For example, when the non-linear element M is a field effect transistor (TFT: thin film transistor), the source potential Vs and the current Ids flowing in the TFT are as follows in the saturation region.
【００２３】 Ｖｓ＝ＲｓＩｄｓ ・・・・・・・・・・・・・・・・・・・・・・ Ｉｄｓ＝（１／２）（Ｗ／Ｌ）μ0 Ｃ0 （Ｖｇ−Ｖｓ−Ｖｔｈ）2 ・・ Ｉｄｓ ＴＦＴに流れる電流 Ｖｇ キャパシタＣに蓄積された電圧 Ｖｓ ソース電位 Ｖｔｈ ＴＦＴの閾値電圧 Ｒｓ 電流−電圧特性が一次比例特性を有する抵抗 Ｃ0 単位面積当りのゲート容量 μ0 移動度 Ｗ ＴＦＴのゲートのチャネル幅 Ｌ ＴＦＴのゲートのチャネル長 この、の両式を微分すると、 ΔＶｓ＝ＲｓΔＩｄｓ ・・・・・・・・・・・・・・・・・・・・ ΔＩｄｓ＝ｇｍ（ΔＶｇ−ΔＶｓ）・・・・・・・・・・・・・・・・ ここで、ｇｍはＴＦＴの相互コンダクタンス〔ｇｍ＝
（Ｗ／Ｌ）μ0 Ｃ0 （Ｖｇ−Ｖｓ−Ｖｔｈ）〕である。Vs = RsIds ... Ids = (1/2) (W / L) μ 0 C 0 (Vg-Vs-Vth ) 2 ... Ids Current flowing in TFT Vg Voltage accumulated in capacitor C Vs Source potential Vth TFT threshold voltage Rs Resistance having current-voltage characteristic of first-order proportional characteristic C 0 Gate capacitance per unit area μ 0 Mobility W The channel width of the gate of the TFT L The channel length of the gate of the TFT When these two equations are differentiated, ΔVs = RsΔIds ..... ΔIds = gm (ΔVg -ΔVs) ... where gm is the transconductance of the TFT [gm =
(W / L) μ 0 C 0 (Vg-Vs-Vth)].
【００２４】式より ΔＩｄｓ＝ΔＶｓ／Ｒｓ ・・・・・・・・・・・・・・・・・・・ 式を式に代入し、 ΔＶｓ／Ｒｓ＝ｇｍ（ΔＶｇ−ΔＶｓ） これを変形し、 （１＋ｇｍＲｓ）ΔＶｓ＝ｇｍＲｓΔＶｇ これにより、 ΔＶｓ＝（ｇｍＲｓ）／（１＋ｇｍＲｓ）・ΔＶｇ ここで、抵抗Ｒｓが発光制御用の非線形素子（ＴＦＴ）
の相互コンダクタンスｇｍの逆数より十分大きな場合、
即ち、ｇｍＲｓ＞＞１のとき、 ΔＶｓ≒ΔＶｇ これにより式から、 ΔＩｄｓ＝（１／Ｒｓ）ΔＶｓ＝（１／Ｒｓ）ΔＶｇ・・・・・・・・ この式の関係により、ＥＬ素子に流れる電流Ｉｄｓと
ゲート電圧Ｖｇとが一次比例の関係となっていることが
わかる。From the formula, ΔIds = ΔVs / Rs ... Substituting the formula into the formula, ΔVs / Rs = gm (ΔVg−ΔVs) , (1 + gmRs) ΔVs = gmRsΔVg As a result, ΔVs = (gmRs) / (1 + gmRs) · ΔVg where the resistance Rs is a nonlinear element (TFT) for controlling light emission.
Is sufficiently larger than the reciprocal of the mutual conductance gm of
That is, when gmRs >> 1, ΔVs≈ΔVg, which leads to ΔIds = (1 / Rs) ΔVs = (1 / Rs) ΔVg. It can be seen that the current Ids and the gate voltage Vg have a linearly proportional relationship.
【００２５】ところで、図１における抵抗Ｒｓは個別の
抵抗体を使用せずに、ソース電極を共通電位ＣＯＭに接
続する導線を、例えばポリシリコンの如き高抵抗な薄膜
により作成することもできる。この場合の抵抗値の制御
は、そのパターン寸法（例えば、幅、長さ、厚さ等）を
調節することにより行うことができる。By the way, as the resistor Rs in FIG. 1, a conductive wire for connecting the source electrode to the common potential COM can be formed by a high-resistance thin film such as polysilicon without using an individual resistor. Control of the resistance value in this case can be performed by adjusting the pattern dimensions (for example, width, length, thickness, etc.).
【００２６】また前記ソース電極に付加する抵抗は、非
線形素子（ＢＩＡＳ ＴＦＴ）に必ず存在する寄生抵
抗、例えばソース抵抗、オフセット領域（ドーピングの
ない領域）等を使用して作ってもよい。このときの抵抗
値の制御は、ドーピング量、オフセット距離、電極のパ
ターン形状等により行う。図２（Ａ）に示す抵抗Ｒｓ
は、この寄生抵抗を等価的に示したものである。The resistance to be added to the source electrode may be formed by using a parasitic resistance which is always present in the non-linear element (BIAS TFT), for example, a source resistance, an offset region (a region without doping) or the like. At this time, the resistance value is controlled by the doping amount, the offset distance, the electrode pattern shape, and the like. Resistance Rs shown in FIG.
Shows equivalently this parasitic resistance.
【００２７】図２（Ａ）において、非線形素子（ＢＩＡ
Ｓ ＴＦＴ）ＭとしてＰチャネル電界効果トランジスタ
を使用し、この非線形素子Ｍのドレイン電極と任意の共
通電位ＣＯＭの間に、ＥＬ素子が設けてある。また、ゲ
ート電極と任意の固定電位ＶＤとの間に信号保持用のキ
ャパシタＣが設けてある。In FIG. 2A, a nonlinear element (BIA
A P-channel field effect transistor is used as STFT) M, and an EL element is provided between the drain electrode of this nonlinear element M and an arbitrary common potential COM. Further, a signal holding capacitor C is provided between the gate electrode and an arbitrary fixed potential VD.
【００２８】この場合も寄生抵抗である抵抗Ｒｓを発光
制御用の非線形素子Ｍの相互コンダクタンスの逆数より
も十分に大きな抵抗（１０倍以上〜１ＴΩ以下）とする
ことにより負帰還が係り、非線形素子Ｍに流れる電流Ｉ
ｄｓとキャパシタＣに蓄積された電圧との間に一次比例
の関係を持つ範囲を作ることができる。Also in this case, the resistance Rs, which is a parasitic resistance, is set to a resistance (10 times or more to 1 TΩ or less) sufficiently larger than the reciprocal of the mutual conductance of the non-linear element M for controlling light emission. Current I flowing in M
It is possible to create a range having a linearly proportional relationship between ds and the voltage stored in the capacitor C.
【００２９】図２（Ｂ）は非線形素子Ｍの寄生抵抗の一
例を示しており、上からドレイン電極Ｄ、ドレインパタ
ーン、ゲート電極Ｇ、ソースパターン、ソース電極Ｓを
示している。このソースパターンの一部にオフセット領
域ＯＰを設け、抵抗Ｒｓを作ることができる。勿論この
ソースパターンの幅、長さ、厚さ等を調節して抵抗Ｒｓ
を作るようにしてもよい。FIG. 2B shows an example of the parasitic resistance of the nonlinear element M, and shows the drain electrode D, the drain pattern, the gate electrode G, the source pattern, and the source electrode S from the top. The resistance Rs can be formed by providing an offset region OP in a part of this source pattern. Of course, the resistance Rs can be adjusted by adjusting the width, length, thickness, etc. of this source pattern.
May be made.
【００３０】さらに前記ソース電極に付加する抵抗は、
薄膜画素素子に必ず発生する寄生抵抗を用いてもよく、
図３（Ａ）に示す抵抗Ｒｓは、この寄生抵抗を等価的に
示したものである。Further, the resistance added to the source electrode is
You may use the parasitic resistance that always occurs in the thin film pixel element,
The resistance Rs shown in FIG. 3A is equivalent to this parasitic resistance.
【００３１】図３（Ａ）において、非線形素子（ＢＩＡ
Ｓ ＴＦＴ）ＭとしてＰチャネル電界効果トランジスタ
を使用し、この非線形素子Ｍのゲート電極と固定電位Ｖ
Ｄとの間に信号保持用のキャパシタＣが設けてある。ま
た、ソース電極と固定電位ＶＤとの間に薄膜画素素子で
あるＥＬ素子とその寄生抵抗Ｒｓが設けてある。In FIG. 3A, a nonlinear element (BIA
A P-channel field effect transistor is used as STFT) M, and the gate electrode of this non-linear element M and the fixed potential V
A capacitor C for holding a signal is provided between the capacitor C and D. An EL element which is a thin film pixel element and its parasitic resistance Rs are provided between the source electrode and the fixed potential VD.
【００３２】この場合も寄生抵抗である抵抗Ｒｓを発光
制御用の非線形素子Ｍの相互コンダクタンスの逆数より
も十分に大きな抵抗（１０倍以上〜１ＴΩ以下）とする
ことにより負帰還が係り、非線形素子Ｍに流れる電流Ｉ
ｄｓとキャパシタＣに蓄積された電圧との間に一次比例
の関係を持つ範囲を作ることができる。Also in this case, the resistance Rs, which is a parasitic resistance, is set to a resistance (10 times or more to 1 TΩ or less) sufficiently larger than the reciprocal of the mutual conductance of the nonlinear element M for controlling light emission, so that negative feedback is involved, and the nonlinear element is affected. Current I flowing in M
It is possible to create a range having a linearly proportional relationship between ds and the voltage stored in the capacitor C.
【００３３】図３（Ｂ）は薄膜画素素子の一例（有機Ｅ
Ｌ発光素子）を示す図であり、寄生抵抗としてこの図に
示す如く、抵抗層１０２を使用してもよい。この場合も
その等価回路は図３（Ａ）に示す通りである。なお図３
（Ｂ）に示す有機ＥＬ発光素子において、１０１はＭｇ
Ａｇ等の陰極、１０３は電子注入輸送層、１０４は発光
層、１０５は正孔注入輸送層、１０６は透明電極であ
る。FIG. 3B shows an example of a thin film pixel element (organic E
L light emitting element), and a resistance layer 102 may be used as a parasitic resistance as shown in this figure. Also in this case, the equivalent circuit is as shown in FIG. FIG. 3
In the organic EL light emitting device shown in (B), 101 is Mg
A cathode such as Ag, 103 is an electron injecting and transporting layer, 104 is a light emitting layer, 105 is a hole injecting and transporting layer, and 106 is a transparent electrode.
【００３４】この寄生抵抗の値を制御するには、抵抗層
１０２としてポリシリコン薄膜、アモルファスシリコン
薄膜、高抵抗有機薄膜等の膜厚で制御を行う。勿論薄膜
画素素子の電流−電圧特性が一次比例する場合には、こ
れを用いてもよい。In order to control the value of this parasitic resistance, the resistance layer 102 is controlled by a film thickness of a polysilicon thin film, an amorphous silicon thin film, a high resistance organic thin film or the like. Of course, this may be used when the current-voltage characteristics of the thin film pixel element are linearly proportional.
【００３５】また、前記ソース電極に付加する抵抗は非
線形素子の出力抵抗を用いてもよい。図４（Ａ）は非線
形素子である負荷ＴＦＴ（ＬＯＡＤ ＴＦＴ）の出力抵
抗を用いたときを示したものである。ＬＯＡＤ ＴＦＴ
のゲート電極には抵抗Ｒ１、Ｒ２で分圧された一定の電
位が加えられている。The resistance added to the source electrode may be the output resistance of a non-linear element. FIG. 4A shows a case where the output resistance of a load TFT (LOAD TFT) which is a non-linear element is used. LOAD TFT
A constant potential divided by resistors R1 and R2 is applied to the gate electrode of.
【００３６】図４（Ｂ）はこの時のＬＯＡＤ ＴＦＴの
ＶDS−Ｉｄｓ特性（ドレインソース間の電圧電流特性）
を示し、ＶDSに一定以上の値が加わるとき（飽和領
域）、Ｖ DS−Ｉｄｓの関係は一次比例となりＬＯＡＤ
ＴＦＴが抵抗と見なせることを表している。なお、ここ
でのＶDSはＬＯＡＤ ＴＦＴのドレインソース電極間に
かかる電圧を表している。この出力抵抗値はＬＯＡＤ
ＴＦＴに印加される電圧、すなわち抵抗Ｒ１，Ｒ２の抵
抗比、及びＬＯＡＤ ＴＦＴのチャネル長で制御を行う
ものである。またＬＯＡＤ ＴＦＴのゲート電極に加え
る一定の電位は抵抗Ｒ１，Ｒ２を使用しないで外部から
一定の電位を与える等の他の手段を用いることもでき
る。FIG. 4B shows the LOAD TFT at this time.
VDS-Ids characteristics (voltage-current characteristics between drain and source)
And VDSWhen a certain value is added to (saturation region
Area), V DS-Ids is linearly proportional and LOAD
This means that the TFT can be regarded as a resistance. In addition, here
At VDSIs between the drain and source electrodes of the LOAD TFT
This voltage is shown. This output resistance value is LOAD
The voltage applied to the TFT, that is, the resistance of the resistors R1 and R2.
Control with coercive ratio and channel length of LOAD TFT
Things. In addition to the gate electrode of LOAD TFT
A constant potential from outside without using resistors R1 and R2
Other means such as applying a constant potential can also be used
You.
【００３７】このように、ＬＯＡＤ ＴＦＴのゲート電
極に加える電位を制御することにより出力抵抗値の制御
を容易に行うことができ、しかも、大きな抵抗値を小さ
な面積で作ることができる。As described above, the output resistance value can be easily controlled by controlling the potential applied to the gate electrode of the LOAD TFT, and a large resistance value can be formed in a small area.
【００３８】なお、前記実施例では非線形素子として薄
膜で製造したＴＦＴを用いた場合の説明をしたが、これ
に限定されるものではなく、他の製法で製造した非線形
素子を用いることもできる。In the above embodiment, the case where the thin film TFT is used as the non-linear element has been described, but the present invention is not limited to this, and the non-linear element manufactured by another manufacturing method may be used.
【００３９】[0039]
【発明の効果】以上説明したように、本発明によれば次
のような効果がある。 ：請求項１記載の本発明によれば入力電圧と非線形素
子に流れる電流を一次比例関係に構成することができる
ので、入力映像信号に忠実な薄膜画素素子の輝度を得る
ことができる。As described above, the present invention has the following effects. According to the first aspect of the present invention, since the input voltage and the current flowing through the non-linear element can be configured in a linear proportional relationship, it is possible to obtain the luminance of the thin film pixel element that is faithful to the input video signal.
【００４０】：請求項２記載の本発明によれば高抵抗
導線を使用して前記一次比例関係を得ることができるの
で、特別な抵抗を必要とせず、入力映像信号に忠実な薄
膜画素素子の輝度を得ることができる。According to the present invention as set forth in claim 2, since the first-order proportional relationship can be obtained by using a high resistance conductive wire, a special resistance is not required and a thin film pixel element faithful to an input video signal can be obtained. The brightness can be obtained.
【００４１】：請求項３記載の本発明によれば非線形
素子の寄生抵抗を用いて前記一次比例関係を得ることが
できるので、これまた特別な抵抗を必要とせず、入力映
像信号に忠実な薄膜画素素子の輝度を得ることができ
る。According to the third aspect of the present invention, the first-order proportional relationship can be obtained by using the parasitic resistance of the non-linear element, so that no special resistance is required and a thin film faithful to the input video signal. The brightness of the pixel element can be obtained.
【００４２】：請求項４記載の本発明によれば薄膜画
素素子の寄生抵抗を用いたので、特別な抵抗を必要とせ
ず、入力映像信号に忠実な薄膜画素素子の輝度を得るこ
とができる。According to the fourth aspect of the present invention, since the parasitic resistance of the thin film pixel element is used, it is possible to obtain the luminance of the thin film pixel element faithful to the input video signal without requiring a special resistance.
【００４３】：請求項５記載の本発明によれば薄膜画
素素子に抵抗薄膜を形成したので、非常に簡単な構成
で、入力映像信号に忠実な薄膜画素素子の輝度を得るこ
とができる。According to the fifth aspect of the present invention, since the resistance thin film is formed on the thin film pixel element, the brightness of the thin film pixel element faithful to the input video signal can be obtained with a very simple structure.
【００４４】：請求項６記載の本発明によれば負荷素
子として非線形素子の出力抵抗を用いたので出力抵抗の
制御が容易に行うことができ、かつ、大きな抵抗値を小
さな面積で作ることができる。According to the sixth aspect of the present invention, since the output resistance of the non-linear element is used as the load element, the output resistance can be easily controlled, and a large resistance value can be formed in a small area. it can.
【図１】本発明の原理説明図である。FIG. 1 is a diagram illustrating the principle of the present invention.
【図２】実施例における非線形素子の寄生抵抗を用いる
場合の説明図である。FIG. 2 is an explanatory diagram when a parasitic resistance of a nonlinear element is used in the example.
【図３】実施例における薄膜画素素子の寄生抵抗を用い
る場合の説明図である。FIG. 3 is an explanatory diagram when using a parasitic resistance of a thin film pixel element in an example.
【図４】実施例における非線形素子の出力抵抗を用いる
場合の説明図である。FIG. 4 is an explanatory diagram in the case of using an output resistance of a nonlinear element in the example.
【図５】従来例の説明図（１）である。FIG. 5 is an explanatory diagram (1) of a conventional example.
【図６】従来例の説明図（２）である。FIG. 6 is an explanatory diagram (2) of a conventional example.
ＥＬ 薄膜画素素子 Ｍ 非線形素子 Ｃ キャパシタ Ｒｓ 負荷素子 Ｔｙ 非線形素子 Ｙｎ Ｙ座標選択信号 Ｄｉ 画像データ ＣＯＭ 共通電位（固定電位） ＶＤ 固定電位 Ｖｓ ソース電位 Ｖｇ ゲート電圧 Ｖｇｓ ソースゲート間電圧 Ｉｄｓ 非線形素子Ｍに流れる電流 EL Thin film pixel element M Non-linear element C Capacitor Rs Load element Ty Non-linear element Yn Y coordinate selection signal Di Image data COM Common potential (fixed potential) VD Fixed potential Vs Source potential Vg Gate voltage Vgs Source gate voltage Ids Flow to non-linear element M Electric current
Claims (6)
素子の発光制御用の非線形素子と、該非線形素子のゲー
ト電極に接続された信号保持用のキャパシタと、該キャ
パシタへのデータ書き込み用の非線形素子と、前記発光
制御用の非線形素子と任意の固定電位との間に、電流−
電圧特性が一次比例である負荷素子とを有することを特
徴とする画像表示装置。1. A thin film pixel element for each pixel, a non-linear element for controlling light emission of the thin film pixel element, a signal holding capacitor connected to a gate electrode of the non-linear element, and data writing to the capacitor. Between the non-linear element for controlling the light emission and the non-linear element for controlling the light emission and any fixed potential.
An image display device, comprising: a load element whose voltage characteristic is linearly proportional.
特徴とする請求項１記載の画像表示装置。2. The image display device according to claim 1, wherein the load element is a high resistance wire.
抗であることを特徴とする請求項１記載の画像表示装
置。3. The image display device according to claim 1, wherein the load element is a parasitic resistance of the nonlinear element.
抵抗であることを特徴とする請求項１記載の画像表示装
置。4. The image display device according to claim 1, wherein the load element is a parasitic resistance of the thin film pixel element.
寄生抵抗であり、該寄生抵抗は抵抗薄膜で形成されたも
のであることを特徴とする請求項１記載の画像表示装
置。5. The image display device according to claim 1, wherein the load element is the thin film pixel element and its parasitic resistance, and the parasitic resistance is formed of a resistive thin film.
あることを特徴とする請求項１記載の画像表示装置。6. The image display device according to claim 1, wherein the load element is an output resistance of a non-linear element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16842895A JP3636777B2 (en) | 1995-07-04 | 1995-07-04 | Image display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16842895A JP3636777B2 (en) | 1995-07-04 | 1995-07-04 | Image display device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004337195A Division JP4175569B2 (en) | 2004-11-22 | 2004-11-22 | Image display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0916123A true JPH0916123A (en) | 1997-01-17 |
| JP3636777B2 JP3636777B2 (en) | 2005-04-06 |
Family
ID=15867944
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16842895A Expired - Fee Related JP3636777B2 (en) | 1995-07-04 | 1995-07-04 | Image display device |
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| Country | Link |
|---|---|
| JP (1) | JP3636777B2 (en) |
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