JPH09154152A - Sampling clock regeneration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a clock signal with a fixed phase relation to a reference frequency signal with a simple circuit configuration and also to reduce a quantization phase error. SOLUTION: A digital burst signal obtained from an A/D converter 22 is given to a sampling circuit 28 and a band elimination filter(BEF) 30. Then sampling circuit 28 samples the burst signal by a subcarrier frequency or at a period shifting the frequency by a prescribed amount. The sample data SI sampled by the sampling circuit 28 and reference pedestal data REF from a pedestal data generating circuit 34 are compared by a comparator 32. The comparator 32 provides an output of a high or a low level signal to a low pass filter 48 only for a burst period when both data SI, REF have a phase difference. A capacitor of the low pass filter 48 is charged or discharged in response to the signal of the high level or the low level, thereby controlling an oscillated frequency of a voltage controlled oscillator 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sampling clock reproducing circuit, and more particularly to a sampling clock reproducing circuit for generating a sampling clock for A / D converting a color video signal in a VTR, a TV receiver or the like.

[0002]

2. Description of the Related Art A composite color video signal is converted into its color bar.
In order to sample in synchronization with the strike signal, conventionally,
A so-called burst PLL (phase synchronization loop) is configured,
The sampling clock is obtained from the output of the PLL. That is, referring to FIG. 5, the input composite color video signal is given to the A / D converter 3 through the low-pass filter 1 for removing aliasing noise and the pedestal clamp (DC reproduction) circuit 2, and the PLL is supplied.
A / D conversion is performed based on the sampling clock of 4 Fsc (four times the frequency of the subcarrier) created in 4.

In the PLL 4, the composite color video signal is given to the bandpass filter 4a and separated into Y / C. The color signal component (burst signal) from the bandpass filter 4a is given to the phase comparator 4b. The composite color video signal is also supplied to the sync separation circuit 4c.
The burst gate pulse generation circuit 4d creates a burst gate pulse based on the horizontal synchronization signal output from the synchronization separation circuit 4c, and the phase comparator 4b is activated by this burst gate pulse. Therefore, the phase comparator 4b outputs the oscillation signal of the voltage controlled oscillator (VCO) 4e having the oscillation frequency of 4Fsc to 1 during the burst gate pulse period.
The phase of the output of the frequency dividing circuit 4f that divides the frequency by / N (for example, 1/4) is compared with the phase of the burst signal. Phase comparator 4
The output of b is supplied to the voltage controlled oscillator 4f via the low pass filter 4g. In this way, burst PL
L4 is configured.

The output of the A / D converter 3 is processed by a three-dimensional Y / C separation circuit 5a in a digital signal processor (DSP) 5, and then the D / A converter 6a.
And 6b, and again converted into an analog luminance signal and an analog color signal. D / A converters 6a and 6
The output of b is further given to a demodulation circuit (not shown) and demodulated by analog signal processing.

In the prior art shown in FIG. 5, an uncertain phase between the sampling clock and the burst signal given to the A / D converter 3 due to the influence of temperature drift of the bandpass filter 4a, the pedestal clamp circuit 2 and the like. There may be an error. Therefore, color demodulation by digital signal processing cannot be performed well, and as shown in FIG.
Since the color demodulation is performed after the conversion into the analog color signal by the converter 6b, there are drawbacks that the circuit configuration becomes complicated and the signal processing efficiency is poor.

The drawback of the prior art shown in FIG. 5 that an uncertain phase error occurs between the sampling clock and the burst signal can be eliminated by the prior art shown in FIG. In the prior art of FIG. 6, the DSP 5 is provided with the phase comparator 7 and the phase shifter 8, and the burst signal (burst data) converted into the digital signal by the A / D converter 3 and the sampling clock from the voltage controlled oscillator 4e are used. Is detected by the phase comparator 7, and the phase of the sampling clock from the voltage controlled oscillator 4e is changed by the phase shifter 8 according to the detected phase error and given to the three-dimensional Y / C separation circuit 5a.

[0007]

However, in the prior art of FIG. 6, it is necessary to average the burst data in one field, for example, in order to eliminate the influence of noise. However, a large capacity memory for accumulating a large amount of burst data was required. Further, when the number of quantization bits is insufficient, there is a drawback that the static phase error, that is, the control phase error due to the quantization error becomes large.

Therefore, the main object of the present invention is to obtain a clock signal synchronized with the digitized burst signal with a simple circuit configuration and to suppress the quantization phase error as much as possible. A sampling clock recovery circuit is provided.

[0009]

SUMMARY OF THE INVENTION The present invention is a variable frequency oscillator whose oscillation frequency is changed by a control signal,
A phase shift means for shifting the oscillation signal from the variable frequency oscillator by a predetermined amount, a switching means for switching the output from the phase shift means and the oscillation signal at a constant cycle, and outputting the television signal based on the output signal from the switching means. An A / D converter for A / D converting at least an intermittent reference frequency signal, a sampling means for sampling the output from the A / D converter with a signal selected by the switching means, and outputting sample data, Comparison signal data generating means for generating comparison signal data having a constant level at least during the comparison period, and sample data
The sampling clock regeneration circuit includes a comparison means for comparing the comparison signal data with the comparison signal data, and a control signal generation means for giving a control signal to the variable frequency oscillator during the reference frequency signal period based on the output of the comparison means.

[0010]

[Operation] In the phase shift means, the signal from the variable frequency oscillator is generated.
The phase of the vibration signal is shifted by a predetermined amount. A / D converter is off
The output signal from the switching means is an intermittent basis of the television signal.
Quasi-frequency signal (burst signal) is A / D converted,
Output data. Burst data is sampled
By means of the signal selected by the switching means.
Is pulled. In other words, digitally converted video data
-Is the reference frequency or subcarrier frequency (F_SC)
Or the period of the output signal from the phase shifting means (F ' _SC) Sump
To be ringed. That is, the switching means has a variable frequency oscillation.
Signal from the instrument (F_SC) And the output signal from the phase shifting means
(F '_SC) And a fixed period, for example, switching every line
I can.

The comparison means compares the sample data (SI) from the sampling means with the reference pedestal data (REF) from the pedestal data generating means (comparison signal data output means). When the pedestal data (REF) is larger (advanced) than the sample data (SI), the comparing means outputs, for example, a high level signal, and the high level signal is, for example, an analog low-pass signal. The control voltage generating means including a filter supplies the variable frequency oscillator as a control signal. Specifically, the high-level signal charges the capacitor of the low-pass filter, and a control signal for reducing the oscillation frequency of the variable frequency oscillator is output.

On the other hand, when the pedestal data (REF) is small (lagging) with respect to the sample data (SI), for example, a low level signal is output from the comparing means, and The low pass filter capacitor is discharged. As a result, a control signal for increasing the oscillation frequency of the variable frequency oscillator is output from the low pass filter.

[0013]

According to the present invention, it is possible to generate a clock signal having a fixed phase relationship with a digitized reference frequency signal with a simple circuit configuration. Further, the quantization phase error can be reduced. The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a sampling clock recovery circuit 10 of this embodiment includes a PLL 12 and a DSP 14. The composite color video signal input from the input terminal 16 is supplied to the low-pass filter 18, and in order to prevent aliasing distortion that occurs when the analog signal is digitally converted therein, the composite color video signal is input at a frequency lower than half the sampling frequency (Nyquist frequency). High frequency video signals are removed. That is, the low-pass filter 18 corresponds to a Y / C separation circuit, and the luminance signal component of the input video signal is output from the low-pass filter 18 and given to the clamp circuit 20.

The clamp circuit 20 is a so-called pedestal clamp that clamps at the pedestal level, and adjusts the black level of the input video signal. The video signal (luminance signal) with a fixed pedestal level is A /
An oscillation signal (4) from the voltage controlled oscillator 24 included in the PLL 12 is provided to the D converter 22.
F _SC ), or a signal obtained by phase-shifting the oscillation signal by the phase shifter 25 by a predetermined amount, and digitally converted.

The digitally converted video signal (video data) is given to a three-dimensional Y / C separation circuit 26 included in the DSP 14, and also given to a sample circuit 28 and a band elimination filter (BEF) 30 in the same DSP 14. To be In the three-dimensional Y / C separation circuit 26, the video data is Y / C according to the clock signal (4F _SC = 14.3 MHz) from the voltage controlled oscillator 24 (phase shifter 25).
Separated. Luminance signal (Y) from the Y / C separation circuit 26
And the color signal (C) is supplied to the D / A converters 31a and 31a.
It is given to b and converted into analog.

Digital input to sample circuit 28
The video signal has a subcarrier frequency (F _SC), Or this
A signal in which the subcarrier frequency is phase-shifted by the phase shifter 25 by a predetermined amount.
(F ' _SC). Sample circuit 28
To the comparator 32, sample data (SI)
Is output. This phase shifter 25 determines the range of quantization phase error.
It has a fixed amount of phase shift determined within. And the comparator 3
In 2, the sample data (SI) and the pedestal
Reference pedestal output from the data generation circuit 34
The data (REF) is compared.

The pedestal data (REF) is fixed (reference) data preset in the ROM of the pedestal data generation circuit 34, and is supplied to the comparators 32 and 36. This pedestal data (R
In addition to EF), the luminance signal data from the band elimination filter (BEF) 30 is input and these two data are compared. The comparator 36 outputs a signal in response to the difference between the luminance signal data and the reference pedestal data (REF).

As comparison signal data for comparison with the sample data (SI) from the sample circuit 28,
Not limited to the pedestal data (REF) described above, for example, a sample circuit (not shown) is provided in the DSP 14 separately from the sample circuit 28, and in this sample circuit, the phase is different from the subcarrier period (F _SC ) by 180 °. It is also possible to sample the video data at a cycle and compare the sampled data with the sampled data (SI) from the sampling circuit 28.

The signal from the comparator 36 is given to the feedback circuit 38, and the output from the comparator 36 is given to the clamp circuit 20 only during the burst period. That is, the feedback circuit 38
Is an AND gate 40a which receives the burst gate pulse (BGP) from the burst gate pulse generating circuit 46 and the inversion of the signal from the comparator 36, and an AND gate 40a.
Three-state switch 42 capable of switching among three states by the output of a
The three-state switch 42a becomes conductive only during the burst period when a difference is generated between the luminance signal data and the reference pedestal data (REF) including a. And
The output signal from the comparator 36 is negatively fed back to the clamp circuit 20.

More specifically, when the comparator 36 compares the luminance signal data from the band elimination filter 30 with the pedestal data (REF), and a difference (voltage difference) occurs between the two data. For example, the comparator 36 outputs a high-level or low-level signal in response to the difference. This signal is given to the clamp circuit 20 via the three-state switch 42a. This signal charges or discharges the capacitor of the clamp circuit 20. That is, the clamp circuit 20 includes a capacitor as shown in FIG. 1, and the clamp level of the clamp circuit 20 changes due to such negative feedback. Therefore,
The pedestal data of the video data after A / D conversion is fixed to the reference pedestal data (REF). Thus, since the pedestal level after digital conversion can be set accurately, most of the clock generation circuit can be digitized, and the reproduction phase of the sampling clock can be set precisely.

The luminance signal data processed by the band elimination filter 30 is applied to the sync separation circuit 44. A burst gate pulse generating circuit 46 generates a burst gate pulse based on the horizontal synchronizing signal from the sync separation circuit 44. That is, the burst gate pulse generation circuit 46
Includes a counter (not shown) that counts the time from the horizontal synchronizing signal and a decoder (not shown) that decodes the output from this counter.

The horizontal sync signal from the sync separation circuit 44 is given to a frequency divider circuit 45, where it is divided into, for example, 1/2, and input to the phase shifter 25 as an enable signal (E). As a result, the phase shifter 25 outputs the clock signal (4
F _SC ) and a signal (4F ′ _SC ) obtained by shifting the clock signal by a predetermined amount are output.

That is, referring to FIG. 2, the 4F _SC clock signal input to the phase shifter 25 is phase-shifted by, for example, N (even stage) inverters. In addition, as shown in FIG. 2, the clock signal phase-shifted by the N / 2 inverters is used as a reference clock signal in three-dimensional Y /
C separation circuit 26 and D / A converters 31a and 31b
Given to. The phase-shifted signal (4F ′ _SC ) and the through signal (4F _SC ) are transferred by the changeover switch 27.
In accordance with the output signal (E) from the frequency dividing circuit 45, it is alternately switched for a fixed period, for example, for each line. The signal selected by the changeover switch 27 is given to the A / D converter 22, and the video signal is digitally converted based on the signal. The signal from the change-over switch 27 is also divided into 1/4 by the frequency dividing circuit 29 and then given to the sampling circuit 28 to sample the video data.

Further, referring to FIG. 3, FIG. 3 (A) shows that after the A / D conversion, the data in the amplitude direction is 4 bits and the sampling clock (F _SC ) is sufficiently large. -Indicates the data. The burst data is shown in FIG.
Quantized phase error (α) is generally included in the amplitude direction data (the number of bits).
The smaller the number, the larger.

Therefore, as described above, the phase shifter 25 is turned on.
It is provided in the latter stage of the pressure controlled oscillator 24, and is shown in FIG.
As shown in (D), the phase shifter 25 has a constant period, for example,
Amount of clock signal from voltage controlled oscillator 24 in horizontal cycle
Phase shift within a range (β) smaller than the sub-phase error (α)
Let The clock signal (4F ') thus phase-shifted
_SC) Is output as an enable signal from the frequency dividing circuit 45.
According to the signal (E) obtained by dividing the horizontal synchronizing signal
The clock signal (4F) before the phase shift shown in FIG. _SC)
Are output alternately for each line. That is, the phase shifter 2
From 5, F_SC, F1_SC, F2_SC, ...
A check signal is output. Therefore, the variance of the quantization phase error
The luck is averaged and the quantization phase error (α) can be reduced.
You.

The burst gate pulse (BGP) output from the burst gate pulse generating circuit 46 is applied to the feedback circuit 38 and the control signal generating circuit 39 as described above. Thus, the output from the comparator 32 is supplied to the PLL 12 only during the burst period. That is, the control signal generation circuit 39 has the same circuit configuration as the feedback circuit 38, and receives the inversion of the output signal from the comparator 32 and the burst gate pulse from the burst gate pulse generation circuit 46 as inputs. And a three-state switch 42b. The sample data (SI) from the sample circuit 28 and the pedestal data generation circuit 34
The tri-state switch 42b becomes conductive only during the burst period when there is a difference (phase difference) from the pedestal data (REF). At that time, the output signal from the comparator 32 is given to the low-pass filter 48 via the three-state switch 42b.

The low-pass filter 48 includes a capacitor (not shown) and both signal data (S) from the comparator 32.
A voltage corresponding to the phase error between (I, REF) is output and given to the voltage controlled oscillator 24. More specifically, FIG.
(A) shows an input burst signal. And the comparator 32
4D, the pedestal data (REF) from the pedestal data generation circuit 34 shown in FIG. 4D and the sample data (SI) from the sample circuit 28 are compared.
The reference pedestal data (REF) is shown in FIG.
As shown in (B), when it is larger than the sample data (SI) (SI-REF = -ΔE), that is, the pedestal data (REF) advances with respect to the sample data (SI). If so, the comparator 32 outputs, for example, a high level signal (H) to the three-state switch 42b.

At this time, the comparator 32 also outputs AN
For example, a low level switching signal (L ') is output to the D gate 40b. This switching signal (L ') is output when there is a phase error between both data (SI and REF) input to the comparator 32 (SI ≠ REF).
The switching signal (L ') and the burst gate pulse (BGP) from the burst gate pulse generating circuit 46 make the three-state switch 42b conductive, and the comparator 3
The high-level signal (H) from 2 is the low-pass filter 4
8 given. With this signal (H), the capacitor (not shown) of the low-pass filter 48 is charged. Therefore, the low pass filter 48 outputs a control signal for reducing the oscillation frequency of the voltage controlled oscillator 24.

On the other hand, as shown in FIG. 4C, when the reference pedestal data (REF) is smaller than the sample data (SI) (retarded) (SI-REF = ΔE).
For example, a low-level signal (L) is output from the comparator 32. As described above, the control signal generation circuit 38 becomes conductive during the burst period when both signals (SI and REF) input to the comparator 32 have a phase difference (SI ≠ REF), and the comparator The low level signal (L) from 32 is given to the low pass filter 48,
The capacitor of the low pass filter 48 is discharged. Therefore, the low pass filter 48 outputs a control signal for increasing the oscillation frequency of the voltage controlled oscillator 24.

In response to the control signal output from the low pass filter 48, the voltage controlled oscillator 24 outputs a clock signal whose oscillation frequency changes according to the phase error data. That is, the low-pass filter 48 averages the phase error data generated between both signals (SI and REF). Therefore, from the voltage controlled oscillator 24,
A clock signal that is always in a fixed phase relationship with the reference frequency signal (input burst signal) is the A / D converter 2
2 is output.

According to the above-described embodiment, most of the components constituting the sampling clock recovery circuit can be implemented by the digital signal processing circuit. Therefore, these digital signal processing circuits can be incorporated in one DSP 14 to
Can be made into chips. The means for removing the color signal component from the video data is not limited to the band elimination filter (BEF) 30 described above, but may be a low pass filter (LP).
F) may be used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a phase shifter of the embodiment of FIG.

FIG. 3 is a waveform chart for explaining the operation of the phase shifter of FIG. 1 embodiment.

FIG. 4 is a waveform diagram showing phase comparison in the comparator of FIG. 1 embodiment.

FIG. 5 is a block diagram showing a conventional technique.

FIG. 6 is a block diagram showing a conventional technique.

[Explanation of symbols]

 10 ... Sampling clock reproduction circuit 12 ... PLL 14 ... DSP 20 ... Clamp circuit 22 ... A / D converter 24 ... Voltage controlled oscillator 25 ... Phase shifter 28 ... Sample circuit 30 ... Band elimination filter (BEF) 32, 36 ... Comparison 34. Pedestal data generating circuit 38. Feedback circuit 39. Control signal generating circuit 48. Low pass filter

Claims (4)

[Claims] 1. A variable frequency oscillator whose oscillation frequency is changed by a control signal, phase shifting means for shifting the oscillation signal from the variable frequency oscillator by a predetermined amount, and an output from the phase shifting means and the oscillation signal. Switching means for switching and outputting at a fixed cycle, an A / D converter for A / D converting at least an intermittent reference frequency signal of a television signal based on an output signal from the switching means, and from the A / D converter Sampling means for sampling the output of the signal with the signal selected by the switching means and outputting sample data; comparison signal data generating means for generating comparison signal data having a constant level at least during a comparison period; Comparing means for comparing sample data with the comparison signal data, and the control signal based on the output of the comparing means for the reference frequency signal period. A control signal generating means for supplying to said variable frequency oscillator during the sampling clock recovery circuit. 2. The sampling clock regenerating circuit according to claim 1, wherein said comparison signal data generating means includes pedestal data generating means for outputting reference pedestal data. 3. The sampling clock regeneration circuit according to claim 1, wherein the reference frequency is a subcarrier frequency of the television signal. 4. The control signal generating means includes an analog low-pass filter for integrating the output of the comparing means, a three-state switch interposed between the output of the comparing means and the analog low-pass filter, and 4. The sampling clock regenerating circuit according to claim 1, further comprising switch control means for controlling the three-state switch according to the output of the comparison means during the period of the reference frequency signal.