JPH09153771A - Signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform pre-hold accompanyied with no sharp noise. SOLUTION: A signal processor 1 has a N-step FIR filter 3 for inputting one-bit digital data through an input terminal 2, error detection circuit 4 for detecting the error contained in these one-bit digital data, and shift/hold output circuit 5 for holding the output of N-step FIR filter 3 for the period of error generation based on the error detected by the error detection circuit 4 and outputting a delayed signal after the recovery of error. Then, since the shift/hold output circuit 5 inhibits the shift operation of this N-step FIR filter 3 during the period in which the hold output signal is generated, pre-hold is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing device for interpolating defective data generated when transmitting and recording 1-bit digital data digitized by 1 bit.

[0002]

2. Description of the Related Art A method called sigma delta (.SIGMA..DELTA.) Modulation has come to be known as a method for digitizing an audio signal (Acoustic Society of Japan, Vol. 46, No. 3, (199).
0) pp. 251-257, "AD / DA converter and digital filter (Yoshio Yamazaki)", etc.). This ΣΔ modulation is a process of modulating an audio signal into 1-bit digital data.

The 1-bit digital data obtained by this ΣΔ modulation has a very high sampling frequency as compared with the data format used for conventional digital audio (for example, sampling frequency 44.1 KHz, data word length 16 bits). And a short data word length (for example, the sampling frequency is 64 times 44.1 KHz and the data word length is 1 bit), and is characterized by a wide transmittable frequency band. In addition, by ΣΔ modulation, 1
Even in the case of a bit signal, a high dynamic range can be ensured in the audio band, which is a low band with respect to the oversampling frequency of 64 times. Utilizing this feature, it can be applied to high-quality sound recorders and data transmission.

This ΣΔ modulation circuit itself is not a new technology in particular, its circuit configuration is suitable for integration into an IC, and the accuracy of A / D conversion can be obtained relatively easily. It is often used inside.

The ΣΔ modulated signal can be returned to an analog audio signal by passing through a simple analog low pass filter.

[0006]

If the original data is lost due to noise on the transmission line or a defective recording medium, it is difficult to recover the data with the 1-bit digital data.

In the conventional multi-bit digital data having a data word tone of 16 bits, it is possible to restore the data having no audible problem by performing, for example, pre-value interpolation from the lost preceding and following data.

However, in the 1-bit digital data obtained by the ΣΔ modulation, the amplitude information is also expressed as a 1-bit pattern on the time axis. The method of replacing with may generate a large amount of noise and was not practical.

The present invention has been made in view of the above circumstances, and provides a signal processing apparatus capable of interpolating defective data generated when transmitting and recording ΣΔ-modulated 1-bit digital data without sharp noise. With the goal.

[0010]

In order to solve the above-mentioned problems, a signal processing apparatus according to the present invention includes an error detecting means for detecting an error contained in the 1-bit digital data, and a 1-bit digital signal over the error occurrence period. Hold the output of N-stage FIR filter to which data is input,
And a hold signal generating means for generating a delayed signal after error recovery, and the N signal is generated during the generation of the hold signal.
The pre-hold is performed by prohibiting the shift operation of the stage FIR filter.

[0011]

Embodiments of a signal processing apparatus according to the present invention will be described below with reference to the drawings.

In this embodiment, the input audio signal is .SIGMA..DELTA. Modulated and recorded in the form of 1-bit digital data on a magnetic tape, and the 1-bit digital data is reproduced from the magnetic tape to output an analog audio signal. It is a preferable signal processing apparatus applied to a recording / reproducing apparatus and interpolates a defective data block that cannot be subjected to normal error correction processing.

As shown in FIG. 1, this signal processing device 1
Is an N-stage FIR filter 3 to which 1-bit digital data is input through the input terminal 2, an error detection circuit 4 for detecting an error included in the 1-bit digital data, and an error detected by the error detection circuit 4. On the basis of the above, a shift / hold ^* output circuit 5 that holds the output of the N-stage FIR filter 3 for the error generation period and generates a delayed signal after error recovery is provided.
The previous value hold is performed by prohibiting the shift operation of the N-stage FIR filter while the hold ^* output circuit 5 is generating the hold output signal. The operation of the signal processing device 1 will be described later.

A digital audio recording / reproducing apparatus to which this signal processing apparatus 1 is applied, uses a Σ
A recording unit 10 as shown in FIG. 2 for recording Δ bit modulation data into 1-bit digital data and recording the 1-bit digital data together with a synchronization signal and an error correction code in units of a predetermined number, and a magnetic tape 19 of the recording unit 10. And a reproducing section 20 as shown in FIG. 3 for reproducing the 1-bit digital data for each of the predetermined number of units. The signal processing device 1 is provided in the reproducing unit 20, but for convenience of description, the recording unit 10 will be described first.

As shown in FIG. 2, in the recording section 10,
The input audio signal from the input terminal 11 is supplied to the integrator 13 via the adder 12. The signal from the integrator 13 is supplied to the comparator 14, where it is compared with, for example, the midpoint potential (“0 V”) of the input audio signal and is quantized by one bit every one sample period. Here, the frequency of the sampling period (sampling frequency) is 48 kHz,
A frequency that is 64 times or 128 times that of 4.1 kHz is used.

This quantized data is a 1-sample delay unit 15
And is delayed by one sample period. This delay data is supplied to the adder 12 through the 1-bit digital / analog (D / A) converter 16 and added to the input audio signal from the input terminal 11. As a result, the comparator 14 outputs quantized data in which the input audio signal is ΣΔ modulated. The quantized data output from the comparator 14 includes a synchronization signal and an error correction code (E
CC) is supplied to the addition circuit 17 and, for example, a synchronization signal and an error correction code are added to the quantized data for each predetermined number of samples.

Next, in the reproducing section 20 shown in FIG. 3, the reproducing head 21 reproduces the 1-bit digital data recorded on the magnetic tape 19. Since this 1-bit digital data is recorded in a format to which the synchronization signal and the error correction code are added every predetermined number,
When supplied to the sync separation and error correction circuit 22, the sync signal is separated and subjected to error correction processing to extract only a predetermined number of 1-bit digital data in which the above-mentioned input audio signal is ΣΔ modulated.

However, at the time of recording / reproducing, in the error correction process in the sync separation and error correction circuit 22, a defective data block including defective data that cannot be corrected as a predetermined number of 1-bit digital data may occur. This may cause a failure of the digital audio recording / reproducing apparatus and its peripheral devices, damage of the magnetic tape 19 as a recording medium, or disconnection in data transmission.

Therefore, in this digital audio recording / reproducing apparatus, the sync separation and error correction circuit 2 is used at the time of recording / reproducing.
When a defective data block that cannot be completely corrected in 2 is generated, the signal processing device 1 is made to output the interpolation data of the defective data block.

The details of the signal processing apparatus 1 will be described below.

The N-stage FIR filter 3 converts the input 1-bit digital data into a high quality analog signal. ΣΔ modulated 1-bit digital data is
Since the amplitude information is also expressed as a 1-bit pattern on the time axis, the DC value of the lost data immediately before can be determined without demodulating it into an analog signal. In the case of ΣΔ-modulated 1-bit digital data, demodulation into an analog signal means that the 1-bit digital data is removed of noise outside the pass band by a low-pass filter. At that time, N-stage FIR filter 3 is used. Enables high quality D / A conversion.

This N-stage FIR filter 3 has an input terminal 2
1-bit digital data input from the D flip-flops F ₁ , F ₂ , F ₃ ... F _N in the upper row in 1-bit digital data in synchronization with the rising edge of the shift clock supplied from the clock input terminal 7. By shifting the output of each of the D flip-flops f ₁ , f ₂ , f _{3 in the} lower N columns.
... Latch again at f _N. The respective outputs of the lower row of N D flip-flops _{f 1, f 2, f 3} ··· f N are synthesized weighted by resistors _{R 1, R 2, R 3} ··· R N, the The 1-bit digital data is subjected to D / A conversion processing by inserting a capacitor between the connection point and the ground.

The N-stage FIR filter 3 can be formed by the digital-analog conversion method disclosed by the applicant of the present application in Japanese Patent Application Laid-Open No. 5-145423.

FIG. 4 shows an FIR filter formed by the digital-analog conversion method disclosed in the above publication. The FIR filter shown in FIG. 4 has eight cascaded D flip-flops f ₁ , f ₂ , f _3.
And · · f _8, the D flip-flop _{f 1, f 2, f 3} ··
.Eight resistors R ₁ , R ₂ , R ₃ respectively connected to f ₈
... and a R _8, this eight resistors _{R 1, R 2, R 3} ·
.. An analog FIR filter is formed by adding the currents from R ₈ , and the output of the FIR filter is smoothed by the capacitor C and obtained from the output terminal.

[0025] That is, 1 an input terminal 30-bit digital data is supplied to connected to the data input terminal D of the D flip-flop f _1, data input to the output terminal Q of the D flip-flop f ₁ D flip-flop f ₂ The output terminal Q of this D flip-flop f ₂ is connected to the terminal D.
Was connected to the data input terminal D of the D flip-flop f _3, connects the output terminal Q of the D flip-flop f ₃ to the data input terminal D of the D flip-flop f _4, the D
Connect the output terminal Q of the flip-flop f ₄ to the data input terminal D of the D flip-flop f _5, connects the output terminal Q of the D flip-flop f ₅ to the data input terminal D of the D flip-flop f _6, the D connect the output terminal Q of the flip-flop f ₆ to the data input terminal D of the D flip-flop f _7, the output terminal Q of the D flip-flop f ₇
Is connected to the data input terminal D of the D flip-flop f ₈ .

The input terminal 31 to which the clock signal is supplied is connected to the D flip-flops f ₁ , f ₂ , f ₃ ... F _{8 respectively.}
To each clock input terminal CK.

Further, one end of the resistor R ₁ is connected to the output terminal Q of the D flip-flop f ₁ and the D flip-flop f ₂
To the output terminal Q of the resistor R _{2 and} to the output terminal Q of the D flip-flop f ₃ to connect one end of the resistor R ₃ .
The output terminal Q of the D flip-flop f ₄ is connected to one end of the resistor R ₄ , the output terminal Q of the D flip-flop f ₅ is connected to one end of the resistor R ₅ , and the output terminal Q of the D flip-flop f ₆ is connected. one end of the resistor R ₆ is connected, to connect one end of a resistor R ₇ to the output terminal Q of the D flip-flop f _7, connecting one end of resistor R ₈ to the output terminal Q of the D flip-flop f ₈ There is.

These resistors R ₁ , R ₂ , R ₃ ...
The other end of R ₈ is connected, the output terminal 32 is formed from the connection point, and the output is smoothed by the capacitor C inserted between the connection point and the ground.

Since the FIR filter shown in FIG. 4 is designed to obtain an analog signal by smoothing the output, noise outside the pass band caused by noise shaping can be removed in the digital-analog conversion process. Therefore, it is possible to perform the digital-analog conversion with high accuracy and high S / N, and it is sufficient that the resistance corresponding to the coefficient is weighted with relative accuracy.
It can be easily integrated into an IC.

Returning to FIG. D flip-flops f ₁ , f ₂ , f ₃ ... f _N in the lower row of the N-stage FIR filter 3 are
The latch is performed in synchronization with the rising edge of the latch clock input via the D gate 6. This latch clock is applied to the D flip-flops F ₁ , F ₂ , F ₃ ... F _{N in the} upper row.
The shift clock supplied from the clock input terminal 7 and the output signal of the shift / hold ^* output circuit 5 to AN
It is input to the D gate 6 and the logical product is taken.

D flip-flops f ₁ , f ₂ , f _{3 in the} lower row
... The latch clock input to f _N via the AND gate 6 is the D flip-flop in the upper row when the output signal of the shift / hold ^* output circuit 5 (shift / hold ^* signal) is “H”. F ₁ , F ₂ , F _3, ... F _N
It is the same as the shift clock supplied to, but remains "L" when the shift / hold ^* signal is "L". Therefore, the D flip-flops f ₁ , f ₂ ,
In f ₃ · · · f _N, not performed a new latching operation, and remains holding the previous value. This makes it possible to hold the analog output after D / A conversion only during the period when the shift / hold ^* signal is "L".

The shift / hold ^* output circuit 5 is composed of, for example, an (N-1) counter 26 as shown in FIG. 5, and inputs an error detection flag which is output when the error detection circuit 4 detects an error. The shift / hold ^* signal is output from the output terminal 2 in synchronization with the bit clock input from the input terminal 29 through the clear terminal via the terminal 25.
7 to output. Where the shift / hold ^* signal is
It is returned to the counter 26 via the inverter 28.

Therefore, the shift / hold ^* output circuit 5
6, as shown in FIG. 6, an error signal input in synchronization with the clock signal and the 1-bit digital signal, and further, the D flip-flops f ₁ , f ₂ , f _3, ... shift based on the number N of f _N /
Hold ^* signals can be combined.

For example, the shift / hold ^* signal shown in FIG.
If no error has occurred as shown in (C) of FIG.
However, once an error occurs and the error signal changes from "H" to "L", it becomes "L" after a delay time of one 1-bit digital signal has elapsed.
Furthermore, the 1-bit digital signal recovers from the error,
As shown in FIG. 6C, when the error signal changes from "L" to "H", the shift / hold ^* signal becomes "H" with a delay of N 1-bit digital signals from that point. This is the D flip-flops f ₁ , f ₂ , f _{3 in the} bottom row.
... It takes time for N 1-bit digital signals to recover from all N inputs of f _N from an error,
This is to wait for that time.

Therefore, the analog output of the N-stage FIR filter 3 is held at the previous value. That is, holding the analog output of the N-stage FIR filter 3 at the previous value can be realized by disabling the shift clock of the shift register. Further, when canceling the previous value hold of the analog output, the FIR filter is released. Waiting for normal data to be reproduced by the tap number N of 3 and loading the data in the filter 3 by the tap number N at once, then the hold of the shift register is released by enabling the clock of the shift register, and the normal state is resumed again. It will return to signal reproduction.

FIG. 7 shows an analog signal waveform after the D / A conversion which is held at the previous value by the signal processing device 1. The section to be held is the DC value hold immediately before, and no sharp noise is generated on both sides of the section. However, the held section is the sum of the time in which an error has occurred and the time for N 1-bit digital signals.

For comparison, FIG. 8 shows a signal waveform diagram when the D / A conversion is performed as it is even when an error occurs. Sharp noise is generated on both sides of the section in which the error occurred, and it is not possible to predict what kind of noise will occur depending on how the analog signal in that section becomes a signal. .

Further, FIG. 9 shows an analog signal waveform after D / A conversion by replacing the section in which an error has occurred with a mute signal. The analog signal in the error section is 0, which is fixed, but sharp noise occurs on both sides of the section.

From the above, the effectiveness of the signal processing device according to the present invention can be illuminated.

[0040]

The signal processing apparatus according to the present invention provides the error detection means for detecting an error contained in the 1-bit digital data and the output of the N-stage FIR filter to which the 1-bit digital data is input during the error occurrence period. Pre-hold without noise is provided by having a hold signal generating means for holding and generating a delayed signal after error recovery, and prohibiting the shift operation of the N-stage FIR filter during the generation of the hold signal. It can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of a signal processing device according to the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a recording unit of a digital audio recording / reproducing apparatus to which the above embodiment is applied.

FIG. 3 is a block diagram showing a schematic configuration of a reproducing section of the digital audio recording / reproducing apparatus.

FIG. 4 is a circuit diagram showing a basic configuration of an N-stage FIR filter used in the above embodiment.

FIG. 5 is a shift / hold used in the above embodiment.
^* It is a circuit diagram which shows the specific example of an output circuit.

FIG. 6 is a timing chart for explaining the operation of the shift / hold ^* output circuit.

FIG. 7 is a diagram illustrating D / held in the previous value according to the above-described embodiment.
It is an analog signal waveform diagram after A conversion.

FIG. 8 is an analog signal waveform diagram after D / A conversion as it is even when an error occurs.

FIG. 9 is an analog signal waveform diagram after D / A conversion by replacing a section in which an error has occurred with a mute signal.

[Explanation of symbols]

1 signal processing device 3 N-stage FIR filter 4 error detection circuit 5 shift / hold ^* output circuit 6 AND gate

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadao Suzuki 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Corporation

Claims (1)

[Claims] 1. An N-stage FIR filter to which 1-bit digital data is input, an error detecting means for detecting an error contained in the 1-bit digital data, and an error based on the error detected by the error detecting means. Hold signal generating means for holding the output of the N-stage FIR filter for a generation period and generating a delayed signal after error recovery, and prohibiting the shift operation of the N-stage FIR filter during the generation period of the hold signal. By doing so, a pre-hold is carried out.