JPH09153747A - Common-mode voltage feedback circuit for differential amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the occupied area on an integrated circuit and to simultaneously provide low power and high gain. SOLUTION: This circuit has a common-mode output detection part 2 for detecting a common-mode voltage from differential output terminals OUT1 and OUT2 of differential amplifier 1 and a common-mode output feedback amplifier part 3 for feeding a voltage for matching an average voltage with a prescribed voltage back to a common-mode feedback terminal 4 of differential amplifier 1 while inputting the common-mode output average voltage from this commonmode output detection part 2 and the prescribed voltage based on a reference voltage VREF and differentially amplifying them. Then, the common-mode output detection part 2 is provided with MOS transistors 8 and 10 for common-mode voltage detection for which respective drains are connected to the terminals OUT1 and OUT2, sources are commonly connected and a high potential VH is supplied to gates and by using these transistors while biasing them to a triode area, the linearity of drain voltage-to-drain current is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a common mode voltage feedback circuit for a differential amplifier, and more particularly to a common mode voltage feedback circuit for a differential amplifier having a differential output terminal and a common mode feedback terminal.

[0002]

2. Description of the Related Art Conventionally, a differential amplifier having a differential output terminal is constructed by using a detection resistor for an output voltage and a feedback amplifier in order to stabilize the output.

FIG. 3 is a common-mode voltage feedback circuit diagram of a differential amplifier showing such a conventional example. As shown in FIG. 3, the differential input terminals IN1 and IN2 and the differential output terminals OUT1 and
The common mode voltage feedback circuit of the differential amplifier 1 having OUT2 is
Two in-phase detection resistors 22, one end of which is connected to the differential output terminals OUT1 and OUT2 and the other end of which is commonly connected,
23, the reference voltage VREF, and the common mode detection resistors 22 and 2
The common connection terminal 3 of the differential amplifier 1 is input and the output thereof is supplied to the common mode feedback terminal 4 of the differential amplifier 1. Amplified difference voltage of the input voltage supplied to the input terminals IN1 and IN2 is output as a voltage from the ground potential to the differential output terminals OUT1 and OUT2, and the average value of both output terminals is the common mode backbone amplifier 21. Is supplied to.

These in-phase detection resistors 22 and 23 use resistance elements having the same resistance value, and the average value voltage of the output voltages at the two differential output terminals OUT1 and OUT2 is applied to the common connection end of the detection resistors 22 and 23. It is generated and input to the common-mode feedback amplifier 21. Further, the common-mode feedback amplifier 21 compares the reference voltage VREF with the average value voltage of the outputs generated at the common connection ends of the detection resistors 22 and 23, and controls the common-mode voltage so that they are equal to each other. It returns to the common-mode feedback terminal 4 of.

Thus, the common-mode voltage feedback circuit performs feedback control so that the average value of the common-mode output voltages generated at the differential output terminals OUT1 and OUT2 of the differential amplifier 1 becomes equal to the reference voltage VREF.

[0006]

The above-described conventional common-mode voltage feedback circuit for a differential amplifier has a structure in which two common-mode detection resistors are connected in series between the differential output terminals of the differential amplifier. There is a drawback that the resistance becomes a load of the differential amplifier and power consumption during operation of the differential amplifier increases.

Further, such a common-mode voltage feedback circuit has a drawback that when a differential amplifier is composed of CMOS transistors, only a low gain can be obtained and it is difficult to realize a high gain.

Further, if the resistance values of the two common-mode detection resistors are increased in order to solve the problems of the increase in power consumption and the reduction in gain, a large area is occupied on the integrated circuit, resulting in a low integrated circuit. There is a drawback that cost reduction becomes difficult.

In short, in the common-mode voltage feedback circuit of the conventional differential amplifier, in order to suppress the increase in power consumption, the resistance value is increased and the current flowing therethrough is reduced, thereby reducing the power consumption. .

It is an object of the present invention to provide a common mode voltage feedback circuit for a differential amplifier which reduces the area occupied by such an integrated circuit and realizes low power consumption and high gain.

[0011]

A common-mode voltage feedback circuit for a differential amplifier according to the present invention is a differential amplifier having two differential input terminals, two differential output terminals and a common-mode feedback terminal, and the differential amplifier. First and second NMOS transistors for detecting in-phase outputs, the drains of which are connected to the output terminals and the gates of which are connected to a high-potential power supply, and the drains between the sources and grounds of the first and second NMOS transistors. And third and fourth connected by shorting the gate
NMOS transistors, and fifth and sixth NMOS transistors having respective drains supplied with a reference voltage and having respective gates connected to a high-potential power supply in order to create a predetermined voltage corresponding to the reference voltage, A common-mode output detection unit including seventh and eighth NMOS transistors connected between the sources and grounds of the fifth and sixth NMOS transistors and by short-circuiting the drain and gate, and a current mirror circuit. A first and a second PMOS transistor, a common-mode average voltage of the common-mode output detector is supplied to the gate, the drain is connected to the drain of the first PMOS transistor and the common-mode feedback terminal, and the source is grounded; N of 9
A MOS transistor, and a predetermined voltage lower than the reference voltage are supplied to the gate and a drain is connected to the source and the gate of the second PMOS transistor,
A common-mode output feedback amplification section including a tenth NMOS transistor whose source is grounded, and the first and second
The NMOS transistor is provided with the same electrical characteristics.

The common-mode voltage feedback circuit of the differential amplifier according to the present invention includes a differential amplifier having two differential input terminals, two differential output terminals and a common-mode feedback terminal, and the differential output terminals respectively. First and second NMs for common mode output detection with drain connected and gate connected to high potential power supply
An OS transistor, third and fourth NMOS transistors connected between the sources of the first and second NMOS transistors and ground, and the third and fourth NMOS transistors
A first bias voltage source commonly connected to the gates of the NMOS transistors, and in order to create a predetermined voltage corresponding to the reference voltage, each drain is supplied with a reference voltage and each gate is connected to a high potential power source. Fifth and sixth NMOS transistors connected to each other, and seventh and eighth transistors connected to the sources and grounds of the fifth and sixth NMOS transistors and to the gate of which the first bias voltage source is connected together. An in-phase output detection unit including an NMOS transistor, first and second PMOS transistors for forming a current mirror circuit, an in-phase average voltage of the in-phase output detection unit is supplied to the source, and a drain is the first A ninth NMOS transistor connected to the drain of the PMOS transistor and the common-mode feedback terminal, and A tenth NMOS transistor having a source supplied with a predetermined voltage lower than the voltage and having a drain connected to the drain of the second PMOS transistor; and a second bias connected to gates of the ninth and tenth NMOS transistors. A common-mode output feedback amplification section including a voltage source, and the first and second NMOs.
The S transistor is configured to have the same electrical characteristics.

Further, the in-phase output feedback amplifying section in the present invention is the third and fourth NM of the in-phase output detecting section.
The common mode voltage is output to the common mode feedback terminal of the differential amplifier so that the common mode average voltage obtained at the drain of the OS transistor and the predetermined voltage obtained at the drains of the seventh and eighth NMOS transistors become equal. Composed.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a common-mode voltage feedback circuit diagram of a differential amplifier showing an embodiment of the present invention. As shown in FIG.
The common mode voltage feedback circuit according to the present embodiment detects a common mode output voltage from a differential amplifier 1 having differential input terminals IN1 and IN2, differential output terminals OUT1 and OUT2, and a common mode feedback terminal 4. It has a detection unit 2 and an in-phase output feedback amplification unit 3 for feeding back the in-phase voltage to the in-phase feedback terminal 4 by the output of the detection unit 2. This in-phase output detection unit 2 has a drain electrode (hereinafter, simply referred to as “drain”) connected to the differential output terminals OUT1 and OUT2, respectively, and a gate electrode (hereinafter, simply referred to as “gate”) connected to the high-potential power supply VH. Output detection NMOS transistors 8 and 10 and these NMOS transistors 8 and 1
The NMOS transistors 9 and 11 which are connected in parallel between the source electrode of 0 (hereinafter, simply referred to as a source) and the ground and short-circuit the drain and the gate to perform a diode function, and a predetermined current corresponding to the reference voltage VREF. A reference voltage VRE is applied to each drain to create
NMOS transistors 12 and 15 which are supplied with F and connected with a high potential power supply VH at their gates, and
The NMOS transistors 13 and 1 which are connected in parallel between the sources of the OS transistors 12 and 15 and the ground and short-circuit the drain and the gate to perform a diode function.
And 4. Further, the in-phase output feedback amplification section 3 supplies PMOS transistors 5 and 6 for forming a current mirror circuit and the in-phase output average voltage of the in-phase output detection section 2 to the gate, and the drain to the drain of the PMOS transistor 5 and the in-phase output. The amplification NMOS transistor 7 which is connected to the feedback terminal 4 and whose source is grounded, and similarly supplied to the gate with a predetermined voltage lower than the reference voltage VREF,
An NMO for amplification whose drain is connected to the source and gate of the PMOS transistor 6 and whose source is grounded.
And an S-transistor 16.

In-phase output detecting NMOS transistors 8 and 1 of the in-phase output detecting section 2 in the in-phase voltage feedback circuit.
0 has their gates connected to the high-potential power supply VH, and further these in-phase output detection NMOS transistors 8 and 1
The drain potential of 0 is NM higher than the potential of the high-potential power supply VH.
Since it is operated at a potential lower than the threshold voltage of the OS transistor, it operates in the triode region and has the same function as the in-phase detection resistors 22 and 23 of FIG. 3 described above. That is, by connecting the NMOS transistors 9 and 11 to the in-phase output detection NMOS transistors 8 and 10, the source potential of the in-phase output detection NMOS transistors 8 and 10 is always higher than the potentials of the differential output terminals OUT1 and OUT2. Biased to be low, NM for common mode output detection
The OS transistors 8 and 10 are designed to operate in a triode in a range where the drain voltage vs. drain current has a good linearity.

The circuit operation will be described more specifically below.

First, since the gates of the in-phase output detecting NMOS transistors 8 and 10 are connected to the high-potential power supply VH, they operate in the triode region (the same applies to the NMOS transistors 12 and 15) and the commonly connected sources. A current corresponding to the average voltage value of the potentials of the differential output terminals OUT1 and OUT2 is passed through.

The current adding NMOS transistors 9 and 11 commonly connected to the sources of the in-phase output detecting NMOS transistors 8 and 10 and the NMOS transistor 7 of the in-phase output feedback amplifying section 3 operate as a current mirror circuit. , The source potentials of the NMOS transistors 8 and 10 are always biased to be lower than the potentials of the differential output terminals OUT1 and OUT2.

Further, like the NMOS transistors 8 and 10, the reference voltage detecting NMOS transistors 12 and 15 which operate in a triode are connected to the sources commonly connected to the reference voltage V.
A current corresponding to REF is passed.

Similarly, the NMO in the in-phase output detector 2 is
N of the S-transistors 13 and 14 and the in-phase output feedback amplifier 3
The MOS transistor 16 operates as a current mirror circuit. In addition, the PMOS that constitutes the in-phase output feedback amplification unit 3
Transistors 5, 6 and NMOS transistors 7, 1
6 operates as a differential amplifier and can feed back the error of the common mode output voltage to the common mode feedback terminal 4.

As described above, according to this embodiment,
By using a MOS transistor biased in the triode region instead of the conventional resistance element, the common-mode voltage feedback circuit can be reduced in size, so that the area on the integrated circuit can be reduced.

For example, comparing the case where a resistor of 50 kΩ is integrated with the case where a MOS transistor having an impedance equivalent to this resistor is compared, although it is slightly different depending on the CMOS diffusion technique, the occupied area is about 1 /. 40
Can be reduced to. As a result, high integration, low power consumption and high accuracy of the integrated circuit using the differential output amplifier circuit can be realized.

The above-mentioned NMOS transistors 9 and 11 and NMOS transistors 13 and 14 can be operated by replacing them with a single NMOS transistor.

FIG. 2 is a common-mode voltage feedback circuit diagram of a differential amplifier showing another embodiment of the present invention. As shown in FIG. 2, this common-mode voltage feedback circuit also has the differential input terminals IN1 and IN2 and the differential output terminal OUT similarly to the feedback circuit of FIG.
In-phase output detecting section 2 for detecting an in-phase output voltage with respect to differential amplifier 1 provided with 1, OUT2 and in-phase feedback terminal 4
And an in-phase output feedback amplification section 3 for feeding back the in-phase voltage to the in-phase feedback terminal 4 by the output of the detection section 2.

Of these, the in-phase output detecting section 2 has an in-phase output detecting N having drains connected to the differential output terminals OUT1 and OUT2 and a gate connected to the high potential power supply VH.
MOS transistors 8 and 10, NMOS transistors 9 and 11 connected in parallel between the sources of these NMOS transistors 8 and 10 and ground, and a reference voltage VREF.
NMOS transistor 1 in which a reference voltage VREF is supplied to each drain and a high potential power supply VH is connected to each gate in order to generate a predetermined current corresponding to
2, 15 and NMOS transistors 13 and 14 connected in parallel between the sources of these NMOS transistors 12 and 15 and the ground, and these NMOS transistors 9 and
A first bias voltage source 20 for supplying a bias voltage to each of gates 11, 13, and 14. The in-phase output feedback amplifying section 3 supplies the PMOS transistors 5 and 6 for forming a current mirror circuit and a predetermined voltage lower than the in-phase average output voltage and the reference voltage VREF of the in-phase output detecting section 2 to the respective drains. , NMOS sources 18 and 19 whose sources are connected to the source of the PMOS transistor 5 and the common-mode feedback terminal 4 and the source of the PMOS transistor 6, and NM of these.
A second bias voltage source 17 for supplying a bias voltage to each gate of the OS transistors 18 and 19.

Also in the common-mode voltage feedback circuit, the common-mode output detection NMOS transistors 8 and 10 of the common-mode output detection unit 2 operate in the triode region because their gates are both connected to the high-potential power supply VH. Therefore, at the sources of these transistors 11 and 13, a voltage corresponding to the average value of the potentials of the differential output terminals OUT1 and OUT2 is generated. Further, since the gates of the NMOS transistors 9 and 11 are biased by the first bias voltage source 20, they operate as current sources. Therefore, the potential of the commonly connected sources of the in-phase output detection NMOS transistors 8 and 10 is always biased to be lower than the potential of the differential output terminal OUT1 or OUT2.

On the other hand, the NMOS transistors 12 and 15 and the NMOS transistors 13 and 14 generate a voltage corresponding to the reference voltage VREF at their common connection point.

As described above, the NMOS transistors 18 and 19 each having a predetermined voltage based on the in-phase average output voltage and the reference voltage are supplied to the drains thereof, the second bias source 17, and the PMOS transistors 5 and 6. Since the in-phase output feedback amplification section 3 operates as a differential amplifier, it is possible to feed back the error of the in-phase output voltage to the in-phase feedback terminal 4.

According to the present embodiment, high integration, low power consumption and high accuracy of the integrated circuit according to the embodiment of FIG. 1 described above are realized, and further, the bias voltage source 20 is provided to the common mode output detection unit 2. , The operating current of the common-mode voltage feedback circuit, that is, the NMOS transistor 8,
The total current of 10, 12, and 15 can be reduced.

Further, in the above-mentioned two embodiments, the MOS transistor 8 forming the in-phase output detecting section 2 is formed.
.About.15 and the MOS transistors 7, 16 or 18, 19 forming the in-phase output feedback amplifying section 3 are N-MOS, and the MOS transistors 5, 6 forming the in-phase output feedback amplifying section 3 are P-MOS. These relationships can be reversed and used. At that time,
In general, the absolute value of the threshold voltage (Vt) of the P-MOS transistor is larger than that of the N-MOS transistor, so that the output voltage range of the N-MOS transistors 8 and 10 in the triode operating region is narrowed.

[0032]

As described above, the common-mode voltage feedback circuit of the differential amplifier according to the present invention includes a common-mode voltage detecting MOS transistor and a predetermined voltage generating MOS transistor which are respectively connected to the differential output terminals of the differential amplifier. And a common-mode output feedback amplification section for feeding back an error of the common-mode output voltage to the feedback terminal of the differential amplifier by the common-mode voltage and the predetermined voltage from the common-mode output detection section. By biasing the detection MOS transistor to the triode region, the common-mode voltage detection section can be formed without using a high resistance, so that there is an effect that high integration, low power consumption and high gain can be realized.

[Brief description of the drawings]

FIG. 1 is a common-mode voltage feedback circuit diagram of a differential amplifier showing an embodiment of the present invention.

FIG. 2 is a common-mode voltage feedback circuit diagram of a differential amplifier showing another embodiment of the present invention.

FIG. 3 is a common-mode voltage feedback circuit diagram of a differential amplifier showing a conventional example.

[Explanation of symbols]

 1 differential amplifier 2 common-mode output detection unit 3 common-mode output feedback amplification unit 4 common-mode feedback terminal 17,20 bias voltage source IN1, IN2 differential input terminal OUT1, OUT2 differential output terminal VREF reference voltage input terminal VH high-potential power supply

Claims (4)

[Claims] 1. A differential amplifier having two differential input terminals, two differential output terminals and a common-mode feedback terminal, and a drain connected to each of the differential output terminals and a gate connected to a high potential power supply. First and second for in-phase output detection
NMOS transistor and the first and second NMs
Third and fourth Ns connected between the source and the ground of the OS transistor and by short-circuiting the drain and the gate
MOS transistors, fifth and sixth NMOS transistors having respective drains supplied with a reference voltage and having respective gates connected to a high-potential power supply in order to create a predetermined voltage corresponding to the reference voltage; And a seventh and an eighth NMOS transistor connected between the source and the ground of the sixth NMOS transistor and by short-circuiting the drain and the gate, and a first mirror for forming a current mirror circuit. A first and a second PMOS transistors, a common-mode average voltage of the common-mode output detector is supplied to the gate, the drain is connected to the drain of the first PMOS transistor and the common-mode feedback terminal, and the source is grounded. NMO
In-phase output feedback including an S transistor and a tenth NMOS transistor whose gate is supplied with a predetermined voltage lower than the reference voltage and whose drain is connected to the source and the gate of the second PMOS transistor and whose source is grounded. An amplifier unit, and the first and second N
A common-mode voltage feedback circuit for a differential amplifier, characterized in that a MOS transistor has the same electrical characteristics. 2. The in-phase output feedback amplification section obtains the in-phase average voltage obtained at the drains of the third and fourth NMOS transistors and the drains of the seventh and eighth NMOS transistors of the in-phase output detection section. 2. The common-mode voltage feedback circuit of the differential amplifier according to claim 1, wherein the common-mode voltage is output to the common-mode feedback terminal of the differential amplifier so that the predetermined voltage becomes equal. 3. A differential amplifier having two differential input terminals, two differential output terminals and a common-mode feedback terminal, and a drain connected to each of the differential output terminals and a gate connected to a high potential power supply. First and second for in-phase output detection
NMOS transistor and the first and second NMs
Corresponding to third and fourth NMOS transistors connected between the source of the OS transistor and ground, a first bias voltage source commonly connected to the gates of the third and fourth NMOS transistors, and a reference voltage And a source of each of the fifth and sixth NMOS transistors, wherein a reference voltage is supplied to each drain and each gate is connected to a high-potential power supply in order to generate the predetermined voltage. And an in-phase output detection unit including a seventh and an eighth NMOS transistor connected to the ground and having the gate connected to the first bias voltage source, and a first and a second for forming a current mirror circuit. A second PMOS transistor,
A ninth NMOS in which the common mode average voltage of the common mode output detection unit is supplied to the source and the drain is connected to the drain of the first PMOS transistor and the common mode feedback terminal.
A transistor, a tenth NMOS transistor having a source supplied with a predetermined voltage lower than the reference voltage and a drain connected to the drain of the second PMOS transistor, and connected to gates of the ninth and tenth NMOS transistors. An in-phase output feedback amplification section including a second bias voltage source, and the first and second N
A common-mode voltage feedback circuit for a differential amplifier, characterized in that a MOS transistor has the same electrical characteristics. 4. The in-phase output feedback amplification section obtains the in-phase average voltage obtained at the drains of the third and fourth NMOS transistors of the in-phase output detection section and the drains of the seventh and eighth NMOS transistors. The common-mode voltage feedback circuit for a differential amplifier according to claim 3, wherein the common-mode voltage is output to the common-mode feedback terminal of the differential amplifier so that the predetermined voltage becomes equal.