JPH09153592A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent intrusion of noise into a passive element by providing a well diffusion layer beneath an LOCOS on which the passive element is formed and feeding the well diffusion layer with a stabilized reference voltage. SOLUTION: A resistive element Rn and a capacitive element Cf are provided at a passive element part 4. The resistive element Rn is formed of a polysilicon layer 104 formed on an LOCOS 103 whereas the capacitive element Cf is formed of the polysilicon layer 104, an oxide insulation layer 105, and a wiring layer 106. A low-pass filter 5 outputs a secondary reference voltage kVref produced by correcting a primary reference voltage Vref with a specified rate (k). Intrusion of noise into a passive element is prevented by providing a well diffusion layer 102 beneath the LOCOS on which the passive element is formed and feeding the well diffusion layer 102 with a stabilized reference voltage kVref so that the potential on the well diffusion layer 102 is insusceptible to the power supply potential Vdd.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and further, a so-called analog / digital I having a digital circuit section and an analog circuit section in one semiconductor substrate.
The present invention relates to a technique effective when applied to C, for example, a technique effective when used for an A / D converter or a D / A converter.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device having an analog circuit portion, passive elements such as resistors and capacitors are formed of LOCOS (local oxide film) in order to enable trimming with a laser or the like, or because of necessity in the circuit. Forming is performed.

The passive element formed on the LOCOS is L
Although it is separated from the semiconductor substrate by OCOS,
Noise from the semiconductor substrate enters through the parasitic capacitance between the upper side and the lower side of the LOCOS. In order to prevent the invasion of this noise, the present inventors have considered placing a well diffusion layer under the LOCOS where passive elements are formed. Since the well diffusion layer is connected to the power supply potential, by forming the well diffusion layer under the LOCOS, the lower side of the LOCOS can be electrically isolated from the substrate, whereby noise intrusion from the substrate can occur. Is to prevent. That is, the well diffusion layer is LOC
It is interposed as a kind of shield layer between the OS and the substrate.

[0004]

However, it has been clarified by the present inventors that the above-described technology has the following problems.

In other words, by providing the well diffusion layer, noise intrusion from the substrate can be prevented,
When noise is added to the power supply potential to which the well diffusion layer is connected, noise from the power supply potential invades the passive element on the LOCOS from the well diffusion layer. In addition to noise from the outside, noise generated inside the semiconductor integrated circuit device is also likely to be added to the power supply potential. Especially analog
In the digital IC, the switch noise accompanying the operation of the digital circuit section spills into the well diffusion layer from the internal power supply line. Therefore, with the above-mentioned conventional technology alone,
Power supply noise resistance in a circuit section including passive elements on LOCOS, so-called PSRR (Power Supply Re)
injection ratio: power supply voltage removal ratio) could not be sufficiently increased.

An object of the present invention is to reliably prevent noise from invading a passive element formed on a LOCOS and to obtain a high PSR.
It is to provide a technology that enables R.

The above and other objects and characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the LO in which the passive element is formed
The well diffusion layer is placed under the COS, and a stabilized reference voltage is supplied to the well diffusion layer.

According to the above-mentioned means, the potential in the well diffusion layer can be prevented from being affected by the power source potential.

Thus, the object of reliably preventing noise from invading the passive element formed on the LOCOS and enabling a high PSRR is achieved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

In the figures, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an outline of a circuit and device configuration in a main part of a semiconductor integrated circuit device to which the technique of the present invention is applied.

In the figure, 100 is a semiconductor integrated circuit device of a MOS process which forms an analog / digital IC.
01 is a p-conductivity type silicon semiconductor substrate (p-sub),
102 is an n-conductivity type well diffusion layer, and 103 is LOCOS.
(Local oxide film), 104 is a polycrystalline silicon layer formed together with a gate electrode of a MOS transistor (not shown), 105 is an oxide insulating layer formed as a kind of the gate insulating film of the MOS transistor, and 106 is Insulating layer 10
5 is a wiring layer formed on the substrate 5, 110 is an external connection terminal, Cs
Is a parasitic capacitance formed across the LOCOS 103.

Further, 1 is a reference voltage generating circuit, 2 is a bias voltage generating circuit, 3 is an operational amplifier circuit which constitutes a constant voltage control circuit, 4 is a passive element portion formed on the LOCOS 103,
5 is a low pass filter circuit, 6 is a reference voltage kVre
An analog circuit portion operating using f, Vdd is a power supply potential, and GND is a ground reference potential. All of these are integrated and formed on the same semiconductor substrate 101.

The passive element section 4 is provided with a resistance element Rn and a capacitance element Cf. The resistance element Rn is LOCOS1.
03 is formed by the polycrystalline silicon layer 104. The capacitive element Cf is formed by the polycrystalline silicon layer 104, the oxide insulating layer 105, and the wiring layer 106. By forming these passive elements on the LOCOS 103, the degree of freedom in the circuit configuration is obtained as an element independent of the substrate, and the trimming process by a laser or the like performed in the final process step of the semiconductor integrated circuit device is also performed. It is possible.

The resistance element Rn forms a kind of resistance ladder by the polycrystalline silicon layer 104 having a zigzag folded pattern, as shown in FIG. The tap has been pulled out.

FIG. 3 shows a complete circuit diagram of the portion shown in FIGS.

As shown in the figure, the operational amplifier circuit 3 outputs the primary reference voltage Vref output from the reference voltage generation circuit Vref under the voltage negative feedback by the resistance element Rn and the phase compensation by the capacitance element Cf. Amplify negative feedback. The output voltage by this negative feedback amplification is taken out at an arbitrary voltage division rate k through the resistance element Rn and the tap selection switch array 41, and is input to the low pass filter 5.

The low-pass filter 5 is composed of an RC type integration circuit 51 composed of a resistor R1 and a capacitance C1, an operational amplification circuit 52 for buffer-amplifying the output of the integration circuit 51 by a voltage follower operation, and a bias circuit 53. , A predetermined rate (k) with respect to the primary reference voltage Vref
The secondary reference voltage kVref corrected by is output.
The secondary reference voltage kVref is stabilized by the negative feedback operation of the operational amplifier circuit 52 so as to have a constant correction factor (k) with respect to the primary reference voltage Vref. The correction factor (k) at this time is arbitrarily preset by the tap selection switch array 41. Further, the resistor R1 and the capacitor C1 of the integrating circuit 51 are formed on the LOCOS like the resistor element Rn and the capacitor element Cf.

The secondary reference voltage kVref output from the low pass filter 5 is further smoothed by the external capacitor Cx connected via the external connection terminal 110,
It is supplied as an analog reference voltage to the analog circuit section 6 which performs A / D conversion or D / A conversion. At the same time, the secondary reference voltage kVref is also supplied to the well diffusion layer 102 under the LOCOS in which the above-mentioned passive element is formed.

As described above, the well diffusion layer 102 is placed under the LOCOS in which the passive elements are formed, and the well diffusion layer 102 is supplied with the stabilized reference voltage kVref, whereby the well diffusion layer 102 is supplied. 1
The potential at 02 can be prevented from being affected by the power supply potential Vdd. As a result, it is possible to reliably prevent noise from invading the passive element formed on the LOCOS and to increase the PS.
It becomes possible to realize RR.

In addition, in the above-described embodiment, the reference voltage kVref supplied to the analog circuit section 6 is supplied to the well diffusion layer 102, so that the circuit for generating the reference voltage kVref is shared. This makes it possible to avoid an increase in the number of circuit elements.

If the reference voltage kVref is also supplied to the well diffusion layer formed in the analog circuit section 6, the ground reference potential in the analog circuit section 6 can be stabilized, and the analog reference voltage can be stabilized. Noise in the circuit section 6 can be further reduced.

Further, by supplying the reference voltage kVref to the well diffusion layer 102 via the capacitor Cx connected to the outside, the potential in the well diffusion layer 102 can be further stabilized.

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

Differences from the above-described embodiment will be described. In the embodiment shown in the figure, the reference voltage kVref is used.
Are supplied to the well diffusion layer 102 via the buffer circuit 6 by the source follower of the p-channel MOS transistor. The buffer circuit 6 acts as an isolation that prevents noise from entering from the well diffusion layer 102 side to the supply side of the reference voltage kVref. As a result, even if noise is added to the well diffusion layer 102, the noise is prevented from being applied to the reference voltage kVref and affecting other circuit portions 6.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the reference voltage kVref may be supplied to the well diffusion layer 102 by an independent reference voltage generating circuit.

In the above description, MO, which is the field of application behind the invention made by the present inventor, is mainly.
The case where the present invention is applied to the semiconductor integrated circuit device of the S process has been described, but the present invention is not limited to this, and can be applied to the semiconductor integrated circuit device of the Bi-CMOS process, for example.

[0032]

The outline of the typical inventions among the inventions disclosed in the present application will be briefly described as follows.

That is, it is possible to reliably prevent noise from entering the passive elements formed on the LOCOS and realize a high PSRR.

[Brief description of the drawings]

FIG. 1 is a circuit / device diagram of a main part of a semiconductor integrated circuit device to which a technique of the present invention is applied.

FIG. 2 is a diagram partially showing an example of a pattern shape of a resistance element.

FIG. 3 is a circuit diagram showing the device components shown in FIGS. 1 and 2 as a circuit diagram.

FIG. 4 is a circuit diagram showing another embodiment of the present invention.

[Explanation of symbols]

 100 semiconductor integrated circuit device 101 p conductive type silicon semiconductor substrate (p-sub) 102 n conductive type well diffusion layer 103 LOCOS (local oxide film) 104 polycrystalline silicon layer 105 oxide insulating layer 106 wiring layer 110 external connection terminal 1 reference voltage Generating circuit 2 Bias voltage generating circuit 3 Operational amplifier circuit forming a constant voltage control circuit 4 Passive element section 5 Low pass filter circuit 52 RC type integrating circuit 6 Analog circuit section Vdd Power supply potential GND Ground reference potential Rn Resistance element Cf Capacitive element Cx External capacitance Cs Parasitic capacitance

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/8249 H01L 27/04 C 21/8238 27/06 102F 27/092 321G H03K 19/003 27 / 08 321B 19/08 H03M 1/76 (72) Inventor Hiroaki Sonobe 15 Asahidai, Moroyama-cho, Iruma-gun, Saitama Prefecture

Claims (6)

[Claims] 1. A semiconductor integrated circuit device having a passive element formed on a LOCOS, wherein a well diffusion layer is placed under the LOCOS on which the passive element is formed, and the well diffusion layer is stabilized. A semiconductor integrated circuit device characterized in that a reference voltage is supplied. 2. A MOS as a passive element on the LOCOS.
2. The semiconductor integrated circuit device according to claim 1, further comprising a resistance element made of a polycrystalline silicon layer formed together with the gate electrode of the transistor. 3. A MOS as a passive element on the LOCOS
A capacitive element including a polycrystalline silicon layer formed together with a gate electrode of a transistor, an insulating layer formed as a kind of the gate insulating film of the MOS transistor, and a wiring layer formed on the insulating layer The semiconductor integrated circuit device according to claim 1 or 2. 4. The semiconductor integrated circuit device according to claim 1, wherein the reference voltage supplied to the analog circuit portion in the semiconductor integrated circuit device is supplied to the well diffusion layer. . 5. The semiconductor integrated circuit device according to claim 1, wherein the reference voltage is supplied to the well diffusion layer via a buffer formed by a source follower. 6. The semiconductor integrated circuit according to claim 1, wherein the reference voltage is supplied to the well diffusion layer via a capacitor connected to the outside of the semiconductor integrated circuit device. apparatus.