JPH10145219A - Semiconductor input circuit and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adapt a semiconductor input circuit to a semiconductor integrated circuit of breakdown strength, which is smaller than the voltage amplitude of an externally supplied logical signal and to enable making capacitive potential division coupling between an internal circuit and an external circuit. SOLUTION: This device is provided with an input pad 11 which receives a logical signal of 5V voltage amplitude, a capacitive-type potential dividing circuit 12 which is serially connected to the pad 11, a voltage-limiting circuit 13 which limits the logical signal to 3V voltage amplitude and a detection circuit DT which detects the voltage amplitude that is limited by the circuit 13 as an input signal. The circuit 12 consists of a capacitor 12a, which is serially connected between the pad 11 and a node P and a capacitor 12b, that is connected between the node P and a power terminal VSS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor input circuit incorporated in a semiconductor integrated circuit for processing a logic signal with a predetermined voltage amplitude, and more particularly to a semiconductor input circuit for receiving a logic signal exceeding a predetermined voltage amplitude and a method of manufacturing the same.

[0002]

2. Description of the Related Art When a semiconductor integrated circuit operates at a power supply voltage of 5 V, a semiconductor input circuit shown in FIG. 5 is generally provided in the semiconductor integrated circuit. This semiconductor input circuit receives a logic signal supplied from the outside at input pad 1 and converts the logic signal from input pad 1 to diodes 2 and 3.
Is limited to a voltage amplitude of 5V by a clamp circuit composed of
Further, the logic signal from the clamp circuit is detected by the CMOS buffer 4 as an input signal. Since the semiconductor element on the semiconductor integrated circuit is formed to have a withstand voltage corresponding to the power supply voltage, the diode 2 is omitted when the voltage amplitude of the logic signal supplied to the input pad 1 does not exceed 5V. Thereby, the leakage current can be reduced.

Recently, high integration and power saving of semiconductor integrated circuits have been actively performed, and semiconductor integrated circuits that operate at a power supply voltage of 3 V have been developed. Such a semiconductor integrated circuit is supplied from another semiconductor integrated circuit.
It is necessary that a logic signal having a voltage amplitude of V can be detected as an input signal. In this case, if the diode 2 is omitted in order to reduce the leakage current, the MOS transistor forming the CMOS buffer 4 will be broken due to insufficient withstand voltage. If the gate breakdown voltage and PN junction breakdown voltage of the MOS transistor are increased to 5 V or more to avoid this, M
The size of the OS transistor increases, which causes a reduction in the integration density of the semiconductor integrated circuit.

Conventionally, a semiconductor input circuit shown in FIG. 6 has been proposed as a technique for reducing leakage current. This semiconductor input circuit has a depletion MOS transistor 5 connected between the input pad 1 and the CMOS buffer 4. The logic supplied to the CMOS buffer 4 by setting the gate potential of the depletion MOS transistor 5 to 3V. Limit the voltage amplitude of the signal to 3V. Therefore, the above-mentioned diode 2 becomes unnecessary.

[0005]

However, the above-described depletion MOS transistor 5 requires a PN junction breakdown voltage of 5 V or more, and must be formed in a process independent of other MOS transistors provided in the semiconductor integrated circuit. No. Therefore, the use of the depletion MOS transistor 5 increases the manufacturing cost of the semiconductor integrated circuit.

Conventionally, the internal circuit and the external circuit of a semiconductor input circuit are electrically connected. However, this method cannot be applied to the case where the internal circuit and the external circuit are to be capacitively coupled.

An object of the present invention is a semiconductor input circuit suitable for a semiconductor integrated circuit having a withstand voltage smaller than the voltage amplitude of a logic signal supplied from the outside, capable of capacitively coupling an internal circuit and an external circuit, and a method of manufacturing the same. Is to provide.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide an input pad for receiving a logic signal exceeding a predetermined voltage amplitude, a capacitance voltage dividing circuit connected to the input pad, and a voltage supplied through the capacitance voltage dividing circuit. A voltage limiting circuit for limiting the logic signal to the predetermined voltage amplitude, and detecting means for detecting a logic signal having the voltage amplitude limited by the voltage limiting circuit as an input signal, wherein the capacitive voltage dividing circuit includes the input pad. And a second capacitor connected between the voltage limiting circuit and a power supply terminal.

In the semiconductor input circuit according to the present invention, a logic signal exceeding a predetermined voltage amplitude is received at the input pad, and the logic signal supplied through the capacitor voltage dividing circuit connected in series to the input pad is subjected to voltage limiting. The circuit is limited to the predetermined voltage amplitude. A logic signal having a voltage amplitude limited by the voltage limiting circuit is detected by the detection means as an input signal. A wiring connected to the input pad is formed so as to have a portion constituting a first electrode of a first capacitor of the capacitance voltage dividing circuit, and a second electrode of the first capacitor and the first electrode are formed. The second electrode also serves as the second electrode of the capacitor
A wiring connected to the voltage limiting circuit and the detecting means is formed so as to have a portion constituting the first electrode of the capacitor. The conductive region in the semiconductor substrate is the second region.
As the second electrode of the capacitor. further,
A first insulating film is formed between a first electrode of the first capacitor and a second electrode of the first capacitor, and a first electrode of the second capacitor and a second electrode of the second capacitor are formed.
A second insulating film is formed between the electrodes.

In this semiconductor input circuit, when a logic signal supplied to an input pad is inverted, the logic signal is temporarily transmitted to a voltage limiting circuit via a capacitance voltage dividing circuit. Therefore, it is possible to prevent the leakage current from continuously flowing to the voltage limiting circuit. At this time, the voltage limiting circuit limits the voltage amplitude of the logic signal from the capacitance voltage dividing circuit to a predetermined voltage amplitude. Therefore, even when the semiconductor integrated circuit has a withstand voltage lower than the voltage amplitude of the logic signal supplied from the outside, useless power consumption can be reduced without increasing the withstand voltage of the semiconductor integrated circuit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor integrated circuit according to one embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit configuration of the semiconductor integrated circuit. This semiconductor integrated circuit includes a semiconductor input circuit IM and a logic circuit module LM which are formed on a single semiconductor substrate SB and operate at a power supply voltage of 3V. The semiconductor input circuit IM is used for converting a logic signal having a voltage amplitude of 5 V exceeding 3 V into an input signal of the logic circuit module LM, and the logic circuit module LM processes an input signal supplied from the semiconductor input circuit IM. .

The semiconductor input circuit IM has an input pad 11 for receiving a logic signal having a voltage amplitude of 5 V supplied from the outside.
And a capacitor voltage dividing circuit 12 composed of capacitors 12a and 12b connected in series to the input pad 11, and a voltage limiting circuit for limiting a logic signal supplied via the capacitor voltage dividing circuit 12 to a voltage amplitude of 3V. 13 and a detection circuit DT that detects a logic signal having a voltage amplitude limited by the voltage limiting circuit 13 as an input signal.

The voltage limiting circuit 13 has a diode 13a reverse-biased between a power supply terminal VDD set to a power supply potential of 3V and a node P connecting the capacitor 12 and the detection circuit DT, and a reference potential of 0V between this node P and 0V. Is a clamp circuit composed of a diode 13b that is reverse-biased between the power supply terminal VSS and the power supply terminal VSS. The detection circuit DT is a latch circuit 1 for latching a logic signal having a voltage amplitude limited by the voltage limiting circuit 13.
4, a pull-down resistor 15 for setting an initial value of the latch circuit 14, and a CMOS inverter 16 for outputting a logic signal latched by the latch circuit 14 as an input signal.

The latch circuit 14 is composed of CMOS inverters 14a and 14b connected in opposite directions.
The input terminal of the latch circuit 14 is connected to the node P and to the power supply terminal VSS via the pull-down resistor 15. The latch circuit 14 is provided to prevent a malfunction due to noise or the like when the frequency f of the input signal to the input pad 11 is extremely low. The latch circuit 14 and the pull-down resistor 15 are provided for compensating a delay in potential change caused by capacitive coupling of the node P to the input pad 11 by the capacitive voltage dividing circuit 12.

The resistance of the capacitor C of the capacitive voltage dividing circuit 12 and the resistance R of the pull-down resistor 15 are determined by the input pad 11
F <10 · C with respect to the frequency f of the logic signal supplied to
-Set to the relationship of R.

In the above-described semiconductor integrated circuit, the input pad 1
1 changes in response to a logic signal supplied from the outside, this change is transmitted to the node P via the capacitor voltage dividing circuit 12.
Is transmitted to The diode 13a prevents the potential of the node P from rising beyond the potential of the power supply terminal VDD (= 3V), and the diode 13b prevents the potential of the node P from falling beyond the potential of the power supply terminal VSS (= 0V). To block. That is, the logic signal is changed from 0 V to 3 at the node P.
It changes in the range of V. Since node P is only capacitively coupled to input pad 12, the current flowing through diode 13a or 13b is temporary. The logic signal on the node P is latched as an input signal by the latch circuit 14, and is output to the logic circuit module LM via the inverter 16.

Here, a manufacturing process of the above-described semiconductor integrated circuit will be schematically described with reference to FIG.

In the step (a), a P-type silicon conductive region 21 is formed in the N-type silicon substrate SB by ion implantation or the like, and an oxide film 22 is formed on the conductive region 21 and the silicon substrate SB. The P-type conductive region 21
Constitutes a first electrode 12b1 of the capacitor 12b and is connected to a ground potential (not shown).

In the step (b), a metal wiring layer 23 is formed on the silicon substrate SB and its oxide film as a wiring connected to the voltage limiting circuit 13 and the latch circuit 14. Part of the metal wiring layer 23 is
Of the second electrode 12b2 and the first electrode 12a1 of the capacitor 12a.

In the step (c), an oxide film 24 is formed on the silicon substrate SB and the metal wiring layer 23. The oxide film 24 is an insulating film between the first metal wiring layer 23 and the second metal wiring layer 25, and is selectively patterned as an insulating film of the capacitor 12a.

In the step (d), a metal wiring layer 25 is formed on the oxide film 24 as a wiring connected to the input pad # 11. Part of this metal wiring layer 25 is
a of the second electrode 12a2.

In the step (e), an oxide film 26 is formed as a surface protection film covering the wiring patterns 23 and 26,
This oxide film 26 serves as the second electrode 12a2 of the capacitor 12a.
Is selectively removed to expose a portion of the. The exposed portion of the second electrode 12a2 of the capacitor 12a is used as the input pad 11. In the above-described embodiment, the semiconductor integrated circuit receives the logic signal having the voltage amplitude of 5 V, the input pad 11, and the capacitor voltage dividing circuit 1 including the capacitors 12a and 12b connected in series to the input pad 11.
2, a voltage limiting circuit 13 for limiting a logic signal supplied via the capacitive voltage dividing circuit 12 to a voltage amplitude of 3 V, and a logic signal having a voltage amplitude limited by the voltage limiting circuit 13 is detected as an input signal. And a detection circuit DT.
When the logic signal supplied to the input pad 11 is inverted, the logic signal is supplied to the voltage limiting circuit 1 via the capacitor voltage dividing circuit 12.
3 is temporarily transmitted. Therefore, it is possible to prevent the leakage current from continuously flowing to the voltage limiting circuit 13. At this time, the voltage limiting circuit 13 limits the voltage amplitude of the logic signal from the capacitance voltage dividing circuit 12 to a voltage amplitude of 3V. Therefore,
Even when the semiconductor integrated circuit has a withstand voltage of 3 V lower than the voltage amplitude of the logic signal supplied from the outside, useless power consumption can be reduced without increasing the withstand voltage of the semiconductor integrated circuit. Specifically, the semiconductor input circuit IM can be applied even when both the gate breakdown voltage and the PN junction breakdown voltage of the MOS transistor formed on the semiconductor substrate SB are 3V.

The capacitors 12a and 12b constituting the capacitance voltage dividing circuit 12 are connected to the second electrode 1 of the capacitor which is a part of the wiring connected to the input pad 11.
2a2, the first electrode 12a1 of the capacitor 12a and the second electrode 12b2 of the capacitor 12b, which are part of the wiring connected to the voltage limiting circuit 13 and the detecting circuit DT.
And a capacitor 12 which is a conductive region 21 of P-type silicon.
b of the first electrode 12b1. Therefore, the electrodes 12a1, 12a of these capacitors 12a and 12b
It is not necessary to add a new manufacturing process to form a2, 12b1, and 12b2. Further, oxide film 24 between these capacitors 12a and 12b can be manufactured in the same manufacturing process as the interlayer insulating film between the first and second metal wiring layers.

Here, a method of obtaining a divided potential in this semiconductor integrated circuit will be described with reference to FIG.

In FIG. 3, the area of the P-type conductive region is S
₁ , the area of the metal wiring layer 25 is S ₂ , the thickness of the metal wiring layer 23 is dm ₁ , and the thickness of the metal wiring layer 25 is d.
m ₂ , the thickness of the oxide film 22 is dox ₁ , and the thickness of the oxide film 24 is dox ₂ . It is assumed that the metal wiring layer 23 is a region including the P-type silicon conductive region 21.

The capacitance C _{1 of the} capacitor 12a composed of the metal wiring layer 23 and the metal wiring layer 25 is

(Equation 1) On the other hand, the capacitance C _{2 of the} capacitor 12b composed of the P-type silicon conductive region 21 and the metal wiring layer 23 is

(Equation 2) Becomes (Here, epsilon _ox is the dielectric constant of the oxide film, epsilon ₀ denotes respectively a dielectric constant in vacuum.) The partial pressure V _o of the input voltage signal V _i is represented by the following formula.

[0028]

(Equation 3) Here, usually remains process, i.e. when not to use an additional mask process, the film thickness dox ₁ of oxide film 22, the film thickness dox ₂ of the oxide film 24 can not be changed. The area S ₂ of the metal wiring layer 25 is the opening area of the input pad 11 which is a bonding portion, and cannot be freely changed. Therefore, the area S ₁ of the P-type conductive region
, The output potential can be changed as appropriate. That is, by arbitrarily setting the area S ₁ of the portion where the P-type conductive region 21 and the metal wiring layer 23 face each other, a desired capacitance C can be obtained, and a desired output can be obtained.

For example, dox ₁ = 5 × 10 ⁻⁷ m, dox
₂ = 4 × 10 ⁻⁷ m, S ₂ = 100 μm × 100 μm = 1
As 0 ^-8 m, Vi = 5V, in order to obtain Vo = 3V _{is, C 2 / (C 1 +} C 2) = Vo / Vi = 3/5 Thus, from the equation (3)

(Equation 4) It is good.

Further, as another embodiment, by using an additional mask step, the thickness of the oxide film dox ₁ ,
dox ₂ can be controlled independently. In this case, an arbitrary partial pressure output can be obtained by the above equation (3) using three parameters of the film thickness dox ₁ , dox ₂ and area S ₁ .

FIGS. 4A and 4B are diagrams showing an example of the structure of a general semiconductor input circuit.

FIG. 4A shows an N-type silicon substrate 31.
A P-type conductive region 32 formed therein and a silicon substrate 32
And a metal wiring layer 34 formed with an oxide film 33 on conductive region 32 interposed therebetween, to form a capacitor. In FIG. 4B, a metal wiring layer 37 formed on the silicon substrate 35 with the oxide film 36 interposed therebetween and a metal wiring layer 38 formed on the metal wiring layer 37 with the oxide film 38 interposed therebetween are formed. Constitutes a capacitor.

In the case of such a capacitive element having any of the configurations shown in FIGS. 4A and 4B, configuring a large-capacity capacitor in an IC has been a problem from the viewpoint of the area occupied by a chip. . However, if a capacitor is directly formed directly below a bonding pad (input pad) as in the present invention, also using the pad, the area occupied on a chip can be increased without requiring an additional step in a manufacturing process. Can solve the problem.

Further, as an application example in which the capacitor voltage division coupling by the capacitance voltage division circuit is used, the input voltage level is reduced and supplied to the internal circuit, so that it is used when the withstand voltage of the internal circuit cannot be made higher than the input voltage level. be able to.

The present invention is not limited to the above-described embodiment, but can be variously modified without departing from the gist thereof. The above-described configuration in which a semiconductor integrated circuit having a withstand voltage of 3V processes a logic signal having a voltage amplitude of 5V may be modified to, for example, a configuration in which a semiconductor integrated circuit having a withstand voltage of 2.5V processes a logic signal having a voltage amplitude of 3V. good.

[0036]

As described above, according to the present invention, it is possible to obtain a signal output obtained by dividing the voltage of a signal input to a bonding pad by a capacitor. In addition, no additional steps are required in the manufacturing process, and no area is occupied on the chip.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to one embodiment of the present invention.

FIG. 2 is a view schematically showing a manufacturing process of the semiconductor integrated circuit shown in FIG. 1;

FIG. 3 is a diagram for explaining how to obtain a divided potential in the semiconductor integrated circuit shown in FIG. 1;

FIG. 4 is a diagram showing an example of the structure of a general semiconductor input circuit.

FIG. 5 is a circuit diagram showing a configuration of a general conventional semiconductor input circuit.

FIG. 6 shows depletion M to reduce leakage current.
FIG. 11 is a circuit diagram showing a configuration of another conventional semiconductor input circuit using an OS transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Input pad, 12 ... Capacitance voltage dividing circuit, 12a ... Capacitor, 12b ... Capacitor, 13 ... Voltage limiting circuit, 14 ... Latch circuit, 15 ... Pull-down resistor, 16 ... CMOS inverter SB ... Substrate, 21 ... Conductive area, 22 ... Oxide film, 23 ... Metal wiring layer, 24 ... Oxide film, 25 ... Metal wiring layer, 26 ... Oxide film, IM ... Semiconductor input circuit, LM ... Logic circuit module, DT ... Detection circuit.

Claims (7)

[Claims] 1. An input pad for receiving a logic signal exceeding a predetermined voltage amplitude, a capacitor voltage dividing circuit connected to the input pad, and a logic signal supplied via the capacitor voltage dividing circuit being connected to the predetermined voltage amplitude. And a detecting means for detecting a logic signal having a voltage amplitude limited by the voltage limiting circuit as an input signal, wherein the capacitance voltage dividing circuit is connected in series between the input pad and the voltage limiting circuit. A semiconductor input circuit comprising a connected first capacitor and a second capacitor connected between the voltage limiting circuit and a power supply terminal. 2. The first capacitor includes an electrode that is a part of a wiring connected to the input pad, and an electrode that is a part of a wiring connected to the voltage limiting circuit and the detecting unit. 2. The semiconductor input circuit according to claim 1, wherein said second capacitor is constituted by an electrode which is a part of a wiring connected to said voltage limiting circuit and said detecting means, and a conductive region in a substrate. . 3. The apparatus according to claim 1, wherein said detecting means includes a latch circuit for latching a logic signal having a voltage amplitude limited by said voltage limiting circuit, and a pull-down resistor for setting an initial value of said latch circuit. A semiconductor input circuit as described in the above. 4. The capacitance C of the capacitance voltage dividing circuit,
2. The semiconductor input circuit according to claim 1, wherein a relationship between a resistance R of the pull-down resistor and a frequency f of the logic signal is f <10 · C · R. 3. 5. The semiconductor input circuit according to claim 1, wherein said voltage limiting circuit is a diode clamp circuit. 6. An input pad for receiving a logic signal exceeding a predetermined voltage amplitude, a capacitor voltage dividing circuit connected in series to the input pad, and a logic signal supplied via the capacitor voltage dividing circuit being supplied to the input pad. Forming, on a semiconductor substrate, a voltage limiting circuit for limiting the voltage amplitude to a voltage amplitude, and detecting means for detecting, as an input signal, a logic signal having the voltage amplitude limited by the voltage limiting circuit; Forming a wiring connected to the input pad so as to have a portion constituting a first electrode of a first capacitor of the voltage circuit; and a second electrode of the first capacitor and the first electrode.
Forming a wiring connected to the voltage limiting circuit and the detecting means so as to have a portion constituting a first electrode of a second capacitor also serving as a second electrode of the capacitor; Forming a conductive region as a second electrode of the second capacitor; and forming a first insulating film between the first electrode of the first capacitor and the second electrode of the first capacitor. Forming a second insulating film between a first electrode of the second capacitor and a second electrode of the second capacitor. 7. The step of forming the first insulating film includes a step of forming the insulating film on the semiconductor substrate together with an insulating film between a first metal wiring layer and a second metal wiring layer. 7. The method for manufacturing a semiconductor input circuit according to claim 6, wherein: