JPH09148576A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacture method of a semiconductor device having a micro MOS transistor whose channel area is a groove type. SOLUTION: For forming the MOS transistor, a reverse conducting type diffusion layer is formed on the surface of a one conducting type semiconductor substrate where an element separation insulating film is not formed. Then, the insulating film where the element separation insulating film and the diffusion layer are covered and stacked is formed. The insulating film is hollowed out in a gate electrode pattern form and an insulating film groove is formed. The insulating film of the gate electrode pattern which is hollowed out is made into an etching mask. The diffusion layer and the semiconductor substrate under the diffusion layer are selectively dry-etched. The diffusion layer is separated into two areas and recessed parts lying in the semiconductor substrate are formed. Gate insulating film is formed on the side wall of the recessed part and a conductive material is buried in the insulating film groove so as to form a gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an insulated gate field effect transistor having a groove type channel region.

[0002]

2. Description of the Related Art A semiconductor device having an insulated gate field effect transistor (hereinafter referred to as a MOS transistor) as a semiconductor element is required to be further miniaturized in order to improve its operating speed and increase the degree of integration. Therefore, the gate / channel length of a MOS transistor is about 0.35 μm or less at a practical level.

In such a short-channel-length MOS transistor, depending on the method of use, the short-channel effect (shortening the gate length lowers the threshold voltage,
The phenomenon that the element does not become non-conductive) becomes remarkable, and the normal transistor structure cannot be used. Or M
It is known that the breakdown voltage between the source and drain of an OS transistor is lowered due to a phenomenon called punch through. This punch-through is due to the fact that the depletion layer extending from the drain region reaches the source region and current flows in the substrate other than the channel region.

Conventionally, in order to suppress such a short channel effect or the above punch-through phenomenon, the source and drain regions are raised from the surface of the semiconductor substrate, or a channel is formed in a U-shaped groove provided on the surface of the semiconductor substrate. By forming it, the channel length is effectively lengthened.

Among these, the conventional channel region has a groove type M.
A method of manufacturing a semiconductor device having an OS transistor is described in, for example, Japanese Patent Laid-Open No. 59-99771.
The technique described in this known example will be described below with reference to FIG. 6A to 6D are cross-sectional views in the manufacturing process order of the groove type MOS transistor.

As shown in FIG. 6A, the silicon substrate 1
On the surface of 01, the field oxide film 102 and the channel stopper region 10 are selectively formed by the normal LOCOS method.
3 is formed. Then, the field oxide film 102
MOS is formed in the region where the
An impurity diffusion layer 104 to be the source or drain region of the transistor is formed. Further, a thick silicon oxide film 105 having a thickness of usually about 1 μm is deposited on the entire surface of the wafer by the chemical vapor deposition (CVD) method.

Next, as shown in FIG. 6B, using the resist mask 106 as an etching mask for reactive ion etching (RIE), the impurity diffusion layer 104 serving as a channel region and the inside of the silicon substrate 101 are selectively etched. The U-shaped groove 107 is formed by etching. At the same time, the impurity diffusion layer 104 is separated and the source region 108 and the drain region 109 are formed.

Next, as shown in FIG. 6 (c), a U-shaped groove 1 is formed.
The surface of 07 is thermally oxidized to form a gate oxide film 110. Then, the gate electrode 111 is formed of a conductive material such as polycrystalline silicon so as to cover the gate oxide film 110. Here, the gate electrode 111 is formed by patterning by a fine processing technique using a photolithography technique and a dry etching technique. Next, a protective insulating film 112 that covers the gate electrode 111 thus patterned is formed.

Next, as shown in FIG. 6D, a source electrode 113 and a drain electrode 114 which are respectively connected to the source region 108 and the drain region 109 are formed.

In this manner, a MOS transistor having a groove-shaped channel region having the U-shaped groove 107 as a channel region and the patterned gate electrode 111, the source region 108 and the drain region 109 is formed on the surface of the silicon substrate 101. To be done.

[0011]

A major problem in forming a MOS transistor having a groove type channel region by such a conventional technique is that a gate electrode pattern is formed in a U-shaped groove pattern in a photolithography process. When aligning, a margin for alignment between these patterns is required. This makes it difficult to miniaturize the MOS transistor. Then, higher integration, higher density, and higher speed of the semiconductor device cannot be promoted.

To explain this reason in more detail, when forming the gate electrode pattern after forming the U-shaped groove, it is necessary to separately form the gate electrode pattern for the U-shaped groove and the gate electrode. During the photolithography process of the gate electrode, it is necessary to perform alignment with the U-shaped groove. In this case, a positioning error occurs due to the positioning accuracy of the exposure apparatus, and in an extreme case, the end of the gate electrode pattern is located inside the U-shaped groove, and as a result, the silicon at the drain end is located. There is a possibility that the current density of the transistor may decrease due to the expansion of the depletion layer on the substrate surface. In order to prevent this, the gate electrode pattern needs to have a positioning margin with respect to the U-shaped groove pattern in advance. However, M
The plane area of the OS transistor increases, which is disadvantageous for the downsizing of the semiconductor device.

An object of the present invention is to solve the above problems,
It is an object of the present invention to provide a method for manufacturing a semiconductor device having a MOS transistor whose channel region suitable for miniaturization has a groove type.

[0014]

To this end, in the method of manufacturing a semiconductor device of the present invention, in forming a MOS transistor, an element isolation insulating film is selectively formed on the surface of a semiconductor substrate of one conductivity type, and A step of forming a diffusion layer of opposite conductivity type on the surface of the semiconductor substrate on which an element isolation insulating film is not formed; a step of forming an insulating film that covers and laminates the element isolation insulating film and the diffusion layer; And a step of forming an insulating film groove by forming the insulating film in a gate electrode pattern of the insulated gate field effect transistor.

Further, in the method for manufacturing a semiconductor device of the present invention, after the insulating film is hollowed into the gate electrode pattern, the hollowed gate electrode pattern-shaped insulating film is used as an etching mask to form the diffusion layer and the diffusion layer. A step of selectively dry etching the lower semiconductor substrate to divide the diffusion layer into two regions to form a recess extending inside the semiconductor substrate; and forming a gate insulating film on the sidewall of the recess,
Embedding a conductor material in the insulating film groove to form a gate electrode.

Here, the insulating film is composed of a silicon nitride film and a silicon oxide film laminated with the silicon nitride film interposed therebetween.

The diffusion layer divided into the two regions constitutes the source / drain regions of the insulated gate field effect transistor.

As described above, according to the present invention, the diffusion layer is divided into two by using the insulating film groove having the gate electrode pattern shape of the MOS transistor to form the source / drain regions of the MOS transistor. Further, the groove of the channel portion of the MOS transistor is formed by using this insulating film groove, and the gate electrode is buried in the channel portion and the insulating film groove via the gate insulating film.

Therefore, the gate electrode is formed so as to be completely self-aligned with the source / drain regions. Then, the alignment between the gate electrode pattern and the groove pattern becomes unnecessary.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. In FIG. 1, the channel region has a groove type M.
It is a top view of an OS transistor. Here, the groove-shaped channel region is shaded. FIG. 2 (a)
2 is a cross-sectional view taken along the line AB in FIG.
(B) is a sectional view similarly cut along CD.

As shown in FIG. 1, in a MOS transistor, a gate electrode 6 is provided in a U-shaped groove 4, and a source region 11 and a drain region 12 are sandwiched by the gate electrode 6.
Are formed. The source region 11 is the source
It is connected to the source electrode 13 through the contact hole 11 '. Drain area is drain contact hole 12 '
It is connected to the drain electrode 14 through. The gate electrode 6 is connected to the gate wiring 15 through the gate contact hole 6 '.

Next, the structure of the groove type MOS transistor will be described with reference to FIG. As shown in FIG. 2, a field oxide film 2 and a channel stopper region 3 are selectively formed as an element isolation region on the surface of a silicon substrate 1. Then, a U-shaped groove 4 extending inside the silicon substrate 1 is formed, and a gate oxide film 5 is formed on the inner wall of the U-shaped groove 4. The gate electrode 6 is a first silicon oxide film 7 formed by stacking as shown in FIG.
It is provided so as to be embedded in the silicon nitride film 8, the insulating film groove provided in the second silicon oxide film 9, and the U-shaped groove 4. Further, as shown in FIG. 2B, the gate electrode 6 is similarly provided on the first silicon oxide film 7, the silicon nitride film 8 and the second silicon oxide film 9 when viewed from the channel direction. Is buried in the groove.

Then, as shown in FIGS. 2A and 2B, the gate electrode 6 is covered with the third silicon oxide film 10.

As shown in FIG. 2A, the source region 11 and the drain region 12 are formed, and the first silicon oxide film 7, the silicon nitride film 8 and the second silicon oxide film 9 are formed.
Are connected to the source electrode 13 and the drain electrode 14, respectively, through the contact holes provided in. Similarly,
As shown in FIG. 2B, the gate electrode 6 is connected to the gate wiring 15 through a contact hole formed in the third silicon oxide film 10.

Next, a method of manufacturing the semiconductor device of the present invention will be described with reference to FIGS. 3 and 4 are cross-sectional views in the order of manufacturing steps of the semiconductor device of the present invention, and are cross-sectional views taken along the lines AB and CD in FIG. 1, which are plan views of a groove-type MOS transistor, respectively. Has become.

As shown in FIG. 3A, first, a LOCOS type field oxide film 2 is selectively formed on the surface of a silicon substrate 1, and a dose amount for isolation between elements is 5 × 10 ¹² cm ^-2.
A channel stopper region 3 formed by ion implantation of boron (B) or phosphorus (P) or the like is formed. Here, the film thickness of the field oxide film 2 is 0.2 μm.
It is about m to 0.6 μm.

Next, phosphorus (P), arsenic (As), boron difluoride (BF ₂ ), boron (B), etc., are added to the active region where the element is formed on the surface of the silicon substrate 2 by 2 ×.
The impurity diffusion layer 16 to be the source / drain regions is formed by ion implantation or the like of about 10 ¹⁵ cm ⁻² .

The selection of such impurities is carried out in accordance with the N-channel or the P-channel of the MOS transistor as usual.

Next, a first silicon oxide film 7 having a film thickness of about 20 nm is deposited on the entire surface by a CVD method or a thermal oxidation method, and subsequently a silicon nitride film 8 having a film thickness of about 100 nm is deposited on the entire surface by a CVD method. Further, a second silicon oxide film 9 having a film thickness of about 200 nm is deposited by the CVD method. As a result, an interlayer insulating film having a film thickness of about 300 nm, which is composed of a plurality of laminated insulating layers of a silicon oxide film and a silicon nitride film, is formed on the entire surface.

Next, as shown in FIG. 3B, after the second silicon oxide film 9 is etched by anisotropic RIE using the resist mask 17 as an etching mask to expose the silicon nitride film 8, Subsequently, the silicon nitride film 8 is etched by anisotropic RIE to expose the first silicon oxide film 7. Further, the first silicon oxide film 7 is exposed by RIE or wet etching with a hydrofluoric acid (HF) solution to expose the surface of the silicon substrate 1. In this way, the interlayer insulating film groove 18 is formed.

Then, the silicon substrate 1 by anisotropic RIE using the pattern of the interlayer insulating film groove 18 as a mask.
The U-shaped groove 4 is formed through the selective etching of the surface of the.

By forming the U-shaped groove 4, the impurity diffusion layer 16 is divided at the same time and the source region 11 and the drain region 12 are formed.

The series of anisotropic RIE will be described in detail with reference to FIG. As shown in FIG. 4A, first, by using the resist mask 17 having the pattern shape of the gate electrode 6 as an etching mask, a high etching selectivity (about 18) with respect to the silicon nitride film 8 can be obtained. RIE is used to etch the second silicon oxide film 9. Then, the silicon nitride film 8 is exposed. Here, this anisotropic RIE is, for example, a plasma discharge power of 600 W and a plasma gas pressure of 8 P.
Under a, it is a magnetron type reactive ion etching in which CHF ₃ gas and CO gas are used as etching gases. The flow rate ratio of these etching gases is, for example, CH.
F ₃ gas flow rate / CO gas flow rate = 20 sccm / 80 sc
cm. The strength of the magnetic field applied to the etching region is about 400 gauss.

Next, as shown in FIG. 4B, using the resist mask 17 as an etching mask, silicon nitriding is performed by using anisotropic RIE capable of obtaining a high etching selection ratio (about 8) with respect to the silicon oxide film. The film 8 is etched to expose the first silicon oxide film 7.

Such anisotropic RIE is performed, for example, with a plasma discharge power of 1300 W and a plasma gas pressure of 10 Pa.
Under nitrogen, using nitrogen gas (N ₂ ) as a carrier gas, CF
Dry etching is performed using ₄ gas and O ₂ gas as etching gas. The flow rate ratio of these etching gases is, for example, CF ₄ gas flow rate / O ₂ gas flow rate = 60 scc
It is m / 40 sccm.

Next, as shown in FIG. 4C, the first silicon oxide film 7 is dry-etched by anisotropic RIE using the resist mask 17 as an etching mask, and the surface of the impurity diffusion layer 16 and the field oxidation are oxidized. The membrane 2 is exposed.

Such anisotropic RIE uses CF ₄ with argon (Ar) gas as a carrier gas under a plasma power of 400 W and a plasma gas pressure of 60 Pa.
The dry etching is performed using gas and CHF ₃ gas as etching gas. The flow rate ratio of these gases is, for example, CF ₄ gas flow rate / CHF ₃ gas flow rate = 20 sccm /
It is 20 sccm.

The first silicon oxide film 7 may be etched by wet etching using a hydrofluoric acid (HF) solution.

Next, as shown in FIG. 4D, the silicon substrate 1 is dry-etched by anisotropic RIE using the resist mask 17 as an etching mask. And
A U-shaped groove 4 having a depth of about 0.5 μm is formed. At this time, the field oxide film 2 is etched by about 10 nm, but the field oxide film thickness immediately before etching is 200 nm.
The silicon substrate under the field oxide film 2 is not exposed during the etching because it is above a certain level. Therefore, no U-shaped groove is formed in the field oxide film 2 region.

The anisotropic RIE condition of the silicon substrate 1 is, for example, under a plasma discharge power of 1000 W and a plasma gas pressure of 3 Pa, using argon (Ar) gas as a carrier gas and etching Cl ₂ gas and N ₂ gas. It is dry etching performed as a gas. The flow rate ratio of these gases is, for example, Cl ₂ gas flow rate / N ₂ gas flow rate = 50 s.
It is ccm / 5sccm.

In this way, the U-shaped groove 4 is formed in the gate electrode formation region on the surface of the silicon substrate 1.

Next, as shown in FIG. 3C, the resist mask 17 is removed, and subsequently 2 × 10 ^{12 to} 5 × 10 ¹² cm ^{-2 is} used for adjusting the threshold voltage of the MOS transistor.
Impurity ions 19 such as boron (B) or phosphorus (P) are introduced to the bottom surface and side walls inside the U-shaped groove 4 by rotational oblique ion implantation. Here, the rotating oblique ion implantation conditions are an oblique angle = 30 degrees and a rotation speed = 1.6 rps. Further, as the mask for the rotary oblique ion implantation, an interlayer insulating film in which the first silicon oxide film 7, the silicon nitride film 8 and the second silicon oxide film 9 are laminated is used.

Next, a gate oxide film having a desired thickness is formed on the surface of the silicon substrate 1 inside the U-shaped groove 4 by a thermal oxidation method, and polycrystalline silicon as a gate electrode material is formed on the entire surface to a thickness of about 600 nm. After the film is formed, N-type impurities such as phosphorus (P) are thermally diffused in the polycrystalline silicon and converted into the N-type polycrystalline silicon film.

As a method of forming the gate electrode material,
Besides this, silane (SiH ₄ ) gas and phosphine (P
There is a method of growing an N-type doped amorphous silicon film by a low pressure (LP) CVD method using H ₃ ) gas as a raw material gas.

Next, as shown in FIG. 3D, isotropic R
The N-type polycrystalline silicon film is etched back by using IE to etch the first silicon oxide film 7, the silicon nitride film 8 and the second silicon oxide film 9 in the U-shaped groove 4 and in the gate electrode pattern. An N-type polycrystalline silicon film is buried in the interlayer insulating film groove 18 made of. Then, the gate electrode 6 is formed.

The conditions for such etch back are:
For example, plasma power 500W, plasma gas pressure 6
This is an isotropic RIE in which SF ₆ gas is used as an etching gas under 0 Pa. Here, the flow rate of SF ₆ gas is set to about 100 sccm.

Further, instead of etch back, a polycrystalline silicon film using a chemical mechanical polishing (CMP) method, or
A method of polishing an amorphous silicon film may be used.
In such a CMP method, for example, a silicon abrasive and a polishing cloth are used, and polishing is performed under the conditions of a polishing rotation speed of 60 rpm and a polishing pressure of 200 g / cm ² .

Next, a third silicon oxide film 10 is deposited to a film thickness of about 400 nm as an interlayer insulating film. Then, the first silicon oxide film 7, the silicon nitride film 8, the second
Source electrode 13 connected to the source region 11 and the drain region 12 through the contact holes formed in the silicon oxide film 9 and the third silicon oxide film 10, respectively.
And the drain electrode 14 is formed.

As described above, the MOS transistor having the channel region formed in the groove is formed.

In the above-described embodiment, the gate electrode 6 of the MOS transistor is formed in self alignment with the U-shaped groove and the interlayer insulating film groove. Therefore, the method of the present invention is a simpler manufacturing method than the method of manufacturing the groove type MOS transistor described in the above publication. Further, it is not necessary to align the gate electrode pattern with the U-shaped groove pattern. Therefore, it is not necessary to secure the alignment margin between the gate electrode pattern and the U-shaped groove, and the area occupied by the semiconductor element is reduced.

Next, another method of manufacturing the semiconductor device of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view in the order of the manufacturing steps. Here, the steps up to the step of forming the U-shaped groove 4 are the same as those described with reference to FIG.

The interlayer insulating film groove and the U-shaped groove formed in the first silicon oxide film 7, the silicon nitride film 8 and the second silicon oxide film 9 have N containing impurities such as phosphorus (P). The gate electrode 6 is formed by filling the type polycrystalline silicon film.

Next, as shown in FIG. 5A, a titanium thin film 20 is deposited on the entire surface by a sputtering method to have a film thickness of about 50 nm. Subsequently, a silicidation reaction between the titanium thin film 20 and the N-type polycrystalline silicon film is performed by lamp annealing at a temperature of 700 ° C. to 900 ° C. for about 30 seconds.

Next, the second silicon oxide film 9 is immersed in a chemical solution of aqueous ammonia, hydrogen peroxide and pure water.
The unreacted titanium thin film remaining on the surface is removed by etching. In this way, the titanium silicide layer 21 is formed only on the surface of the gate electrode 6 as shown in FIG. 5B.

Next, a third silicon oxide film 10 is deposited as an interlayer insulating film to a film thickness of about 400 nm, and a contact hole reaching the surface of the source region 11 or the drain region 12 is opened. Subsequently, a source electrode 13 and a drain electrode 14 made of, for example, an aluminum alloy are formed, and the channel region as described in FIG. 2 has a groove type MO.
The S transistor is completed.

In this embodiment, as in the first embodiment, the alignment margin for the U-shaped groove of the gate electrode pattern becomes unnecessary. Further, in the first embodiment, the gate electrode 6 embedded in the U-shaped groove is composed of an N-type polycrystalline silicon film, whereas in this embodiment, the titanium silicide layer 21 is used. Are formed on the gate electrode made of this N-type polycrystalline silicon. Therefore, the gate electrode is reduced by about one digit compared with the case of the first embodiment. Then, the operation speed of the semiconductor device is significantly improved.

In the above embodiments, the case where the groove of the channel region is U-shaped has been described, but it should be noted that this groove is similarly formed in other shapes such as V-shaped. .

[0058]

As described above, the first effect of the present invention is that the occupied area of the MOS transistor, which is a semiconductor element, becomes small, and the high integration of the semiconductor device becomes advantageous.

The reason for this is that the gate electrode of the MOS transistor is formed in self-alignment with the U-shaped groove. Further, since the alignment with respect to the U-shaped groove is unnecessary, it is not necessary to secure the alignment margin between the gate electrode pattern and the U-shaped groove, and the area occupied by the semiconductor element is reduced. Considering the alignment accuracy of the current exposure equipment, the gate electrode pattern is less than that of the U-shaped groove.
It is necessary to take a positioning margin of about 25 μm,
According to the present embodiment, since this alignment margin is unnecessary, the channel width is 10 μm as the transistor size.
In this case, the occupied area of the semiconductor element can be reduced by about 20%.

A second effect is that the semiconductor device is manufactured by a simpler manufacturing method than the manufacturing method disclosed in Japanese Patent Laid-Open No. 59-97771 which is a conventional method for manufacturing a semiconductor device. is there.

The reason is that the gate electrode is formed in self-alignment with the U-shaped groove as described above, and the photolithography process is shortened by one process.

[Brief description of the drawings]

FIG. 1 is a plan view of a groove type channel MOS transistor for explaining the present invention.

FIG. 2 is a sectional view of a groove channel MOS transistor for explaining the present invention.

FIG. 3 is a cross-sectional view of the MOS transistor in the order of manufacturing steps.

FIG. 4 is a cross-sectional view of the MOS transistor in the order of manufacturing steps.

5A to 5C are cross-sectional views in the order of another manufacturing process of the MOS transistor.

FIG. 6 is a cross-sectional view in order of manufacturing steps for explaining a conventional technique.

[Explanation of symbols]

 1, 101 Silicon substrate 2, 102 Field oxide film 3, 103 Channel stopper region 4, 107 U-shaped groove 5, 110 Gate oxide film 6, 111 Gate electrode 6'Gate contact hole 7 First silicon oxide film 8 Silicon Nitride film 9 Second silicon oxide film 10 Third silicon oxide film 11 'Source contact hole 11,108 Source region 12,109 Drain region 12' Drain contact hole 13,113 Source electrode 14,114 Drain electrode 15 Gate Wiring 16,104 Impurity diffusion layer 17,106 Resist mask 18 Interlayer insulating film groove 19 Impurity ion 20 Titanium thin film 21 Titanium silicide layer 105 Thick silicon oxide film 112 Protective insulating film

Claims (4)

[Claims] 1. In the formation of an insulated gate field effect transistor, after a device isolation insulating film is selectively formed on the surface of a semiconductor substrate of one conductivity type, the surface of the semiconductor substrate on which the device isolation insulating film is not formed. A step of forming a diffusion layer of opposite conductivity type, a step of forming an insulating film that covers and laminates the element isolation insulating film and the diffusion layer, and the insulating film in a gate electrode pattern of the insulated gate field effect transistor. And a step of forming an insulating film groove by hollowing out. 2. The insulating film is hollowed into the shape of the gate electrode pattern, and then the diffusion layer and the semiconductor substrate thereunder are selectively dry-etched using the insulating film of the hollowed gate electrode pattern as an etching mask. Separating the diffusion layer into two regions and forming a recess extending into the semiconductor substrate; forming a gate insulating film on a sidewall of the recess; and then filling a conductive material in the insulating film groove. A step of forming a gate electrode, and a method of manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is composed of a silicon nitride film and a silicon oxide film laminated with the silicon nitride film sandwiched therebetween. . 4. The method of manufacturing a semiconductor device according to claim 2, wherein the diffusion layer divided into the two regions constitutes a source / drain region of the insulated gate field effect transistor.