JPH09148546A - Master slice system integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remarkably improve performance.characteristic of a master slice system LSI, such as speed, consumpsion power, level of integration and logic level. SOLUTION: Two or more P channel type MOS transistors wherein sources or drains are connected in common, and two or more N channel type MOS transistors wherein sources or drains are connected in common are arranged facing to each other. The respective gates of the P channel type and the N channel type MOS transistors are isolated. Concerning the contact for connecting the gates of the transistors with a first wiring layer, a dynamic circuit is constituted as the structure which can be arranged only in the region between the P channel type and the N channel type MOS transistors which are arranged facing to each other. In the dynamic circuit, input terminals are arranged on the upper layer of a basic cell, through which terminals all reference clock signals are inputted in storage circuits and gate circuits which constitute function cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device according to a master slice system, and more particularly to a master slice array
By configuring all circuit functions with a dynamic circuit and optimally setting the channel width of the transistor,
The present invention relates to an integrated circuit device capable of greatly improving speed, power consumption, and integration degree.

[0002]

2. Description of the Related Art As one form of a master slice type integrated circuit device, in an embedded array in which a block area is embedded, as shown in FIG. 9, in which a gate array and basic cells of the gate array are arranged in a matrix. Have used a plurality of basic cells arranged in at least one direction in the block area, provided wiring on the basic cells, formed functional cells having a logical function, and arranged and wired these cells.

5 and 7 show a latch and a composite gate circuit based on a typical conventional basic cell structure, in which a physical wiring method is provided on the basic cell.

Here, in order to form a functional cell having a logical function, a static circuit as shown in FIGS. 6 and 8 is adopted.

Further, the transistors shown in FIGS. 5 and 7 are shaped so that the second contacts can be used at both ends in the channel width direction.

[0006]

However, in the above-mentioned prior art, since only the static circuit is used to form the above-mentioned functional cell, a) logic design using a logic synthesis tool or the like. The substantial increase in the logic circuit scale, which is proportional to the dramatic improvement in productivity, b) The speedup of the circuit to secure a large amount of information processing capability, and c) The power consumption of the entire chip due to the demand for one chip. For the problem of increase, we have no choice but to rely on the progress of process technology.

Therefore, compared with a full custom design in which a dynamic circuit is positively adopted for a substantial logic function regardless of a memory circuit, a logic gate circuit, etc., even if the same process technology is used, In terms of integration, speed, and power consumption during operation, there are several fold differences.

These gate circuits are designed to improve the speed, power consumption, integration, logic level, etc., which are the original performances of the LSI, by using the circuit system, with the goal of high-mix low-volume production with the goal of short delivery time. In terms of aspects, it can be said that it is a sacrifice.

On the other hand, along with the progress of process technology, gate arrays and the like having a number of hundreds of thousands to nearly 1 million gates have appeared, and there is no unity such as a scrap, which is called a conventional glue logic. It is no longer the case of a gate array that deals only with circuits.
In other words, system-on-silicon large-scale LS
Conditions for developing I in the semi-custom field are now in place.

With such a circuit scale, the chip itself has a system clock, a bus line, etc.
It will be a cohesive system that also has functional blocks such as M, ROM, ALU, and registers.

Even when the gate array or embedded array itself has a system clock,
The function cells used internally do not use any dynamic circuits and are composed of conventional static circuits only. This increases the number of transistors required to realize the same circuit function, increases parasitic capacitance, and This leads to an increase in power consumption during operation, which hinders further functioning on a single chip.

However, the speed, the degree of integration, the power consumption, the logic level, etc. are optimized for each of the functional blocks described above, and the channel length and the channel width of the transistor used therein are unique to the functional cell level. It is not possible to adopt the full-custom or standard cell method, which is a nuisance.

This is because the specification of the system and the design are always changed during the development of such a large-scale circuit. In this case, basically, the manufacturing of the LSI must be restarted from the first step. This is because a product delivery delay and a cost are several times higher than those of a gate array in which a circuit can be changed only by a wiring process.

The present invention solves such a problem, and an object of the present invention is to provide a master slice that can be further optimized as an LSI including speed, power consumption, degree of integration, and logic level of a circuit. System semiconductor integrated circuit device.

[0015]

A master slice type integrated circuit device according to the present invention comprises: a) basic cells arranged in a matrix in a divided block area in an LSI chip; and b) in the block area. A plurality of first wiring layers for connecting the basic cells arranged in at least one direction in an upper layer of the basic cells to form a functional cell having a logical function; and c) the first wiring layer. Power supply wiring layers Vdd and Vss for supplying power to the basic cells, which are formed in the same layer as the wiring layer and in parallel along the one direction, and d) the basic cell has a source or a drain. Two or more P-channel type MOS transistors commonly connected to each other and two or more N-channel type MOS transistors commonly connected to their sources or drains are arranged to face each other; The gates of the P-channel and N-channel type MOS transistors arranged to face each other are separated, and f) the source and the drain of the P-channel and N-channel type MOS transistors, and a plurality of the first wiring layers. A plurality of first contacts to be connected and a plurality of second contacts to connect the gate of the transistor and the first wiring layer are provided, and g) the second contacts are arranged to face each other. A memory circuit and a gate circuit which are arranged only in a region between the P-channel and N-channel type MOS transistors, and which constitute a functional cell,
All of them are composed of a dynamic circuit having an input terminal for taking in a reference clock signal.

[0016]

According to the above-mentioned structure of the present invention, since the dynamic circuit which processes the input / output signal by storing the electric charge in the parasitic capacitance of the MOS transistor is employed, the conventional static circuit is used. The number of transistors, the number of circuit stages, and the input load capacity, which are necessary to realize functional cells having the same function, can be significantly reduced compared to the conventional one. Therefore, it is possible to realize high integration and high speed of the circuit as a whole.

Further, as the number of transistors forming the circuit decreases, the gate capacitance, the junction capacitance, the parasitic capacitance due to the wiring, etc. are also reduced, so that the power consumption during the high speed operation can be reduced.

Further, when the gate circuit is constructed by using the dynamic circuit, even if the use is biased to one channel type MOS transistor and the circuit is unbalanced with respect to the logic level and the like, the second contact is formed. The (wiring connection contact between the first-layer metal wiring and the polysilicon region) is arranged only in the region between the P-channel and N-channel type MOS transistors which are arranged opposite to each other, and each gate is separated. Thus, the logic level can be adjusted without changing the wiring pattern of the functional cell once formed on the basic cell.

From the above, the performance, speed, power consumption, degree of integration, and logic level of the LSI can be greatly improved.

[0020]

FIG. 10 is a schematic plan view of an entire chip according to an embodiment of the present invention. For one chip, five I / O cells are arranged in a ring around the chip,
Inside thereof, a basic cell matrix region of 3 in which basic cells of 2 are arranged in a matrix, and a RAM of 6 as a mega cell having a coherent function, R
A plurality of functional blocks having a function of a clock driver 7 are arranged to supply a clock to a block area 3 and a functional block 3 to form an OM and MPU.

Then, a plurality of basic cells on the basic cell matrix are used, wiring is performed thereon to form functional cells having a logical function, and these are arranged and wired. On the other hand, around the chip, wiring is provided on the bulk of each input / output cell to form a functional cell for input / output having a logical function, and these are arranged. Further, 4 is a wiring dedicated area for connecting the input / output cell and the internal functional cell.

FIG. 9 is a layout diagram showing a structure of a semiconductor device in which basic cells are arranged in a matrix in the embodiment of the present invention, and wiring is not provided.

In the layout diagrams of FIGS. 1, 3, 5, and 7, 101 is a P-type diffusion region, 102 is an N-type diffusion region, and a polysilicon region 103 extends vertically through these regions. A transistor having a channel width of Wp and Wn is formed.

Reference numeral 104 is an N-type diffusion region for a stopper of a P-channel transistor, 105 is a P-type diffusion region for a stopper of an N-channel transistor, and 106 respectively.
, And a part of the P-type substrate region 107.

Reference numeral 201 is a first layer VDD metal wiring, and 202 is a first layer VSS metal wiring.

Reference numeral 203 is a first layer metal wiring, and 204 is a second layer metal wiring, which is a wiring for transmitting an electric signal.

Reference numeral 205 is a contact for connecting the first layer metal wiring and the P type diffusion region, 206 is a contact for connecting the first layer metal wiring and the N type diffusion region, and 207 is a first layer metal wiring and the stopper P. A wiring connection contact with the type diffusion region, 208 is a wiring connection contact between the first layer metal wiring and the stopper N-type diffusion region, 209 is a wiring connection contact between the first layer metal wiring and the polysilicon region, 210
Is a through hole between the first layer metal wiring and the second layer metal wiring.

First layer VDD metal wiring 201 and 2
The first layer VSS metal wiring 02 is a wiring connection contact between the first layer metal wiring 208 and the stopper N-type diffusion area, and the wiring between the first layer metal wiring 207 and the stopper P-type diffusion area. The connecting contacts finally connect the N-type substrate region 106 and the P-type substrate region 107.

FIG. 1 shows a first embodiment of the present invention.
FIG. 6 is a layout diagram in which a dynamic latch circuit is configured by using a plurality of the basic cells 2 in the horizontal direction.

FIG. 2 is a transistor circuit diagram corresponding to the layout diagram of FIG.

In FIG. 2, while the clock (Φ) is Low, the transistors 201 and 204 are in a conductive state, so that the P-type diffusion region 101 and the N-type diffusion region 102 in FIG. , The drain junction capacitance occupies most of the capacitance, and the capacitance 205 is read by inverting the electric signal applied to the gates of the transistors 202 and 203, and the clock (Φ) is High.
During the period, the transistors 201 and 204 are turned off, so that the electric potential is stored by the electric charge stored in the capacitor 205.

FIG. 11 is a timing chart showing the operation of the above-mentioned latch circuit. As shown in the figure, 301 (Φ) which is the clock input signal and 3 of the opposite phase
In synchronization with 02 (/ Φ), the input signal 303 (D) is read when the clock is at the Low level, latched when the clock is at the High level, and output to 304 (/ M).

FIG. 5 is a layout diagram when a latch circuit having the same function as that of the first embodiment of the present invention is constituted by a conventional static circuit.

FIG. 6 is a transistor circuit diagram corresponding to the layout diagram of FIG. 5, and the timing diagram is the same as FIG. 11.

In FIG. 6, while the clock (Φ) is low, the transistors 601 and 604 forming the first clocked gate become conductive,
The electrical signal D applied to the gates of the transistors 602 and 603 is inverted and read, and further inverted by the transistors 609 and 609 which form the inverter, and the gates 606 and 607 of the transistors which form the second clocked gate. That is, up to (M) is read. At this time, the above-mentioned second clocked gate has the transistors 605 and 6 of the transistors constituting it.
No signal is transmitted because 08 is non-conductive.

When the clock (Φ) is in the high period, the outputs of the first clocked gate do not carry the input signal D because the transistors 601 and 604 are in the non-conducting state, and the second clocked gate does not transmit the input signal D. In the gate, since the transistors 605 and 608 of the transistors forming the gate are in the conductive state, the input can be transmitted to the output, the above-mentioned inverter and the latched state, and the above-mentioned (M)
The electric potential of is stored.

Comparing the first embodiment with the conventional example, the number of transistors used is 1 in FIG. 5 and FIG. 6 which are the conventional examples even though the circuits have the same function.
In FIG. 1 and FIG. 2, which is the first embodiment, the number of 0 is reduced to 4 and the input load capacitances for Φ and / Φ are reduced to about one half. Moreover, the number of gate stages in which the circuit operates is small. from these things,
The present invention can realize high integration and high speed of LSI as a whole. Furthermore, power consumption during high speed operation can be reduced.

FIG. 3 shows the second embodiment of the present invention.
FIG. 6 is a layout diagram in which a dynamic composite gate circuit is configured by using a plurality of the basic cells 2 in the horizontal direction.

FIG. 4 is a transistor circuit diagram corresponding to the layout diagram of FIG.

In FIG. 4, while the clock (Φ) is Low, the transistor 409 is in the conductive state and the transistor 410 is in the non-conductive state, so that the transistor 10 in FIG.
In the P-type diffusion region 1 and the N-type diffusion region 102, most of the drain junction capacitance occupies,
Electric charges are stored in the capacitor 411 from the power supply Vdd, and the output X becomes Vdd level.

When the clock (Φ) is in the High period, the transistor 409 is turned off and the transistor 410 is turned on, so that the charge stored in the capacitor 411 is transferred to the N-channel MOS transistors 405 and 406. Composed of 407 and 408,
X = ((A1∩A2) ∪B) ∩C is discharged or held according to the logical formula.

FIG. 12 is a timing chart showing the operation of the aforementioned composite gate circuit.

As shown in the figure, the input signals 402 (A1), 4 (4) are synchronized with the clock input signal 401 (Φ).
03 (A2), 404 (B), 405 (C) are High
At the time of the h level, the above logic is taken and output to 406 (X).

FIG. 7 is a layout diagram when a composite gate circuit having the same function as that of the second embodiment of the present invention is constituted by a conventional static circuit.

FIG. 8 is a transistor circuit diagram corresponding to the layout diagram of FIG.

Here, P-channel MOS transistors 801, 802, 803, 804 and N-channel MOS transistors 805, 806, 807, 8 are provided.
08, the above logical expression X = ((A1 ∩ A
2) ∪ B) ∩ C constitutes a static composite gate.

Comparing the second embodiment and the conventional example on the assumption that the entire LSI constitutes a cohesive system having a system clock, although the circuits having basically the same functions are used, Regarding the number, the number used in FIG. 7 and FIG. 8 which is the conventional example is reduced to 6 in FIG. 3 and FIG. 4 which is the second embodiment, and the input A1, A2, B, C
The input load capacity is about half compared to the conventional one, and if Wp and Wn are set appropriately, it is possible to avoid using a P-channel transistor having a lower mobility than an N-channel transistor in a static circuit as much as possible. it can.

Further, the gates of the P-channel and N-channel type MOS transistors arranged opposite to each other in the basic cell shown in FIGS. 1 and 3 have a terminal lead-out portion only in the central portion sandwiched by the respective transistors, That is, the wiring connection contact 209 is provided.
Therefore, the channel lengths Wp and Wn of the transistor
Is easily extended to the Vdd side 201 and the Vss side 202.

Also, the wirings of the first layer that make up the circuit and the contacts to the wirings of the first layer, 205, 206,
Reference numerals 207, 208, and 209 denote the first-layer Vdd power supply wiring 2 set in the channel length direction of each transistor.
01 and Vss power supply wiring 202 are configured to be completed in a region.

This is because when a gate circuit is constructed by using a dynamic circuit, one channel type MOS is used.
Even if the transistors are improperly used and the circuit is unbalanced with respect to the logic level, etc., the LSI can be used without changing the wiring pattern of the functional cell once constructed on the basic cell.
This is to adjust the overall logic level.

All the memory circuits and the gate circuits are constructed by the method according to the above-mentioned embodiment, and by using only these circuits in combination, high integration and high speed operation of the LSI as a whole and power consumption during high speed operation can be achieved. Can be achieved and the logic level can be optimized.

[0052]

As described above, according to the present invention, it is possible to greatly reduce the number of transistors, the number of circuit stages, and the input load capacitance required to realize functional cells having the same function. Therefore, there is an effect that high integration and high speed of the circuit can be realized as a whole.

Further, since the gate capacitance, the junction capacitance, the parasitic capacitance due to the wiring, etc. are reduced as the number of transistors forming the circuit is reduced, there is an effect that the power consumption during the high speed operation can be reduced.

Further, even if a gate circuit is constructed by adopting a dynamic circuit, the logic level can be adjusted without changing the wiring pattern which has already been subjected to the wiring processing to construct the functional cell. Have an effect. .

Further, there is an effect that the speed, power consumption, degree of integration, and logic level, which are the performances of the LSI as a whole, can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a layout diagram of a latch circuit according to an embodiment of the present invention.

FIG. 2 is a transistor circuit diagram of a latch circuit according to an embodiment of the present invention.

FIG. 3 is a layout diagram of a composite gate circuit according to an embodiment of the present invention.

FIG. 4 is a transistor circuit diagram of a composite gate circuit according to an embodiment of the present invention.

FIG. 5 is a layout diagram of a conventional latch circuit.

FIG. 6 is a transistor circuit diagram of a conventional latch circuit.

FIG. 7 is a layout diagram of a conventional composite gate circuit.

FIG. 8 is a transistor circuit diagram of a conventional composite gate circuit.

FIG. 9 shows basic cells of the present invention arranged in a matrix.
It is a layout diagram showing a configuration of a semiconductor device.

FIG. 10 is a schematic plan view of the entire chip according to the embodiment of the present invention.

FIG. 11 is a timing diagram of the latch circuit according to the embodiment of the present invention.

FIG. 12 is an AND-OR-NA according to an embodiment of the present invention.
It is a timing diagram of an ND gate circuit.

[Explanation of symbols]

1. . . Chip outline 2. . . Unit basic cell 3. . . Basic cell matrix 4. . . Area dedicated to wiring 5. . . Input / output cell 6. . . Functional block 7. . . Clock driver 101. . . P-type diffusion region 102. . . N-type diffusion region 103. . . Polysilicon region 104. . . N-type diffusion region for stopper 105. . . P-type diffusion region for stopper 106. . . N-type substrate region 107. . . P-type substrate region 201. . . First layer VDD metal wiring 202. . . First layer VSS metal wiring 203. . . First layer metal wiring 204. . . Second layer metal wiring 205. . . Contact for connection between first layer metal wiring and P type diffusion region 206. . . 207. Contact for connection between first layer metal wiring and N type diffusion region 207. . . A contact for wiring connection between the first-layer metal wiring and the stopper P-type diffusion region 208. . . A contact for wiring connection between the first layer metal wiring and the N-type diffusion region for stopper 209. . . Contact for wiring connection between first-layer metal wiring and polysilicon region 210. . . Through hole for first layer metal wiring and second layer metal wiring 301. . . Input clock waveform at terminal Φ 302. . . Opposite-phase input clock waveform at terminal ΦΦ 303. . . Input waveform at terminal D 304. . . Output waveform at terminal M 401. . . Input clock waveform at terminal Φ 402. . . Input waveform at terminal A1 403. . . Input waveform at terminal A2 404. . . Input waveform at terminal B 405. . . Input waveform at terminal C 406. . . Output waveform at terminal X

Claims (4)

[Claims] 1. A) basic cells arranged in a matrix in a divided block area in an LSI chip; and b) basic cells arranged in at least one direction in the block area. A plurality of first wiring layers that are connected in the upper layer of the basic cell to form a functional cell having a logical function; and c) parallel to the first wiring layer in the same direction as the first wiring layer. Power supply wiring layers Vdd and Vss for supplying power to the basic cell, and d) the basic cell includes two or more P-channel type MOS transistors whose sources or drains are commonly connected, and a source. Alternatively, two or more N-channel MOS transistors whose drains are commonly connected are arranged to face each other, and e) the P-channel and N-channel MOS transistors arranged to face each other. The gates of the respective transistors are separated, and f) a plurality of first contacts connecting the sources and the drains of the P-channel and N-channel MOS transistors and a plurality of the first wiring layers, and the transistor. A plurality of second contacts connecting the gate of the P-channel MOS transistor and the first wiring layer are provided, and g) the second contact is a region between the P-channel and N-channel MOS transistors arranged to face each other. And h) the memory circuit and the gate circuit that form the functional cell are
A master slice type integrated circuit device, characterized in that it is composed of a dynamic circuit, all of which has an input terminal for taking in a reference clock signal. 2. The power supply wiring layer Vd according to claim 1, wherein the first and second contacts are in the block region.
A master slice type integrated circuit device characterized by being completed in a region between d and Vss. 3. The wiring formed by the first wiring layer for forming the functional cell according to claim 1, is the power supply wiring layer V.
A master slice type integrated circuit device characterized by being completed in a region between dd and Vss. 4. The relative positions of the first and second contacts with respect to the power supply wiring layers Vdd and Vss are the P channel and N channel MOs.
A master-slice integrated circuit device, wherein the channel widths Wp and Wn of the S-transistor are constant even if they are expanded to the power supply wiring layers Vdd and Vss sides, respectively.