JPH09148496A - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method thereforInfo
- Publication number
- JPH09148496A JPH09148496A JP7306991A JP30699195A JPH09148496A JP H09148496 A JPH09148496 A JP H09148496A JP 7306991 A JP7306991 A JP 7306991A JP 30699195 A JP30699195 A JP 30699195A JP H09148496 A JPH09148496 A JP H09148496A
- Authority
- JP
- Japan
- Prior art keywords
- cavity
- semiconductor chip
- base substrate
- semiconductor device
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特に、キャビティを有するベース基
板のキャビティ内に半導体チップをフェースダウンボン
ディングしたキャビティダウン方式の半導体装置に適用
して有効な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a technique effective when applied to a cavity-down type semiconductor device in which a semiconductor chip is face-down bonded in a cavity of a base substrate having a cavity. Regarding
【０００２】[0002]
【従来の技術】半導体装置の代表として知られるＬＳＩ
は、多くの機能が要求されるにつれて集積度はより高ま
って、ますます多ピン化の傾向にある。また、最近では
より高速化されたＬＳＩの要求が広まっており、これに
伴い半導体チップで大量の熱が発生するので、この熱の
対策が重要になっている。2. Description of the Related Art LSIs known as representatives of semiconductor devices
As the number of functions is required, the degree of integration is increasing and the number of pins is increasing. Further, recently, a demand for a higher-speed LSI has spread, and accordingly, a large amount of heat is generated in a semiconductor chip. Therefore, measures against this heat have become important.
【０００３】このような観点から、最近のＬＳＩとして
キャビティダウン方式のパッケージを有するものが提供
されている。例えば、日経ＢＰ社発行、１９９３年５月
３１日発行、「ＶＬＳＩパッケージング技術（下）」、
Ｐ２０７には、そのようなＬＳＩが示されている。From such a viewpoint, a recent LSI having a cavity-down type package has been provided. For example, “VLSI Packaging Technology (below)” issued by Nikkei BP, May 31, 1993,
Such an LSI is shown in P207.
【０００４】このキャビティダウン方式のＬＳＩは、例
えばＡｌＮのように熱伝導率の高いセラミックからなる
絶縁材料を用いて、キャビティを有するベース基板を構
成してそのキャビティ内に半導体チップをフェースダウ
ンボンディングし、半導体チップで発生した熱をこの裏
面から前記熱伝導率の高いベース基板に伝達させて周囲
空間に放熱するようにしたものである。あるいは、例え
ばＡｌ2Ｏ3のように熱伝導率の低いセラミックからなる
絶縁材料を用いてキャビティを有するベース基板を構成
した場合には、キャビティの中央部に貫通孔を設けると
ともに、ベース基板の上面に例えばＣｕ−Ｗなどからな
る放熱体を取り付け、キャビティ内に半導体チップを貫
通孔を通じてその放熱体に接着するようにフェースダウ
ンボンディングするようにして、半導体チップで発生し
た熱を放熱体に伝達させて周囲空間に放熱するようにし
たものである。In this cavity down type LSI, a base substrate having a cavity is formed by using an insulating material such as AlN having a high thermal conductivity, and a semiconductor chip is face down bonded in the cavity. The heat generated in the semiconductor chip is transferred from the back surface to the base substrate having high thermal conductivity to be radiated to the surrounding space. Alternatively, when the base substrate having a cavity is formed by using an insulating material made of a ceramic having a low thermal conductivity such as Al 2 O 3 , a through hole is provided at the center of the cavity and the upper surface of the base substrate is formed. A heat radiator made of Cu-W, for example, is attached to the heat sink, and the heat generated in the semiconductor chip is transferred to the heat sink by face down bonding so that the semiconductor chip is bonded to the heat sink through the through hole. It radiates heat to the surrounding space.
【０００５】ここで、ベース基板の底面にはピン状ある
いはボール状の実装用電極が配置されており、フェース
ダウンボンディングされている半導体チップの表面の電
極とキャビティの周囲位置のベース基板に設けられた導
電層との間には、例えばＡｕ、Ａｌなどからなるワイヤ
がボンディングされて、各導電層とこれに対応した実装
用電極との間はベース基板内の多層配線を通じて導通さ
れている。ＬＳＩを各種電子機器に組み込む場合には、
実装用電極を配線基板に実装することにより行われる。Here, a pin-shaped or ball-shaped mounting electrode is arranged on the bottom surface of the base substrate, and is provided on the electrode on the surface of the semiconductor chip which is face-down bonded and on the base substrate around the cavity. A wire made of, for example, Au or Al is bonded to the conductive layer, and the conductive layer and the corresponding mounting electrode are electrically connected through a multi-layer wiring in the base substrate. When incorporating the LSI into various electronic devices,
This is performed by mounting the mounting electrodes on the wiring board.
【０００６】このようにキャビティダウン方式のＬＳＩ
では、半導体チップをフェースダウンボンディングする
ことによりその表面の電極にワイヤボンディングを行っ
て多ピン化に対処させるとともに、その裏面からは放熱
を行わせてパッケージの低熱抵抗化が図られている。Thus, the cavity down type LSI
In this case, the semiconductor chip is face-down-bonded to wire-bond the electrodes on the surface to cope with the increase in the number of pins, and heat is radiated from the back surface to reduce the thermal resistance of the package.
【０００７】ここで、キャビティダウン方式のＬＳＩで
パッケージ構造をより簡単にして低熱抵抗化を図るため
には、ベース基板のキャビティに設けた貫通孔から半導
体チップの裏面を露出させたままにすれば良い。しかし
ながら、この構造をとろうとすると、ＬＳＩの組立時に
半導体チップの表面の電極にワイヤボンディングを行う
際に、半導体チップを固定できないのでワイヤボンディ
ングが不可能になってしまう。このため、前記文献に示
されたような構造を採用せざるを得ない。Here, in order to further simplify the package structure and reduce the thermal resistance in the cavity down type LSI, it is necessary to leave the back surface of the semiconductor chip exposed through the through hole provided in the cavity of the base substrate. good. However, if this structure is adopted, the wire bonding becomes impossible because the semiconductor chip cannot be fixed when the wire bonding is performed on the electrodes on the surface of the semiconductor chip during the assembly of the LSI. Therefore, there is no choice but to adopt the structure shown in the above-mentioned document.
【０００８】[0008]
【発明が解決しようとする課題】前記のようなキャビテ
ィダウン方式のＬＳＩを組み立てる場合、パッケージの
低熱抵抗化を図るにはベース基板としてセラミックのよ
うな高価な絶縁材料を用いる必要があり、さらに、これ
に加えて放熱体を用いる必要があるので、コストアップ
になるという問題がある。When assembling the above-mentioned cavity down type LSI, it is necessary to use an expensive insulating material such as ceramic as the base substrate in order to reduce the thermal resistance of the package. In addition to this, since it is necessary to use a heat radiator, there is a problem that the cost increases.
【０００９】また、ベース基板の底面に配置する実装用
電極としてボール状電極を用いるＢＧＡ（Ｂａｌｌ Ｇ
ｒｉｄ Ａｒｒａｙ）パッケージ構造をとる場合には、
ボール電極を配線基板に実装する際に、放熱体の重みで
ボール電極が変形してしまうおそれがあるので、接続不
良や短絡不良などの不都合が生じ易くなる。Further, a BGA (Ball G) using a ball-shaped electrode as a mounting electrode disposed on the bottom surface of the base substrate.
Rid Array) package structure,
When the ball electrode is mounted on the wiring board, the ball electrode may be deformed due to the weight of the heat radiator, so that inconveniences such as connection failure and short circuit failure are likely to occur.
【００１０】本発明の目的は、キャビティダウン方式の
ＬＳＩを組み立てる場合、コストアップを伴うことなく
パッケージの低熱抵抗化を図ることが可能な技術を提供
することにある。It is an object of the present invention to provide a technique capable of reducing the thermal resistance of a package without increasing the cost when assembling a cavity down type LSI.
【００１１】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１２】[0012]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記の通りである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.
【００１３】（１）本発明の半導体装置は、キャビティ
を有するベース基板を用いて前記キャビティ内に半導体
チップをフェースダウンボンディングするとともに、前
記半導体チップの表面の電極と前記ベース基板の導電層
との間にワイヤをボンディングし、前記ベース基板の底
面に前記導電層と導通する実装用電極を配置した半導体
装置であって、前記キャビティの中央部に貫通孔を設け
てこの貫通孔から半導体チップの裏面を露出させ、前記
キャビティ内に半導体チップを封止する樹脂を充填して
いる。(1) In the semiconductor device of the present invention, a semiconductor chip is face-down bonded in the cavity using a base substrate having a cavity, and an electrode on the surface of the semiconductor chip and a conductive layer of the base substrate are formed. A semiconductor device, in which a wire is bonded between them, and a mounting electrode that is electrically connected to the conductive layer is arranged on the bottom surface of the base substrate, and a through hole is provided in the center of the cavity, and the through hole is used to form the back surface of the semiconductor chip. Is exposed and the cavity is filled with a resin for sealing the semiconductor chip.
【００１４】（２）本発明の半導体装置の製造方法は、
キャビティを有しこの中央部に貫通孔を設けたベース基
板を用意して、このベース基板の上面に前記貫通孔を覆
うように吸着手段を設ける工程と、この吸着手段によっ
て半導体チップをこの裏面から吸着して前記キャビティ
内に仮止めする工程と、前記半導体チップの表面の電極
と前記ベース基板の導電層との間にワイヤをボンディン
グする工程と、前記ベース基板の底面側からキャビティ
内に樹脂を充填する工程と、前記吸着手段を除去する工
程とを含んでいる。(2) The method of manufacturing a semiconductor device according to the present invention comprises:
A step of preparing a base substrate having a cavity and having a through hole in the center thereof, and providing a suction means on the upper surface of the base substrate so as to cover the through hole, and the semiconductor chip from the back surface by the suction means. A step of adsorbing and temporarily fixing in the cavity, a step of bonding a wire between the electrode on the surface of the semiconductor chip and the conductive layer of the base substrate, and a resin in the cavity from the bottom side of the base substrate. It includes a step of filling and a step of removing the adsorption means.
【００１５】上述した（１）の手段によれば、本発明の
半導体装置は、ベース基板のキャビティの中央部に貫通
孔を設けてこの貫通孔から半導体チップの裏面を露出さ
せ、前記キャビティ内に半導体チップを封止する樹脂を
充填しているので、キャビティダウン方式のＬＳＩを組
み立てる場合、コストアップを伴うことなくパッケージ
の低熱抵抗化を図ることが可能となる。According to the above-mentioned means (1), in the semiconductor device of the present invention, the through hole is provided in the central portion of the cavity of the base substrate, the back surface of the semiconductor chip is exposed from the through hole, and the inside of the cavity is exposed. Since the resin for sealing the semiconductor chip is filled, when assembling the cavity down type LSI, it is possible to reduce the thermal resistance of the package without increasing the cost.
【００１６】上述した（２）の手段によれば、本発明の
半導体装置の製造方法は、まず、キャビティを有しこの
中央部に貫通孔を設けたベース基板を用意して、このベ
ース基板の上面に前記貫通孔を覆うように吸着手段を設
ける。次に、この吸着手段によって半導体チップをこの
裏面から吸着して前記キャビティ内に仮止めした後、前
記半導体チップの表面の電極と前記ベース基板の導電層
との間にワイヤをボンディングし、続いて、前記ベース
基板の底面側からキャビティ内に樹脂を充填する。これ
により、ベース基板のキャビティの貫通孔から半導体チ
ップの裏面を露出させたパッケージ構造を実現すること
ができる。従って、キャビティダウン方式のＬＳＩを組
み立てる場合、コストアップを伴うことなくパッケージ
の低熱抵抗化を図ることが可能となる。According to the above-described means (2), in the method for manufacturing a semiconductor device of the present invention, first, a base substrate having a cavity and a through hole provided in the central portion thereof is prepared, and the base substrate is prepared. Adsorption means is provided on the upper surface so as to cover the through hole. Next, the semiconductor chip is sucked from this back surface by this suction means and temporarily fixed in the cavity, and then a wire is bonded between the electrode on the front surface of the semiconductor chip and the conductive layer of the base substrate. The cavity is filled with resin from the bottom side of the base substrate. Thus, it is possible to realize a package structure in which the back surface of the semiconductor chip is exposed from the through hole of the cavity of the base substrate. Therefore, when assembling a cavity down type LSI, it is possible to reduce the thermal resistance of the package without increasing the cost.
【００１７】以下、本発明について、図面を参照して実
施例とともに詳細に説明する。Hereinafter, the present invention will be described in detail with reference to the drawings together with embodiments.
【００１８】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１９】[0019]
（実施形態１）図１は本発明の実施形態１による半導体
装置を示す平面図で、ＰＧＡパッケージ構造をとるＬＳ
Ｉに適用した例で示している。図２は図１のＡ−Ａ断面
図である。(Embodiment 1) FIG. 1 is a plan view showing a semiconductor device according to Embodiment 1 of the present invention, which is an LS having a PGA package structure.
The example applied to I is shown. 2 is a sectional view taken along line AA of FIG.
【００２０】キャビティ１を有する例えばＢＴ樹脂など
からなる多層配線構造のベース基板２が用いられて、こ
のベース基板２のキャビティ１の中央部には貫通孔３が
設けられている。また、ベース基板２の底面にはピンか
らなる実装用電極８が配置されている。キャビティ１内
には貫通孔３内に配置されるように半導体チップ４がフ
ェースダウンボンディングされて、この半導体チップ４
の裏面４Ｂは貫通孔３から露出されている。A base substrate 2 having a multilayer wiring structure made of, for example, BT resin or the like having a cavity 1 is used, and a through hole 3 is provided in the central portion of the cavity 1 of the base substrate 2. Further, a mounting electrode 8 composed of a pin is arranged on the bottom surface of the base substrate 2. The semiconductor chip 4 is face-down bonded in the cavity 1 so as to be arranged in the through hole 3, and
The back surface 4B of is exposed from the through hole 3.
【００２１】半導体チップ４の表面４Ａの電極５とベー
ス基板２に設けられている導電層６との間には、例えば
Ａｕ、Ａｌなどからなるワイヤ７がボンディングされ、
各導電層６とこれに対応した実装用電極８との間はベー
ス基板２内の多層配線を通じて導通されている。ＬＳＩ
を各種電子機器に組み込む場合には、実装用電極８を配
線基板に実装することにより行われる。A wire 7 made of, for example, Au or Al is bonded between the electrode 5 on the surface 4A of the semiconductor chip 4 and the conductive layer 6 provided on the base substrate 2,
The conductive layers 6 and the corresponding mounting electrodes 8 are electrically connected through the multilayer wiring in the base substrate 2. LSI
When is mounted in various electronic devices, the mounting electrodes 8 are mounted on a wiring board.
【００２２】キャビティ１内には半導体チップ４を封止
するように例えばエポキシ樹脂からなる樹脂９が充填さ
れている。A resin 9 made of, for example, an epoxy resin is filled in the cavity 1 so as to seal the semiconductor chip 4.
【００２３】次に、図３乃至図７を参照して、本実施形
態１の半導体装置の製造方法を工程順に説明する。Next, with reference to FIGS. 3 to 7, the method for manufacturing the semiconductor device of the first embodiment will be described in the order of steps.
【００２４】まず、図３に示すように、キャビティ１を
有しこのキャビティ１の中央部に貫通孔３を設けた例え
ばＢＴ樹脂などからなる多層配線構造のベース基板２を
用意して、このベース基板２の上面に貫通孔３を覆うよ
うに例えばポリイミド樹脂からなる粘着性を有する耐熱
性テープ１０を用いてその粘着面１０Ａを接着する。こ
の耐熱性テープ１０は吸着手段として働き、約２００℃
程度までの耐熱性を有しており、また常温で接着及び剥
離が容易である。ベース基板２の底面にはピン状の実装
用電極８が取り付けられている。図４は、ベース基板２
のキャビティ１側からみた平面図である。図４では各導
電層６は一部のみ図示している。First, as shown in FIG. 3, a base substrate 2 having a multi-layer wiring structure made of, for example, BT resin, which has a cavity 1 and a through hole 3 provided in the central portion of the cavity 1, is prepared. The adhesive surface 10A is adhered to the upper surface of the substrate 2 so as to cover the through holes 3 by using an adhesive heat resistant tape 10 made of, for example, a polyimide resin. This heat-resistant tape 10 works as an adsorption means, and is about 200 ° C.
It has heat resistance up to a certain degree and is easy to bond and peel at normal temperature. A pin-shaped mounting electrode 8 is attached to the bottom surface of the base substrate 2. FIG. 4 shows the base substrate 2
FIG. 3 is a plan view seen from the side of a cavity 1. In FIG. 4, each conductive layer 6 is shown only partially.
【００２５】次に、図５に示すように、半導体チップ４
をキャビティ１内の貫通孔３内に配置して、この裏面４
Ｂを耐熱性テープ１０の粘着面１０Ａに常温で接着して
仮止めする。これによって、半導体チップ４をキャビテ
ィ１内にフェースダウンボンディングする。Next, as shown in FIG. 5, the semiconductor chip 4
Is placed in the through hole 3 in the cavity 1 and the back surface 4
B is adhered to the adhesive surface 10A of the heat resistant tape 10 at room temperature and temporarily fixed. As a result, the semiconductor chip 4 is face down bonded into the cavity 1.
【００２６】続いて、図６に示すように、裏面４Ｂが耐
熱性テープ１０に固定されている半導体チップ４の表面
４Ａの電極５と、ベース基板２に設けられている導電層
６との間に例えばＡｕ、Ａｌなどからなるワイヤ７をボ
ンディングする。このワイヤボンディング作業は約２０
０℃付近で行われるが、耐熱性テープ１０は十分にこれ
らの温度に耐えられる。Subsequently, as shown in FIG. 6, between the electrode 5 on the front surface 4A of the semiconductor chip 4 whose back surface 4B is fixed to the heat resistant tape 10 and the conductive layer 6 provided on the base substrate 2. A wire 7 made of, for example, Au or Al is bonded to the. This wire bonding work is about 20
Although performed at around 0 ° C., the heat resistant tape 10 can sufficiently withstand these temperatures.
【００２７】次に、図７に示すように、ベース基板２の
底面側からキャビティ１内に、例えばエポキシ樹脂から
なる樹脂９をポッテングすることにより充填する。これ
により、半導体チップ４は樹脂９によって封止される。Next, as shown in FIG. 7, the cavity 1 is filled from the bottom surface side of the base substrate 2 by potting a resin 9 made of, for example, an epoxy resin. As a result, the semiconductor chip 4 is sealed with the resin 9.
【００２８】続いて、耐熱性テープ１０を常温で剥離す
ることにより、図１及び図２に示したような半導体装置
が組み立てられる。このように、耐熱性テープ１０を剥
離しても、半導体チップ４は樹脂９によって封止されて
いるので、固定された状態が維持されている。Subsequently, the heat resistant tape 10 is peeled off at room temperature to assemble the semiconductor device as shown in FIGS. In this way, even if the heat-resistant tape 10 is peeled off, the semiconductor chip 4 is sealed with the resin 9, so that the fixed state is maintained.
【００２９】また、半導体チップ４の裏面４Ｂが貫通孔
３から露出されているので、半導体チップ４で発生した
熱は効率良く周囲空間に放熱される。さらに、これに基
づいて、ベース基板２の絶縁材料としては高価なセラミ
ックを用いることなく、樹脂のような安価な材料を用い
ることができるので、コストアップが避けられる。Further, since the back surface 4B of the semiconductor chip 4 is exposed from the through hole 3, the heat generated in the semiconductor chip 4 is efficiently radiated to the surrounding space. Further, based on this, an inexpensive material such as a resin can be used as the insulating material of the base substrate 2 without using an expensive ceramic, so that an increase in cost can be avoided.
【００３０】以上のような実施形態１によれば次のよう
な効果が得られる。According to the first embodiment, the following effects can be obtained.
【００３１】（１）ベース基板２のキャビティ１の中央
部に貫通孔３を設けてこの貫通孔３から半導体チップ４
の裏面４Ｂを露出させ、キャビティ１内に半導体チップ
４を封止する樹脂９を充填しているので、半導体チップ
４で発生した熱をこの裏面から放熱できるため、キャビ
ティダウン方式のＬＳＩを組み立てる場合、コストアッ
プを伴うことなくパッケージの低熱抵抗化を図ることが
可能となる。(1) A through hole 3 is provided in the central portion of the cavity 1 of the base substrate 2, and the semiconductor chip 4 is formed through the through hole 3.
Since the back surface 4B of the semiconductor chip 4 is exposed and the cavity 9 is filled with the resin 9 for sealing the semiconductor chip 4, the heat generated in the semiconductor chip 4 can be radiated from this back surface. It is possible to reduce the thermal resistance of the package without increasing the cost.
【００３２】（２）耐熱性テープ１０のように安価な材
料を用いて、半導体チップ４を仮止めした状態でワイヤ
ボンディング及び樹脂充填を行った後に耐熱性テープ１
０を除去するので、簡単な方法で半導体チップ４の裏面
４Ｂを露出させた半導体装置を製造することができる。(2) Using a heat resistant tape 10 such as a heat resistant tape 10, the semiconductor chip 4 is temporarily fixed and then wire bonding and resin filling are performed, and then the heat resistant tape 1
Since 0 is removed, a semiconductor device in which the back surface 4B of the semiconductor chip 4 is exposed can be manufactured by a simple method.
【００３３】図８は実施形態１による半導体装置を製造
する際の、半導体チップ４を仮止めする他の手段を示す
ものである。本例においては、真空吸着治具１１を吸着
手段として用いることにより、半導体チップ４の裏面４
Ｂを吸着して仮止めする。このような吸着手段によって
も、ワイヤボンディング及び樹脂充填を行った後に真空
吸着治具１１を取り外すことにより、同様な目的を達成
することができる。FIG. 8 shows another means for temporarily fixing the semiconductor chip 4 when manufacturing the semiconductor device according to the first embodiment. In this example, by using the vacuum suction jig 11 as the suction means, the back surface 4 of the semiconductor chip 4 is
Adsorb B and temporarily fix it. Even with such a suction means, the same object can be achieved by removing the vacuum suction jig 11 after performing wire bonding and resin filling.
【００３４】（実施形態２）図９は本発明の実施形態２
による半導体装置を示す断面図で、実装用電極８として
ボール状電極を用いた例を示すものである。(Second Embodiment) FIG. 9 shows a second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a semiconductor device according to the above, showing an example of using a ball-shaped electrode as a mounting electrode 8.
【００３５】このような実施形態２によれば、実施形態
１と同様な効果が得られる他に、ＢＧＡパッケージ構造
をとるＬＳＩの場合でも、放熱体を用いてないのでボー
ル状電極を配線基板に実装する際に、放熱体の重みでボ
ール状電極が変形してしまうおそれはないため、接続不
良や短絡不良などの不都合が生じないという効果が得ら
れる。According to the second embodiment as described above, in addition to the same effect as that of the first embodiment, even in the case of the LSI having the BGA package structure, since the heat radiator is not used, the ball-shaped electrode is used as the wiring substrate. Since there is no possibility that the ball-shaped electrode will be deformed by the weight of the heat radiator when mounting, it is possible to obtain the effect that no inconvenience such as connection failure or short circuit failure occurs.
【００３６】（実施形態３）図１０は本発明の実施形態
３による半導体装置を示す断面図で、実施形態１で得ら
れた半導体装置に対して、さらに低熱抵抗化を図るため
に、貫通孔３から露出されている半導体チップ４の裏面
４Ｂに、例えばＣｕのように熱伝導率の高い材料からな
る放熱フィン１２を例えばシリコーンゴムなどの絶縁性
接着剤１３を介して取り付けた構造を示すものである。
これは、実施形態１の半導体装置を各種電子機器の配線
基板に実装した後に、半導体チップ４の裏面４Ｂに放熱
フィン１２を取り付けることにより組み立てることがで
きる。(Third Embodiment) FIG. 10 is a cross-sectional view showing a semiconductor device according to a third embodiment of the present invention. In order to further reduce the thermal resistance of the semiconductor device obtained in the first embodiment, a through hole is provided. 3 shows a structure in which a heat radiation fin 12 made of a material having a high thermal conductivity such as Cu is attached to the back surface 4B of the semiconductor chip 4 exposed from 3 via an insulating adhesive 13 such as silicone rubber. Is.
This can be assembled by mounting the semiconductor device of Embodiment 1 on the wiring boards of various electronic devices and then attaching the radiation fins 12 to the back surface 4B of the semiconductor chip 4.
【００３７】このような実施形態３によれば、さらに低
熱抵抗化を図ることができる他に、実装用電極８が固化
した後に放熱フィン１２を取り付けるので、この放熱フ
ィン１２による重みは実装時に障害にはならない。According to the third embodiment, the heat resistance can be further reduced, and the heat radiation fins 12 are attached after the mounting electrodes 8 are solidified. It doesn't.
【００３８】（実施形態４）図１１は本発明の実施形態
４による半導体装置を示す断面図で、実施形態３の半導
体装置に対して、半導体チップ４と放熱フィン１２との
間に、半導体チップ４に対する熱的応力を緩和する中間
体１４を介在させた例を示すものである。(Fourth Embodiment) FIG. 11 is a cross-sectional view showing a semiconductor device according to a fourth embodiment of the present invention, which is different from the semiconductor device of the third embodiment in that a semiconductor chip is provided between the semiconductor chip 4 and the radiation fin 12. 4 shows an example in which an intermediate body 14 that relaxes the thermal stress on 4 is interposed.
【００３９】この中間体１４としては、半導体チップ４
を構成しているＳｉ（熱膨張率：約２．６×１／１
０6）と放熱フィン１２を構成しているＣｕ（熱膨張
率：約１６．５×１／１０6）との中間の線膨張率を有
する、例えばＭｏ（熱膨張率：約３．７〜５．３×１／
１０6）を用いて構成することができる。As the intermediate body 14, the semiconductor chip 4 is used.
Constituting Si (coefficient of thermal expansion: about 2.6 × 1/1
0 6 ) and Cu (coefficient of thermal expansion: about 16.5 × 1/10 6 ) forming the radiation fin 12, for example Mo (coefficient of thermal expansion: about 3.7 to 5.3 × 1 /
10 6 ) can be used.
【００４０】このような実施形態４によれば、実施形態
３と同様な効果が得られる他に、熱により温度が広範囲
に変化しても、中間体１４の存在により半導体チップ４
に加わる熱的応力を緩和できるという効果が得られる。According to the fourth embodiment, in addition to the same effect as the third embodiment, even if the temperature changes over a wide range due to heat, the presence of the intermediate 14 causes the semiconductor chip 4 to be present.
The effect that the thermal stress applied to the can be relaxed is obtained.
【００４１】以上、本発明者によってなされた発明を、
前記実施形態に基づき具体的に説明したが、本発明は、
前記実施形態に限定されるものではなく、その要旨を逸
脱しない範囲において種々変更可能であることは勿論で
ある。As described above, the inventions made by the present inventor are
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above embodiment, and various changes can be made without departing from the scope of the invention.
【００４２】例えば、前記実施形態で説明したワイヤボ
ンディングは、特定のボンディング法に限らずに、一般
に行われているネイルヘッドボンディング法、ウエッジ
ボンディング法などの中から任意のボンディング法を選
んで行うことができる。For example, the wire bonding described in the above embodiment is not limited to a specific bonding method, but an arbitrary bonding method may be selected from commonly used nail head bonding methods, wedge bonding methods and the like. You can
【００４３】また、放熱フィンを取り付ける構造は、実
装用電極としてピン状電極を用いるパッケージ構造に限
らず、ボール状電極を用いるＢＧＡパッケージ構造に対
しても同様に適用することができる。Further, the structure for attaching the radiation fin is not limited to the package structure using the pin-shaped electrode as the mounting electrode, but can be similarly applied to the BGA package structure using the ball-shaped electrode.
【００４４】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野であるＬＳＩ
に適用した場合について説明したが、それに限定される
ものではない。本発明は、少なくとも回路素子の低熱抵
抗化を図ることを条件とするものには適用できるIn the above description, the invention which was mainly made by the present inventor is the field of application which is the background of the invention.
Has been described, but the present invention is not limited to this. INDUSTRIAL APPLICABILITY The present invention can be applied at least to the condition that the thermal resistance of the circuit element is reduced.
【００４５】[0045]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記の通りである。The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００４６】（１）ベース基板のキャビティの中央部に
貫通孔を設けてこの貫通孔から半導体チップの裏面を露
出させ、キャビティ内に半導体チップを封止する樹脂を
充填しているので、半導体チップで発生した熱をこの裏
面から放熱できるため、キャビティダウン方式のＬＳＩ
を組み立てる場合、コストアップを伴うことなくパッケ
ージの低熱抵抗化を図ることが可能となる。(1) Since the through hole is provided in the center of the cavity of the base substrate, the back surface of the semiconductor chip is exposed from this through hole, and the resin for sealing the semiconductor chip is filled in the cavity, the semiconductor chip Because the heat generated at the back can be radiated from this back side, the cavity down type LSI
In the case of assembling, it is possible to reduce the thermal resistance of the package without increasing the cost.
【００４７】（２）吸着手段によって半導体チップ４を
仮止めした状態でワイヤボンディング及び樹脂充填を行
った後に吸着手段を除去するので、簡単な方法で半導体
チップの裏面を露出させた半導体装置を製造することが
できる。(2) Since the suction means is removed after the wire bonding and the resin filling are performed while the semiconductor chip 4 is temporarily fixed by the suction means, the semiconductor device in which the back surface of the semiconductor chip is exposed is manufactured by a simple method. can do.
【図１】本発明の実施形態１による半導体装置を示す平
面図である。FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.
【図２】図１のＡ−Ａ断面図である。FIG. 2 is a sectional view taken along line AA of FIG.
【図３】本発明の実施形態１による半導体装置の製造方
法の一工程を示す断面図である。FIG. 3 is a cross-sectional view showing a step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図４】図３の底面から見た平面図である。FIG. 4 is a plan view seen from the bottom surface of FIG.
【図５】本発明の実施形態１による半導体装置の製造方
法の他の工程を示す断面図である。FIG. 5 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図６】本発明の実施形態１による半導体装置の製造方
法のその他の工程を示す断面図である。FIG. 6 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図７】本発明の実施形態１による半導体装置の製造方
法のその他の工程を示す断面図である。FIG. 7 is a sectional view showing another step of the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
【図８】本発明の実施形態１による半導体装置の製造方
法で用いられる他の吸着手段を示す断面図である。FIG. 8 is a sectional view showing another suction means used in the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
【図９】本発明の実施形態２による半導体装置を示す断
面図である。FIG. 9 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.
【図１０】本発明の実施形態３による半導体装置を示す
断面図である。FIG. 10 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.
【図１１】本発明の実施形態４による半導体装置を示す
断面図である。FIG. 11 is a sectional view showing a semiconductor device according to Embodiment 4 of the present invention.
１…キャビティ、２…ベース基板、３…貫通孔、４…半
導体チップ、４Ａ…半導体チップの表面、４Ｂ…半導体
チップの裏面、５…半導体チップの電極、６…ベース基
板の導電層、７…ボンディングワイヤ、８…実装用電
極、９…樹脂、１０…耐熱性テープ、１１…真空吸着治
具、１２…放熱フィン、１３…絶縁性接着剤、１４…中
間体。DESCRIPTION OF SYMBOLS 1 ... Cavity, 2 ... Base substrate, 3 ... Through hole, 4 ... Semiconductor chip, 4A ... Semiconductor chip front surface, 4B ... Semiconductor chip back surface, 5 ... Semiconductor chip electrode, 6 ... Base substrate conductive layer, 7 ... Bonding wire, 8 ... Mounting electrode, 9 ... Resin, 10 ... Heat resistant tape, 11 ... Vacuum suction jig, 12 ... Radiating fin, 13 ... Insulating adhesive, 14 ... Intermediate.
Claims (6)
前記キャビティ内に半導体チップをフェースダウンボン
ディングするとともに、前記半導体チップの表面の電極
と前記ベース基板の導電層との間にワイヤをボンディン
グし、前記ベース基板の底面に前記導電層と導通する実
装用電極を配置した半導体装置であって、前記キャビテ
ィの中央部に貫通孔を設けてこの貫通孔から半導体チッ
プの裏面を露出させ、前記キャビティ内に半導体チップ
を封止する樹脂を充填したことを特徴とする半導体装
置。1. A semiconductor chip is face-down bonded into the cavity using a base substrate having a cavity, and a wire is bonded between an electrode on the surface of the semiconductor chip and a conductive layer of the base substrate. A semiconductor device in which a mounting electrode electrically connected to the conductive layer is disposed on a bottom surface of a base substrate, a through hole is provided in a central portion of the cavity, and a back surface of a semiconductor chip is exposed from the through hole, A semiconductor device characterized by being filled with a resin for sealing a semiconductor chip.
付けたことを特徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein a heat radiator is attached to the back surface of the semiconductor chip.
ボール状電極からなることを特徴とする請求項１または
２に記載の半導体装置。3. The semiconductor device according to claim 1, wherein the mounting electrode is a pin-shaped electrode or a ball-shaped electrode.
設けたベース基板を用意して、このベース基板の上面に
前記貫通孔を覆うように吸着手段を設ける工程と、この
吸着手段によって半導体チップをこの裏面から吸着して
前記キャビティ内に仮止めする工程と、前記半導体チッ
プの表面の電極と前記ベース基板の導電層との間にワイ
ヤをボンディングする工程と、前記ベース基板の底面側
からキャビティ内に樹脂を充填する工程と、前記吸着手
段を除去する工程とを含むことを特徴とする半導体装置
の製造方法。4. A step of preparing a base substrate having a cavity and having a through hole in the center thereof, and providing a suction means on the upper surface of the base substrate so as to cover the through hole, and a semiconductor by the suction means. From the bottom surface side of the base substrate, the step of adsorbing the chip from this back surface and temporarily fixing it in the cavity, the step of bonding a wire between the electrode on the surface of the semiconductor chip and the conductive layer of the base substrate, A method of manufacturing a semiconductor device, comprising: a step of filling a resin into a cavity; and a step of removing the suction means.
いることを特徴とする請求項４に記載の半導体装置の製
造方法。5. The method of manufacturing a semiconductor device according to claim 4, wherein a heat-resistant tape is used as the suction means.
いることを特徴とする請求項４に記載の半導体装置の製
造方法。6. The method of manufacturing a semiconductor device according to claim 4, wherein a vacuum suction jig is used as the suction means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7306991A JPH09148496A (en) | 1995-11-27 | 1995-11-27 | Semiconductor device and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7306991A JPH09148496A (en) | 1995-11-27 | 1995-11-27 | Semiconductor device and manufacturing method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09148496A true JPH09148496A (en) | 1997-06-06 |
Family
ID=17963706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7306991A Pending JPH09148496A (en) | 1995-11-27 | 1995-11-27 | Semiconductor device and manufacturing method therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09148496A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008159955A (en) * | 2006-12-26 | 2008-07-10 | Shinko Electric Ind Co Ltd | Substrate incorporating electronic component |
-
1995
- 1995-11-27 JP JP7306991A patent/JPH09148496A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008159955A (en) * | 2006-12-26 | 2008-07-10 | Shinko Electric Ind Co Ltd | Substrate incorporating electronic component |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2548350B2 (en) | Heat dissipation interconnect tape used for tape self-bonding | |
| US4620215A (en) | Integrated circuit packaging systems with double surface heat dissipation | |
| JPH0964099A (en) | Semiconductor device and its mounting structure | |
| JPH07254668A (en) | Semiconductor package for high heat dissipation | |
| JPH0878574A (en) | Semiconductor device and manufacturing method thereof | |
| TW200834768A (en) | Low profile ball grid array (BGA) package with exposed die and method of making same | |
| US6828676B2 (en) | Semiconductor device manufacturing method, semiconductor device, and semiconductor device unit | |
| JP2725448B2 (en) | Semiconductor device | |
| JP3421137B2 (en) | Bare chip mounting structure and heat sink | |
| JP3732051B2 (en) | Automotive control unit | |
| JPH08264688A (en) | Ceramic package for semiconductor | |
| US6963129B1 (en) | Multi-chip package having a contiguous heat spreader assembly | |
| JPH09148496A (en) | Semiconductor device and manufacturing method therefor | |
| JP3894749B2 (en) | Semiconductor device | |
| JPH1126634A (en) | Semiconductor device | |
| JPH0279451A (en) | Semiconductor device, its cooling and manufacturing methods | |
| JPH11163229A (en) | Semiconductor device and manufacture thereof | |
| JPH0878616A (en) | Multi-chip module | |
| JPH08255868A (en) | Semiconductor device and manufacture thereof | |
| JP3058142B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3032124U (en) | High density bonding pad array integrated circuit package with middle layer | |
| JP2504465B2 (en) | Semiconductor device | |
| JPH08139267A (en) | Multichip module | |
| JPH1027866A (en) | Semiconductor integrated circuit device and manufacture thereof | |
| JPH0797616B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091027 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20091027 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101027 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111027 Year of fee payment: 11 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111027 Year of fee payment: 11 |