JPH09145789A - Microprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily test entire connection and at the same time relieve the load of hardware and the load for creating test data when a register used inside a user I/O block need neither read nor write data to or from an MPU. SOLUTION: In a microprocessor system, a scan control part 14 serially transfers data from registers 5 and 6 to a scan register 13 exclusively for testing by scanning when an MPU 2 instructs the registers 5 and 6 exclusively to output data and serially transfers data from the scan register 13 exclusively for testing to the registers 7 and 8 by scanning when the MPU 2 instructs the registers 7 and 8 exclusively for reading to write data.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an ASIC microcomputer L.
The present invention relates to a microprocessor system having a scan test function used for SI.

[0002]

2. Description of the Related Art Generally, a microprocessor system is a microprocessor (hereinafter abbreviated as MPU).
And I / O (Input / Output) block,
Data transfer between the MPU and the I / O block is performed via an internal data bus. And recently, we have developed a new user-specific I / O block,
By connecting the I / O block to an existing MPU, a user-specific microprocessor system LSI, that is, A
It is possible to develop SIC (Application Specific Integrated Circuit) microcomputers.

FIG. 12 shows an ASIC according to the prior art.
A basic 16-bit microprocessor system configuration realized by a microcomputer is shown and described. In FIG. 12, a control signal used for data transfer from the MPU 102 is once received by the I / O decoder 101, and the user I / O
Creating the data transfer signal for block 104. More specifically, the control signal includes a signal RD for instructing I / O data read, a signal WR for instructing I / O data write,
I / O chip select signal CS, address signals A0-A
Consists of ten. The function of generating this data transfer signal can also be included inside the user I / O block 104. The data bus I / F 103 is used to output the internal register of the user I / O block 104 to the internal data bus 110. However, if the load of the data bus is small, The internal register output can also be directly connected.

In order to clarify the existence of a problem described later, FIG. 12 shows a case where the internal register of the user I / O block 104 transfers data to and from the MPU 102 only in one direction of reading or writing. There is.

In the development of such an ASIC microcomputer, a verification in which the entire ASIC microcomputer including the MPU 102 and the user I / O block 104 is completely operated on a computer requires a great deal to create test data and verify by the computer. I need time. When such system verification is required, it is performed using an in-circuit emulator that causes the MPU 102 to operate in a pseudo manner. AS
In the IC microcomputer, design verification is performed for each MPU 102 and user I / O block 104. In the ASIC microcomputer as a whole, complete verification including the operation of the user I / O block 104 cannot be performed in consideration of the time.
The verification of the connection operation between the MPU 102 and the user I / O block 104 is mainly performed as the verification of the entire C microcomputer.

Further, FIG. 13 shows a system configuration diagram when a test is taken into consideration in the ASIC microcomputer basic system of FIG. This system simply MPs the registers 125-128 inside the user I / O block 124.
The configuration is such that writing and reading can be performed from U122.

On the other hand, Japanese Laid-Open Patent Publication No. 62-233780 is characterized in that test data input time is shortened by sequentially and independently performing a process of executing a test on each functional block. A technique related to "large-scale integrated circuit and test method thereof" is disclosed. That is, this technique aims at facilitating the test for each functional block in the block division test using the scan register.

Further, in Japanese Patent Application Laid-Open No. 2-38978, a hardware quantity is reduced by being composed of an input / output shift register and a shift register latch for storing a microprogram for controlling input / output of these data. A technique relating to a "scan path circuit" is disclosed. That is, this technique is to replace the input or output register connected to the data bus with setting the test data in the test input register and outputting the test result from the test output register. It is effective for a certain LSI.

Further, in Japanese Patent Laid-Open No. 4-55778,
The present invention relates to a "test method for a semiconductor device" characterized in that a test time is shortened by testing a functional block using a scan test method according to a program instruction executed by a processor included in the same system as the functional block. The technology is disclosed. That is, according to this technique, the block under test on the same chip is tested by the instruction of the built-in processor, and the test data and the test result are transferred and controlled in parallel via the data bus of the processor.

[0010]

However, in the development of the ASIC microcomputer as described above, the user I
The register used in the I / O block 104 is MPU1.
There is no problem if the data transfer with 02 requires both writing and reading, but it is not always necessary. In addition, the MPU 102 and user I /
In the verification of the connection operation with the O block 104, the MPU 10
2 is the first verification item to confirm that data transfer between the internal register of the user I / O block 104 and the user I / O block 104 is possible in the actual operation.
If the data transfer with the U102 is only writing or reading, it will be a big obstacle.

For example, when the data transfer between the internal register and the MPU 102 is only writing, various data are set in the internal register using the MPU 102, and the user I
This is because the / O block 104 is operated, but it takes a considerable time to create and verify such test data. If data transfer between the internal register and the MPU 102 is only read, the user I / O block 104 is operated to set various data in the internal register and then the MPU 102 reads the data. This is because it takes a considerable amount of time to create and verify such test data.

Further, in the above-mentioned system configuration of FIG. 13, the internal register is 16 bits, but one for each write / read-only register.
Six signal lines are required, and the data bus IF 123 becomes large. Furthermore, the read-only registers 127 and 12
8 requires not only the selection circuit 133 for selecting the data write path from the user logic 129 and the write path from the internal data bus 130, but also the test mode designation input terminal 134 for this selection.
Will also be required. Also, this test mode specification input terminal 1
34 is the easiest to use as an LSI external terminal,
This increases the number of LSI external terminals.

On the other hand, the technique disclosed in Japanese Patent Laid-Open No. 62-233780 does not show the concept of the scan test using the MCU, and further, the data bus and the scan register are not connected. . Further, in the technique disclosed in Japanese Patent Laid-Open No. 2-38978, serial data transfer is performed from outside the LSI, and serial data transfer between an input or output register connected to a data bus and a scan register for testing is performed. No concept is shown. Further, in the technique disclosed in Japanese Patent Application Laid-Open No. 4-55778, since the scan instruction is prepared in the built-in processor, the processor is limited. Further, the F / F to which the scan data is transferred is not connected to the data bus.

As described above, in each of the above-mentioned conventional techniques, M
When there is a read instruction from the MPU to a register that is accessed only by the PU, or when a write instruction is issued from the MPU to a register that is accessed only from the MPU, It was not possible to perform quick and accurate data transfer via the data bus.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a register used inside a user I / O block in designing a user I / O block necessary for developing an ASIC microcomputer. However, when the data transfer with the MPU does not require both writing and reading, it is to facilitate the connection test of the entire ASIC microcomputer and reduce the load of hardware and test data creation.

[0016]

In order to achieve the above object, a microprocessor system having a scan test function according to a first aspect of the present invention is mapped in an address space of a microprocessor, In a microprocessor system having a register for performing data transfer with a microprocessor via a data bus to which the control signal is connected, access from the microprocessor via the data bus is read and write. It has a scan register dedicated to the test and a scan-operable register whose access from the microprocessor via the data bus is either read or write, and the register from the microprocessor via the data bus. When a microprocessor issues a read instruction to a scan-enabled register that is write-only, the microprocessor scans the test-only scan register from the scan-enabled register that is write-only. When the microprocessor instructs to write to the register that can perform scan operation, the data is serially transferred with, and the microprocessor can access only read through the data bus. It is characterized in that data is serially transferred by a scan operation to a scan-operable register which can be accessed only by reading from the microprocessor via the data bus.

The microprocessor system according to the second aspect comprises a microprocessor for writing data to a register and reading data from the register via a data bus, and a microprocessor for performing data write on the register via the data bus. Scan-only read-only register that can be accessed only for reading, scan-only write-only register that can be accessed only by the microprocessor for writing through the data bus, and micro-processor that can be accessed through the data bus. When the microprocessor issues a read instruction to the test-dedicated test register that can perform scan operation and the access from the processor is read and write, the test-dedicated register is written from the write-only register. Data is serially transferred to the read data register by the scan operation, and when the microprocessor instructs writing to the read only register, the test operation register is serially transferred to the read only register by the scan operation. And a scan control means for controlling.

That is, in the present microprocessor system, the registers are composed of scannable registers, and M
At least one test scan register is provided that allows data transfer with the PU in both directions of writing and reading with respect to the MPU. When the MPU gives an instruction to read to a register that is write-only, the data of the write-only register passes through the scan data path between the write-only register and the test scan register. Transferred to register. Further, when the MPU issues a write instruction to a register that is read-only for access from the MPU, the data in the test scan register is read-only through the scan data path between the test scan register and the read-only register. Transferred to register.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment in which a microprocessor system incorporating a scan test function of the present invention is applied to an ASIC microcomputer.

FIG. 1 shows an embodiment corresponding to the prior art shown in FIG. 12 and has two sets of write and read only registers. However, here, the data signals of the user logic, the write-only register, and the read-only register shown in FIG. 12 are not shown.

In FIG. 1, the MPU previously shown in FIG.
The same MPU2 as the MPU of the user I / O block 4
The U synchronization clock signal CLK and the reset signal RST synchronized with the rising edge of CLK are supplied to the scan control block 14 which controls the scan operation. I / O decoder 1
Are pulse signals WR1 to WR4, R for one CLK cycle in synchronization with the falling edge of CLK in accordance with read / write requests from the MPU2 to the scan registers 5 to 8 and 13.
D1 to RD4, TWR, and TRD are generated.

The I / O decoder 1 supplies signals RD1, RD2, WR3 and WR4 instructing the scan operation to the scan control block 14 controlling the scan operation, and a signal TRD instructing the read operation of the test scan register 13. Is supplied to the data bus IF3. The I / O decoder 1 supplies the signal TWR instructing the write operation to the write clock input of the test scan register 13 and outputs the signals WR1 and WR2 instructing the write operation of the write-only scan registers 5 and 6 respectively to the write-only signal. It is supplied to the write clock input of the scan registers 5 and 6.

Further, the I / O decoder 1 uses the signal RD for instructing the read operation of the read-only registers 7 and 8.
3, RD4 is supplied to the data bus IF3. The data bus IF3 is a read instruction signal R from the I / O decoder 1.
According to D3, RD4 and TRD, the output signals of the read-only registers 7 and 8 and the test scan register 13 are output to the internal data bus 10, respectively. The width of the scan register 13 and the internal data bus 10 is 16 bits in this embodiment.

FIG. 2 shows a detailed circuit configuration of the read-only scan register 7 and the scan clock control circuit 16 for explanation. This read-only scan register 7
Are composed of 16 scan flip-flops in this embodiment. The scan data may be transferred from the upper side to the lower side of the data, or from the lower side to the upper side of the data, but in this embodiment, the data is shifted from the upper side to the lower side. It has a circuit.

In FIG. 2, the scan flip-flop 21 corresponds to the high-order bit (15th bit), and the scan flip-flop 23 corresponds to the low-order bit (0th bit). The output terminal SO of the upper bit and the input terminal SI of the lower bit are connected so as to be shifted to the bit. The scan input terminal SI of the scan flip-flop 21 is connected to the scan output terminal SO of the test scan register as shown in FIG. 1, and the contents of the test scan register are scanned in by the scan operation.

Although the scan output terminal SO of the scan flip-flop 23 is connected to the scan output terminal 18 in FIG. 1 described above, it may be open. The scan clock control block 24 has a 2-input NA.
The ND gates 25 and 26 are provided to scan the scan clock signal ACL from the scan control block 14 in FIG.
K, BCLK, and clock control signal SCENR3 are supplied. Then, the scan flip-flops 21 to 2
The three scan clock input terminals A and B are connected to the output terminals of the two-input NAND gates 25 and 26, respectively.

The normal input terminal D and the clock input terminal CP of the scan flip-flops 21 to 23 are connected to the user logic 28 which is not shown in FIG. 1, and the normal output terminal Q is connected to the data bus IF27.
The output terminals Q of the scan flip-flops 21 to 23 correspond to the upper to lower parts of the internal data bus 10 in FIG. 1, that is, D15 to D0. The description of the read-only scan register 8 and the scan clock control circuit 16 in FIG. 1 is the same as that of FIG. 2 except that the scan clock control signal is changed to SCENR4, and thus detailed description thereof is omitted here.

FIG. 3 shows a detailed circuit configuration of the write-only scan register 5 and the scan clock control circuit 16 for description. This write-only scan register 5
Is composed of 16 scan flip-flops. Then, as in the description of FIG. 2, the direction of the data to be transferred as the scan data may be from the upper side to the lower side of the data or from the lower side to the upper side, but in this embodiment, the data is transferred. It is a circuit that shifts from the upper side to the lower side.

In FIG. 3, the scan flip-flop 31 corresponds to the upper bit (15th bit), and the scan flip-flop 33 corresponds to the lower bit (0th bit).
The output terminal SO of the upper bit and the input terminal SI of the lower bit are connected so that the data is shifted from the upper bit to the lower bit during the scan operation. The scan input terminal SI of the scan flip-flop 31 is connected to the scan input terminal 17 in FIG. 1, but is connected to GND or VDD corresponding to “0” or “1”.
Or may be connected to the SO of the scan flip block 33.

As shown in FIG. 1, the scan output terminal SO of the scan flip-flop 33 is connected to the input terminal of the scan path selection circuit 15, and the contents of the scan flip-flops 31 to 33 are scanned for a test by the scan operation. Scan input to the register. The scan clock control block 34 includes 2-input NAND gates 35, 3
The scan control block 14 of FIG.
Are supplied with the scan clock signals ACLK and BCLK and the clock control signal SCENW1.

The scan flip-flops 31-31
33 scan clock input terminals A and B are 2
It is connected to the output terminals of the input NANDs 35 and 36. Normal input terminal D of the scan flip-flops 31 to 33
Are connected to the internal data bus 38, and input data from upper to lower, that is, D15 to D0, respectively. Clock input terminals C of the scan flip-flops 31 to 33
The clock pulse signal WR1 generated by the I / O decoder 1 in FIG. 1 is input to P.

Further, the scan flip-flops 31-31
The output terminal Q of 33 is supplied to the user logic 37 not shown in FIG. The description of the write-only scan register 6 and the scan clock control circuit 16 in FIG. 1 is the same as that of FIG. 3 except that the scan clock control signal is changed to SCENW2 and the clock pulse from the I / O decoder is changed to WR2. Description is omitted.

FIG. 4 shows the test scan register 1 described above.
3 and the detailed circuit configurations of the scan clock control circuit 16 and the scan path selection circuit 15 will be described. The test scan register 13 is composed of 16 scan flip-flops. Similar to the description of FIG. 2 and FIG. 3, the direction of the data to be transferred as the scan data may be from the upper side to the lower side of the data, or from the lower side to the upper side, but in this embodiment, , A circuit for shifting data from the upper side to the lower side.

In FIG. 4, the scan flip-flop 41 corresponds to the upper bit (15th bit), and the scan flip 43 corresponds to the lower bit (0th bit). The upper bit output terminal SO and the lower bit input terminal SI are connected so as to be shifted to.

The scan input terminal SI of the scan flip-flop 41 is connected to the output terminal of the scan path selection circuit 44, and the scan output terminal SO (in FIG. 3) of the scan flip-flop of the least significant bit of the write-only scan register 5 in FIG. The output terminal SO of the scan flip-flop 33) or the scan output terminal SO of the scan flip-flop of the least significant bit of the write-only scan register 6 in FIG. 1 is selected and input.

As shown in FIG. 1, the scan output terminal SO of the scan flip-flop 43 has the scan input terminal SI (the input of the flip-flop 21 in FIG. 2) of the scan flip-flop of the most significant bit of the read-only scan register 7. Terminal SI) and the scan input terminal SI of the scan flip-flop of the most significant bit of the read-only scan register 8 in FIG. The scan clock control block 45 has a 2-input NA.
The ND gates 46 and 47 are provided to scan the scan clock signals ACLK and BC from the scan control block 14 of FIG.
LK and the clock control signal SCEN are supplied. The scan clock input terminals A and B of the scan flip-flops 41 to 43 are connected to the outputs of the 2-input NAND gates 46 and 47, respectively.

The normal input terminals D of the scan flip-flops 41 to 43 are connected to the internal data bus 49, and input the data from the higher order to the lower order, that is, D15 to D0, respectively. Also, the scan flip-flops 41 to 4
The clock pulse signal TWR generated by the I / O decoder 1 in FIG. Further, the output terminals Q of the scan flip-flops 41 to 43 are supplied to the data bus IF3 (reference numeral 48 in FIG. 4) in FIG.

A detailed circuit configuration of the scan control block 14 is shown in FIG. 5 and will be described. The scan control block is for generating various control signals for the scan operation of FIGS. 8 and 9 which will be described later, and includes a write-only scan register 5 state flip-flop 51, a write-only scan register 6 state flip-flop 52, and a read-only. The scan register 7 state flip-flop 53, the read-only scan register 8 state flip-flop 54, a 4-bit binary counter 55, a two-phase clock generation circuit 56, and various gate circuits.

Scan clock signals ACLK, BCLK
Is the output signal SCANC of the 4-input OR gate 57 generated from the MPU synchronization clock CLK supplied from the MPU 2 in FIG. 1 and the control signal from the I / O decoder 1.
Is generated by the two-phase clock generation circuit 56.
This two-phase clock generation circuit, as shown in FIG.
2-input NAND gate 81 and 2-input NOR gate 82,
The signal SCA is composed of 83 and a plurality of inverters.
Two-phase clock signal ACL based on NC and CLK
Get K and BCLK. That is, as shown in the operation timing chart of FIG. 11, one pulse is added to the scan clock signal ACLK at the phase of “1” of the clock signal CLK based on the clock signal CLK.
0 pulse is generated in the scan clock signal BCLK in the phase of "0", and both are designed to be "0" when the output signal SCANC is "0".

The 4-bit binary counter 55 is an MPU.
Counts at the falling edge of the synchronization clock signal CLK,
In the 15 states, CO is made to output "1". Then, the reset signal RST from the MPU 2 and the scan operation are completed (operation S of the test scan register is enabled).
It is reset when CEN is inverted. Since the state flip-flops 51 to 54 for scan registers have exactly the same circuit configuration, the state flip-flop 51 for write-only scan register 5 will be described.

The scan register status flip-flop 51 is reset by the reset signal RST from the MPU 2 and a reset D flip-flop 64 which changes its status at the fall of the MPU synchronization clock signal CLK of the user I / O block, A 2-input NOR gate 63 for resetting the D flip-flop 64 with reset by CO of the 4-bit binary counter 55, and a scan operation instruction signal RD1 from the I / O decoder 31 in FIG.
D flip-flop 6 with reset for a predetermined period
It is composed of a 2-input NOR gate 62 for holding the state of 4, and an inverter 61 for outputting a scan path selection signal SCSELW1.

The reset D flip-flop 64
Output Q corresponds to the scan clock operation enable signal SCENW1 of the write-only scan register. 4
The input OR gate 57 has a scan clock signal ACL.
The operation enable signal SCANC of K and BCLK is output, and the 4-input OR gate 58 outputs the scan clock operation enable signal SCEN of the test scan register.

The operation of the microprocessor system with a built-in scan test function according to this embodiment will be described below with reference to the timing charts of FIGS.
First, referring to the timing chart of FIG. 6, write-only registers 5 and 6 and read-only registers 7 and 8 and M
Data transfer with PU2 will be described.

In FIG. 6, when the reset signal RST from the MPU 2 becomes "1", the flag inside the user logic 9 in the user I / O block 4 is reset, the reset signal RST becomes "0", and the ASIC microcomputer The system starts working. Further, in order to operate the user I / O block 4 in synchronization with the MPU 2, the MPU 2 outputs the clock signal CLK to the user I / O block 4.

The access of the scan register from the MPU 2 changes 1/4 cycle before the rising edge of the clock signal CLK, and the address signals A0 to A10 which hold the state for two clock cycles or more, the chip select CS and the clock signal CLK. Of the address latch enable ALE that changes 1/4 cycle before the rising edge of CLK and becomes "1" for 1/2 clock cycle, and the read instruction signal R that becomes "0" for 1 cycle in synchronization with the falling edge of the clock signal CLK.
D and the write instruction signal WR.

In the operation of FIG. 6, after resetting, the read-only scan register 7 is read, the write-only scan register 5 is written, the read-only scan register 8 is read, and the write-only scan register 6 is written.

In the reading of the read-only scan register 7, the MPU 2 outputs the address REG3 and the chip enable CS in which the read-only scan register 7 is mapped in the address space of the MPU 2 and outputs the read after the address latch enable ALE falls. The instruction signal RD becomes "0" in synchronization with the fall of the clock signal CLK. The signals from these MPU2 are I
The / O decoder 1 processes and outputs a signal RD3 having a polarity different from that of RD at the timing of the read instruction signal RD to the data bus IF3. Upon receiving this signal RD3, the data bus IF3 causes the output data of the read-only scan register 7 to be output to the internal data bus 10 (D0 to D15).
The MPU 2 reads the data of the read-only scan register 7 output to the internal data bus 10 (D0 to D15), and the read-only scan register 7 of the MPU 2 is read.
Read cycle ends.

In the writing of the write-only scan register 5, the MPU 2 outputs the address (REG1) in which the write-only scan register 5 is mapped in the address space of the MPU 2 and the chip enable CS, and after the address latch enable ALE falls. The write instruction signal WR becomes "0" in synchronization with the fall of the clock signal CLK. The I / O decoder 1 processes the signals from the MPU 2 and supplies the signal WR1 to the clock signal end of the write-only scan register 5 in synchronization with the timing of the write instruction signal WR. Since the write data is output from the MPU 2 to the internal data bus 10 (D0 to D15) at the timing of “0” of the write instruction signal WR, the write-only scan register 5 is
The data from the MPU 2 can be read at the rising timing of the signal WR 1, and the write cycle to the write-only scan register 5 ends.

The read cycle of the read-only scan register 8 is the same in function as the read cycle of the read-only scan register 7, and the address RE
Instead of G3, the read-only 3 scan register 8 has an address R mapped in the address space of the MPU 2.
EG4 is output from MPU2, processed by I / O decoder 1, outputs signal RD4 instead of signal RD3 to data bus IF3, receives signal RD4, and receives data bus IF
3 causes the output data of the read-only scan register 8 to be output to the internal data bus 10 (D0 to D15). This is performed by the MPU 2 reading this data.

The write cycle of the write-only scan register 6 has the same function as the write cycle of the write-only scan register 5, and the address RE
Instead of G1, the write-only scan register 6 is M
Address RE mapped in the address space of PU2
G2 is output from the MPU 2, processed by the I / O decoder 1, and the clock signal WR2 of the write-only scan register 6 is supplied to the clock end of the write-only scan register 6 at the timing of the write instruction signal WR instead of the signal WR1. , MPU2 to internal data bus 10 (D0
D15) to the write-only scan register 6 reading the write data.

Next, the basic read / write operation of the test scan register 13 will be described with reference to the time chart of FIG. The test scan register 13 is
The write-only scan registers 5 and 6 and the read-only scan registers 7 and 8 are mapped in a different address space of the MPU 2. The address at the time of reading from the MPU 2 and the address at the time of writing may be different. Since the test scan register 13 can be accessed by the MPU 2 for both reading and writing, FIG.
The read / write cycle described above can be performed. The reading of the destination scan register 13 from the MPU 2 is exactly the same as the reading control of the read-only scan register 7 except that the MPU 2 outputs the address TREG.

In the I / O decoder 1, the data bus IF3
Signal T for instructing a read operation instead of signal RD3
Output RD, receive signal TRD, and receive data bus IF3
Causes the output data of the test scan register 13 to be output to the internal data bus 10 (DO to D15).
U2 reads this data. Also, MPU
Writing from 2 to the test scan register 13
The MPU 2 only outputs the address TREG, and the rest is exactly the same as the write control of the write-only scan register 5.

In the I / O decoder 1, instead of the signal WR1, the clock signal T of the test scan register 13 is used.
The WR is supplied to the clock terminal of the test scan register 13 so that the internal data bus 10 (D0 to D1) is supplied from the MPU2.
This is performed by reading the write data output to 5) by the test scan register 13.

In the description of FIGS. 6 and 7, the access operations for reading and writing the registers mapped from the MPU2 to the address space of the MPU2 are the same as the MPU2.
Output from the register data output enable signal R to be output to the internal data bus from the I / O decoder 1 to the data bus IF3 when read.
D3, RD4, TRD are output at the timing of RD, and the MPU2 reads them, so that I / O can be performed at the time of writing.
The decoder 1 outputs the signals WR1 and W at the timing of the signal WR.
It has been shown that R2 and TWR are supplied to the clock input of the write target register, and the data output from the MPU 2 at that time is read by each target register. M
From the perspective of the PU2, it is not known that these registers are write-only or read-only, so the software of the MPU2 created by the ASIC microcomputer system designer does not read or write the write-only registers. The present invention provides a scan test function that operates with these unused software.

Next, the scan data transfer operation from the write-only scan register 5 to the test scan register 13 will be described with reference to the time chart of FIG. M
When a read request is issued from the PU2 to the write-only scan register 5, the MPU2 outputs the address REG1 and the chip enable CS mapped by the write-only scan register 5 in the address space of the MPU2, and after lowering the address latch enable ALE, Signal RD
Is set to "0" in synchronization with the falling edge of the clock signal CLK. If the write-only scan register 5 is readable, then the I / O decoder 1 continues to operate on the data bus IF3.
The output data of the write-only scan register 5 is output to the internal data bus 10 in response to the instruction, but since this data path does not exist, the MPU 2 reads the meaningless hold data previously output to the internal data bus 10.

In FIG. 1 of the present invention, the I / O decoder outputs a signal RD1 having a different polarity at the timing of the signal RD in response to the read instruction signal RD output from the MPU2. The scan control block 14 receives the signal RD1 and transfers the scan data from the write-only 1 scan register 5 to the test scan register 13 in a cycle of 17 cycles of the user I / O synchronous clock signal CLK output from the MPU 2. After the scan data transfer from the write-only scan register 5 to the test scan register 13, the MPU 2 reads the test scan register 13 so that the MPU 2 can read the contents of the write-only scan register 5. Therefore, the software of the MPU 2 discards the first read data of the write-only scan register 5 and uses the data of the test scan register 13.

Further, in FIG. 1, the synchronous clock signal CLK
The scan data transfer is performed in the cycle of 17 cycles, but the scan path selection signal SCSELW1 (SCA
If a high-speed design is performed so that the output of (NC) can be determined within a half cycle of clock signal CLK,
Enable signal SCENW1 (SCEN) to SCSEL
Synchronous clock signal C used as W1 (SCANC)
Scan data transfer is possible in a cycle of 16 cycles of LK. In the scan data transfer operation from the write-only scan register 6 to the test scan register 13, the signal RD1 in FIG. 8 is RD2 and SCSELW1 is SC.
The operation is exactly the same except that SELW2 and SCENW1 are replaced by SCENW2 and REG1 is replaced by REG2. Therefore, detailed description is omitted here.

Next, the scan data transfer operation from the test scan register 13 to the read-only scan register 7 will be described with reference to the time chart of FIG. First, data to be written in the read-only scan register 7 is written in the test scan register 13. This operation is the same as that described in the write operation of the test scan register 13 in FIG. 7, and thus detailed description will be omitted. Then, when a write request is issued from the MPU2 to the read-only scan register 7, the MPU2 outputs the address REG1 and the chip enable CS, which are mapped by the read-only scan register 7 in the address space of the MPU2, and the address latch enable ALE falls. After that, the signal WR is set to "0" in synchronization with the falling edge of the clock signal CLK.

If the read-only scan register 7 is writable, then the I / O decoder 1 generates a write pulse to write the data output from the MPU 2 to the internal data bus 10 to the read-only scan register 7. Yes, but there is no data path, so MPU
For 2, the operation is completely meaningless.

In FIG. 1 of the present invention, the I / O decoder 1 corresponds to the write instruction signal WR output from the MPU 2.
Outputs a synchronous signal WR3 at the timing of the signal WR. The scan control block 14 receives the signal WR3,
The scan data is transferred from the test scan register 13 to the read-only scan register 7 in a cycle of 17 cycles of the user I / O synchronous clock signal CLK output from the MPU 2. Therefore, in the software of MPU2, writing to the test scan register 13
Writing to the read-only scan register 7 forms a set, and writing to the read-only scan register 7 is performed.

Similar to the description of FIG. 8, in FIG. 1, scan data transfer is performed in a cycle of 17 cycles of the synchronous clock signal CLK, but the scan path selection signal S is used.
CSELR3 (SCANC) output is clock signal CL
If a high-speed design is performed so that it can be determined within a half cycle of K, the scan clock enable signal SCENR3
(SCEN) is used as SCSELR3 (SCANC), and scan data transfer is possible in a cycle of 16 cycles of the synchronous clock signal CLK. Further, in the scan data transfer operation from the test scan register 13 to the read-only scan register 8, the signal WR3 in FIG. 9 is WR4, the SCSELR3 is SCSELR4, and the SCENR.
3 is replaced with SCENR4 and REG3 is replaced with REG4, and the operation is exactly the same, and therefore the description thereof is omitted.

Here, the above-mentioned structural features of the present invention are summarized as follows. (1) Registers (read-only register and write-only register) unidirectionally connected to the data bus are composed of scan registers. (2) The test scan register is bidirectionally (read / write) connected to the data bus. (3) The test scan register, the read-only register, and the write-only register are connected by a serial data transfer path (scan path). (4) W (write); scan register for test → read-only register R (read) using serial data transfer path (scan path) instead of parallel data transfer using data bus in normal R / W control of MCU ); Data is transferred from the write-only register to the test scan register.

However, as the control of the MCU, in WR (write), after writing the data in the test scan register, it is necessary to write in the read-only register, and in R (read), the read-only register is read. After that, it is necessary to read the test scan register.

The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention. For example, the scan input terminal SI of the write-only scan register 5 and the write-only scan register 6 is the scan input terminal 1
7 is connected to this scan input terminal 17
If it is not necessary to input scan data from outside or inside the SI, it may be fixed to "0" or "1". When it is desired to retain the contents of the register, it may be connected to the lowest SO.

Also, the scan output terminals SO of the read-only scan register 7 and the read-only scan register 8 are connected to the scan output terminal 18, but LS
If there is no need to output scan data from outside or inside, it may be open.

Further, in FIG. 1, the scan output terminals SO of the read-only scan register 7 and the read-only scan register 8 are individually connected to the scan output terminal 18, but they are combined into one by using the scan path selection circuit 15. You can also put them together. In such a case, the SO selection signals are SCSELR3 and SCSELR4 in FIG.

As described in detail above, according to the present invention, A
In designing the user I / O block required for SIC microcomputer development, when the registers used inside the user I / O block do not require both writing and reading for data transfer with the MPU, the entire ASIC microcomputer is connected. Testing can be done easily.

The only additional hardware is a scan register, a test scan register, a test I / O decoder access signal, and a scan control signal generation circuit. Compared to the method of doing both, it is significantly less independent of the number of bits in the register.

Since the test data can be created from MPU shiftware, it is possible to create test data such as a bit format suitable for a computer such as conversion to serial data required for a conventional scan test. It is no longer necessary, and the verification period can be greatly shortened.

[0070]

According to the present invention, in the design of the user I / O block necessary for developing the ASIC microcomputer, the register used inside the user I / O block is the MPU.
A microprocessor system with a built-in scan test function that simplifies the connection test of the entire ASIC microcomputer and reduces the burden of creating hardware and test data when data transfer with and without the need for both writing and reading Can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment in which a microprocessor system having a scan test function according to the present invention is applied to an ASIC microcomputer system.

FIG. 2 is a block diagram showing a detailed configuration of read-only scan registers 7 and 8 in FIG.

FIG. 3 is a block diagram showing a detailed configuration of write-only scan registers 5 and 6 in FIG.

FIG. 4 is a block diagram showing a detailed configuration of a test scan register 13 of FIG.

5 is a block diagram showing a detailed configuration of a scan control unit 14 in FIG.

FIG. 6 is a timing chart showing a basic read / write operation of read / write dedicated registers 5-8.

FIG. 7 is a timing chart showing a basic read / write operation of the test scan register 13.

FIG. 8 is a timing chart showing a scan operation of write-only scan registers 5 and 6.

FIG. 9 is a timing chart showing a scan operation of read-only scan registers 7 and 8.

10 is a diagram showing a configuration of a two-phase clock generation circuit which constitutes FIG. 1. FIG.

11 is a timing chart showing an operation of the two-phase clock generation circuit of FIG.

FIG. 12 is a diagram showing a basic system configuration in an ASIC microcomputer according to a conventional technique.

FIG. 13 is a diagram showing a microprocessor system configuration according to a conventional technique in consideration of a test.

[Explanation of symbols]

1 ... I / O decoder, 2 ... MPU (microprocessor), 3 ... Data bus IF, 4 ... User I / O block, 5 ... Write-only scan register, 6 ... Write-only scan register, 7 ... Read-only scan register, 8 ... Read-only scan register, 9 ... User logic, 10 ... Internal data bus, 11 ... LSI external input terminal, 12 ... LSI external output terminal, 13 ... Test scan register, 14 ... Scan control block, 15
... scan path selection circuit, 16 ... scan clock control circuit, 17 ... scan input terminal, 18 ... scan output terminal, 21 ... scan flip-flop (15 bit)
Eyes), 22 ... Scan flip-flops (14 bits)
Eye), 23 ... Scan flip-flop (0 bit
Eye), 24 ... Scan clock control block, 25, 2
6 ... 2-input NAND gate, 27 ... Data bus IF, 2
8 ... User logic, 31 ... Scan flip-flop (15 bits), 32 ... Scan flip-flop (14th bit), 33 ... Scan flip-flop (0th bit), 34 ... Scan clock control block, 35, 36 ... 2-input NAND gate, 37 ... User logic, 38 ... Internal data bus, 41 ... Scan flip-flop (15th bit), 42 ... Scan flip-flop (14th bit), 43 ... Scan flip-flop (0 bit), 44 ... Selection circuit, 45 ... Scan clock control Block, 46, 47 ... 2-input NAN
D gate, 48 ... Data bus IF, 49 ... Internal data bus, 51 ... Status flip-flop for write-only scan register 5, 52 ... Write-only scan register 6
State flip-flops, 53 ... Read-only scan register 7 state flip-flops, 54 ... Read-only scan register 8 state flip-flops, 55 ...
4-bit binary counter, 56 ... 2-phase clock generation circuit, 57, 58 ... 4-input OR gate, 61, 65, 6
9, 71 ... Inverter, 62, 63, 66, 67 ... 2-input NOR gate, 64, 68 ... D flip-flop with reset, 70 ... 2-input OR gate, 81 ... 2-input NA
ND gate, 82, 83 ... 2-input NOR gate, 101
... I / O decoder, 102 ... MPU, 103 ... Data bus IF, 104 ... User I / O block, 105 ... Write-only register, 106 ... Write-only register,
107 ... Read-only register, 108 ... Read-only register, 109 ... User logic, 110 ... Internal data bus, 111 ... LSI external input terminal, 112 ... LS
I external output terminal, 121 ... I / O decoder, 122 ... M
PU, 123 ... Data bus IF, 124 ... User I /
O block, 125 ... Write-only register, 126 ...
Write-only register, 127 ... Read-only register, 128 ... Read-only register, 129 ... User logic, 130 ... Internal data bus, 131 ... LSI external input terminal, 132 ... LSI external output terminal, 133 ... Selection circuit, 134 ... Test mode Designated input terminal.

Claims (2)

[Claims] 1. A microprocessor system having a register which is mapped in an address space of the microprocessor and which transfers data to and from the microprocessor via a data bus to which the microprocessor is connected in response to a control signal from the microprocessor. , A scan register dedicated to the test in which the access from the microprocessor via the data bus is read and write, and a scan operation in which the access from the microprocessor via the data bus is either read or write When a microprocessor issues a read instruction to a register that has a large number of registers and is accessible only by the microprocessor via the data bus for writing, the microphone Scan operation is possible when the processor can access only the write operation to perform the scan operation to transfer data serially from the register that can be scanned to the test dedicated scan register, and the microprocessor access via the data bus can only perform the read operation. When there is a write instruction from the microprocessor to such a register, from the test-dedicated scan register to the scan-operable register in which access from the microprocessor via the data bus is only for reading,
A microprocessor system characterized by serially transferring data in a scan operation. 2. A microprocessor that writes data to a register and reads data from a register via a data bus, and a scan operation in which access from the microprocessor via the data bus is read-only. A read-only register, a scan-only write-only register that can be accessed by the microprocessor via the data bus for writing, and a scan-only scan that can be accessed by the microprocessor through the data bus for reading and writing. When the microprocessor issues a read instruction to the operable test-only register and the write-only register, data is serially transferred from the write-only register to the test-only register by a scan operation, and the read-only register is read. Scan control means for controlling to serially transfer data from the test dedicated register to the read only register by a scan operation when the microprocessor issues a write instruction to the output dedicated register. Characteristic microprocessor system.