JP3255139B2 - High-level synthesis system, method and recording medium - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-level synthesis system, a method, and a recording medium storing a program for executing the method, and more particularly to an RTL which combines a plurality of processes while realizing exclusive control of a shared register. (Regist
(Transfer Level) description.

[0002]

2. Description of the Related Art As the scale of semiconductor integrated circuits has increased, the number of circuit design steps has increased. In order to cope with such a situation, in recent years, a process of converting an operation description language describing an operation level of hardware specifications into an RTL description, and further performing a circuit design from the RTL description has been adopted.

[0003] Converting the hardware specifications described at the operation level in the operation description language to the RTL description while maintaining its consistency is called high-level synthesis. A unit that performs a series of operations in hardware specifications described in an operation description language and can proceed in parallel with each other is called a process, and is generally designed by a set of processes. Circuit is configured.

As methods for exchanging data between processes cooperating in a circuit, a method of directly passing signals between processes and a method of passing data by interposing a register or a memory between processes are known. is there. In the former method of passing the direct signal,
Since the process on the signal transmitting side and the process on the receiving side must be completely synchronized, it is very difficult to design a circuit.

On the other hand, the latter method of exchanging data via a register or memory, that is, the method of using a shared register for exchanging data between processes does not require that the processes are completely synchronized. Instead, data exchange is possible with simple control such as data setting, waiting, and reading. For this reason, designing a circuit using a shared register is practical and widely used.

[0006]

However, when data is exchanged using a shared register, when a plurality of processes simultaneously write data to the same shared register, it is determined which process writes the data. There's a problem.

In order to address such a problem, conventionally,
In order to prevent data from being written to the same shared register from multiple processes, related processes can be completely coordinated with each other, or each process can independently determine whether to write the shared register. The method was adopted. However, when implementing exclusive control of the shared register by any of these methods, a heavy burden is imposed on the circuit designer.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art. A circuit description is provided by converting operation descriptions of a plurality of cooperating processes into RTL descriptions and logically designing the RTL descriptions. Provided is a high-level synthesis system and method which can easily perform circuit design realizing exclusive control of a shared register when designing, and a computer-readable recording medium storing a program for executing the method. The purpose is to:

[0009]

In order to achieve the above object, a high-level synthesis system according to a first aspect of the present invention comprises:
A process operation description input means for inputting a process operation description in which the operations of a plurality of processes included in a circuit to be designed are described in a predetermined operation description language; and used for transferring data between the plurality of processes. Priority input means for inputting identification information of the shared register and a priority of a process of writing data to each shared register;
High-level synthesis means for converting a process operation description input from the process operation description input means into a register transfer level description of the process; a process operation description input from the process operation description input means; A shared register control description generating means for generating a description of a register transfer level relating to exclusive control of the shared register among the plurality of processes, based on a process priority of each shared register input from the means; An integrated means for integrating the register transfer level description of the process converted by the synthesizing means and the register transfer level description related to the exclusive control of the shared register generated by the shared register control description generating means.

In the above-described high-level synthesis system, in addition to the operation description of the process, identification information of the shared register, which is simple information, and the priority of the process of writing data to each shared register are input, so that the process can be executed between the processes. The exclusive control of the shared register can be realized to generate a description of the register transfer level of the circuit to be designed. For this reason,
There is no burden on designers for circuit design.

[0011] In addition, when the priority of accessing the shared register is changed for each process at a stage during circuit design, it can be easily performed without changing the operation description of the process.

In the high-level synthesis system, an operation description of a process input from the process operation description input means may be a description in which the plurality of processes are collectively described. In this case, the high-level synthesis system divides the operation description of the process in which the plurality of processes are collectively described into the operation description of each process, and also describes the reference to the shared register included in the operation description of each process. The high-level synthesizing unit may further include a process conversion unit that rewrites a description for requesting data writing from each process to the shared register, and the high-level synthesis unit performs an operation for each process divided by the process conversion unit. Each description may be converted into a register transfer level description.

The high-level synthesis system further comprises: a process analyzing means for analyzing the operation description of the process inputted from the process operation description input means, and outputting an analysis result in which a list of shared registers referred to for each process is output; Priority analysis means for analyzing the identification information of the shared register and the priority of the process input from the priority input means, and outputting an analysis result in which the processes referred to for each shared register are listed according to the priority. May be further provided. In this case, the shared register control description generating means may include a register transfer level for exclusive control of the shared register among the plurality of processes, based on an analysis result of the process analysis means and an analysis result of the priority order analysis means. Is generated.

In this case, the shared register control description generating means refers to a list of shared registers referred to for each process output from the process analyzing means, and for each shared register output by the priority order analyzing means. Remove processes that do not reference each shared register from the elements of the list according to the priority of the referenced process,
A description of a register transfer level relating to exclusive control of the shared register among the plurality of processes may be generated based on the list from which processes that do not refer to the shared register are deleted.

In the high-level synthesis system, the priority of the process of writing the data of each shared register input from the priority input means may include a case where the priority is set to a default. .

In order to achieve the above object, a high-level synthesis method according to a second aspect of the present invention provides an operation description of a process in which operations of a plurality of processes included in a circuit to be designed are described in a predetermined operation description language. Inputting process operation description inputting step, inputting identification information of a shared register used for data transfer between the plurality of processes, and inputting priority of a process of writing data to each shared register. An input step, a high-level synthesis step of converting a process operation description input in the process operation description input step into a register transfer level description of the process, and a process operation description input in the process operation description input step; Based on the priority of the process for each shared register input in the priority input step, A shared register control description generating step for generating a register transfer level description related to exclusive control of the shared register among a plurality of processes; a register transfer level description of the process converted in the high-level synthesis step; and the shared register control description generation Integrating the description of the register transfer level relating to the exclusive control of the shared register generated in the step.

The high-level synthesis method includes a process analyzing step of analyzing a process operation description input in the process operation description inputting step and outputting an analysis result in which a list of shared registers referred to for each process is output; A priority analysis step of analyzing the shared register identification information and the process priority input in the priority input step, and outputting an analysis result in which a list of processes referred to for each shared register is arranged according to the priority; May be further included. In this case, the shared register control description generation step includes a register related to exclusive control of the shared register among the plurality of processes, based on an analysis result in the process analysis step and an analysis result in the priority order analysis step. A description of the transfer level may be generated.

In order to achieve the above object, a computer-readable recording medium according to a third aspect of the present invention comprises:
A process operation description input step of inputting a process operation description in which the operations of a plurality of processes included in a circuit to be designed are described in a predetermined operation description language; and used for data transfer between the plurality of processes. A priority input step of inputting identification information of the shared register and a priority of a process of writing data to each shared register; and a process transfer description of the process input in the process operation description input step is a register transfer level of the process. Based on the high-level synthesis step of converting the description into the description of the process, the operation description of the process input in the input step of process operation description, and the priority of the process for each shared register input in the priority input step. Of register transfer level for exclusive control of the shared register between processes Generating a shared register control description, generating a description of a register transfer level of the process converted in the high-level synthesis step, and a description of a register transfer level relating to exclusive control of the shared register generated in the shared register control description generating step. And recording a program for executing the integrating step.

The recording medium analyzes a process operation description input in the process operation description input step, and outputs an analysis result in which a list of shared registers to be referred to for each process is output. A priority analysis step of analyzing the identification information of the shared register and the priority of the process input in the priority input step, and outputting an analysis result in which the processes referred to for each shared register are listed according to the priority. A program for execution may be further recorded. in this case,
The shared register control description generation step includes the step of generating a register transfer level related to exclusive control of the shared register among the plurality of processes based on an analysis result in the process analysis step and an analysis result in the priority analysis step. A description can be generated.

[0020]

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of a high-level synthesis system according to this embodiment. As shown in the figure, the high-level synthesis system includes a data processing device 1 that operates under program control, and a storage device 2 that stores information.
And

The storage device 2 stores a shared register name and priority 21 and an operation description 22 of a process as input data. The storage device 2 also includes an internal table 23 as primary storage data, an RTL description 24 of the process,
The shared register with priority RTL description 25 is stored. The storage device 2 further stores a composite process RTL description 26 as output data.

The shared register name and priority 21 are made up of processes that may access each register and their priorities in association with the names of the shared registers. The shared register name and the priority order 21 are input from a predetermined input device by a designer at a stage before high-level synthesis in circuit design and are stored in the storage device 2 in advance.

FIG. 2 shows an example of the shared register name and the priority 21. Here, procA, procB, procC, procD
4 processes of Reg1, Reg2, Reg3, Reg4
This shows a case where two shared registers are shared. Also,
The priority of a process that refers to a shared register is set to a default order unless otherwise specified. Here, the priority of the process referring to Reg3 is procB, pro
In the order of cA, the priority of the process that refers to Reg4 is proc
This indicates that the priority order of the processes referring to Reg1 and Reg2 in the order of D, procC, procB, and procA is the order of procA, procB, procC, and procD set by default.

The process operation description 22 collectively describes, using a predetermined operation description language, hardware specifications at the operation level of each process constituting a circuit to be designed. The shared register referred to by each process must be extern declared in the operation description of the process. The process operation description 22 is input from a predetermined input device by a designer at a stage before high-level synthesis in circuit design and is stored in the storage device 2 in advance.

FIG. 3 shows an example of the operation description 22 of the process. Here, procA stores Reg1 and Reg2, and procB stores Re1 and Reg2.
g2 and Reg4, procC is Reg2 and Reg3, procD is
This indicates that Reg1, Reg2, Reg3, and Reg4 are referred to. The operation description 22 of the process may be put together as one register with the shared register name and the priority 21.

The internal table 23 includes a process priority list listing the processes and their priorities that are referenced for each shared register, and a shared register list listing the shared registers and their priorities that are referenced for each process. It is something that is memorized.

The RTL description 24 of the process is an RTL description resulting from the high-level synthesis unit 11 converting the operation description 22 of the process into an RTL description.

The prioritized shared register control unit RTL description 25 contains information for the shared register RTL output unit 14 to perform exclusive control of shared registers between processes based on the shared register list as the internal table 23. R
The TL description is output. As this description,
As described in detail below, an if-else statement or the like is used.

The composite process RTL description 26 is obtained by integrating the RTL description 24 of the process and the RTL description 25 with the shared register control unit with priority by the RTL integration unit 15.
This is a TL description. FIG. 4 schematically shows an example of the composite RTL description 26. In this example, a priority-added shared register control unit (RTL description) 25 and a process A circuit (R
TL description) 24A and process B circuit (RTL description)
24B.

Here, the priority-added shared register control unit 2
5 is a circuit A of the process A and a circuit 24 of the process B.
When the request for writing data to the shared register is received from both B and B at the same time, information on the exclusive control of the shared register (shared register exclusive control unit) is checked, and a write request from a process with a higher priority is accepted. The data from this process is written to a shared register.

The data processor 1 includes a high-level synthesis unit 11, a process priority analysis unit 12, a shared register reference process analysis unit 13, a shared register RTL output unit 14, and a high-level synthesis unit 11, which are realized by executing predetermined programs. , R
A TL integration unit 15 and a process conversion unit 16 are provided.

The process conversion section 16 reads the operation description 22 of the process from the storage device 2 as pre-processing by the high-level synthesis section 11 and divides this into a separate file for each process. Further, the process conversion unit 16 changes the description related to writing to the shared register in the operation description of each divided process. That is, the process conversion unit 16
Generates a new description of a signal for making a write request to the shared register and inserts it into the corresponding part of the operation description for each process.

The high-level synthesizing unit 11 reads the behavioral descriptions of the processes, which are divided for each process by the process converting unit 16 and whose description has been changed, respectively, reads them in order, converts them into RTL descriptions having the same logic inside, and converts the process descriptions into RTL descriptions. It is output as the RTL description 24 and stored in the storage device 2.

The process priority analysis unit 12 reads the shared register name and the priority 21 from the storage device 2 and analyzes them to obtain a list of the processes to be referred to for each shared register and the priorities. The ranking list is generated as one of the internal tables 23 and stored in the storage device 2.

The shared register reference process analyzing unit 13
By reading the operation description 24 of the process from the storage device 2 and analyzing the registers actually referred to by each process,
A shared register list that lists the shared registers to be referred to for each process and their priorities is set as one of the internal tables 23, generated, and stored in the storage device 2.

The shared register RTL output unit 14 refers to the process priority list and the shared register list stored in the storage device 2 as the internal table 23, and exclusively controls the shared registers used between the processes. The information is generated as the priority-added shared register control unit RTL description 25 and stored in the storage device 2.

The RTL integration unit 15 reads out the RTL description 24 of the process and the RTL description 25 of the shared register control unit with priority from the storage device 2 and integrates them to generate a composite process RTL description 26, The data is stored in the storage device 2 as the output data of the system.

The operation of the high-level synthesis system according to this embodiment will be described below. Here, the storage device 2
Has the shared register name and priority 21 shown in FIG.
And the operation description 22 of the process shown in FIG. 3 are input and stored in advance from a predetermined input device before the high-level synthesis in the circuit design.

FIG. 5 is a flowchart showing the operation of the high-level synthesis system according to this embodiment.

First, the process conversion unit 16 reads the operation description 22 of the process. The operation description 22 of the read process describes a plurality of processes collectively, but the process conversion unit 16 divides the process into separate files for each process. At this time, if there is a description about writing to the shared register in the operation description of the divided process, a signal for a write request of the shared register is prepared, and the data is written to the shared register control unit before writing data to the shared register. The description is changed to a description that issues a write request signal to the user (step A1).

Here, for the sake of simplicity, an example of an operation description of a process different from that of FIG. 3 will be described with reference to FIG. 9. The operation description of this process is obtained by the process conversion unit 16 as shown in FIG. Will be expanded to. That is, new outputs Reg1_procA and Reg1_procA0 for accessing the shared register Reg1 in this process are added.

Here, Reg1_procA0 is a write request signal, indicating that procA is a write request to Reg1. Reg1_procA is a write-only data signal, and writing to Reg1 is performed via this. When writing to shared register Reg1, first write request signal Reg1
Set 1 to _procA0 and write data to Reg1_procA.
When data writing is completed, the write request signal Reg1
_procA0 is set to 0, and the shared register Reg1 is released to another process.

Next, the high-level synthesis unit 11 receives the operation description of the process divided for each process by the process conversion unit 16, converts this into an RTL description, and converts the RTL description of the process.
It is output as the description 24 and stored in the storage device 2 (step A2).

Next, the process priority analysis unit 12 performs a process for analyzing the shared register name and the process priority (step A3). FIG. 6 is a flowchart showing the process of step A3 in detail.

The process priority analysis unit 12 reads the shared register name and the priority 21 line by line (step B1), and determines whether or not this is a declaration of the shared register name (step B3). If it is not a declaration of a shared register name, the process returns to step B1 and proceeds to read the next line.

On the other hand, in the case of a declaration of a shared register name, the process priority analysis unit 12 obtains a priority list of processes using the declared shared register, and uses the shared register name as a key. It is stored in the internal table 23 as a list (step B4). Then, the process returns to step B1. When the reading of all the rows is completed (step B2), the processing of this flowchart ends, and the processing returns to the processing of the flowchart of FIG.

Here, the default process priority is specified on the first line. Reg1 and Reg2 do not have explicit priorities, so defaults apply. Since Reg3 is a partial specification, it is given priority in the order of B and A. Reg4 specifies all priorities. Therefore, in this example, the process priority list stored as the internal table 23 is as shown in FIG.

When returning from the processing of the flowchart of FIG. 6, the shared register referring process analyzing unit 13 analyzes the operation description of the process divided for each process by the process converting unit 16, and analyzes the process referring to the shared register. Processing is performed (step A4). FIG. 7 is a flowchart showing the processing of step A4 in detail.

The shared register reference process analyzing unit 13
First, the operation description of the process divided by the process conversion unit 16 is read for each process (step C1).
Then, the shared register reference process analyzing unit 13 lists the names of the shared registers used in the process (Step C3). FIG. 8 is a flowchart showing the process of step C3 in detail.

That is, the shared register reference process analysis unit 13 reads the operation description of the process divided for each process line by line (step D1), and determines whether or not this is a declaration of a shared register name. (Step D3). If it is not a declaration of a shared register name, the process returns to step D1 and proceeds to read the next line.

On the other hand, if it is a declaration of a shared register name, the shared register referring process analyzing unit 13 stores the shared register in the internal table 23 as a shared register list using the process name as a key (step D4). Then, the process returns to step D1. When the reading of all the rows is completed (step D2), the processing of this flowchart ends, and the processing returns to the processing of the flowchart of FIG.

As in this example, the process operation description 22
3 is described as shown in FIG. 3, since the shared registers are explicitly declared in the description of each process, the processing here is simply that they are stored in the internal table 23. Only be done. At this time, the state of the shared register list stored as the internal table 23 is
As shown in FIG.

When the process description unit 16 has finished reading the operation descriptions of all the processes divided for each process (step C 2), the shared register reference process analysis unit 13 stores them as the internal table 23. The process for checking the list of process priorities and the shared register list is started. That is, the process priority list may include a process that does not actually refer to the register. Therefore, the redundant process is deleted from the process priority list by checking the list of the shared registers actually referred to by the process.

Here, the shared register referring process analysis unit 13 reads one shared register list using the process name as a key (step C4). Here, the process name used as the key is the current process. Next, the shared register process analysis unit 13 refers to the process priority list using all the registers included in the read list as keys, and if the list has the current process as an element, checks that element. (Step C6). This operation is performed for all process entries. As a result, a process name that is not checked in the process priority list is not actually referred to, and can be deleted in step C7 described later.

In this example, the shared register list is shown in FIG.
In the state shown in FIG. 12, the process priority list is in the state shown in FIG. At this time, first, the list of procA in FIG. 12 is read. The shared register list of procA is Reg1, R
Since it has eg2 as an element, the proc in the Reg1 list in FIG.
A, procA of Reg2 list is checked. Similarly, FIG.
By analyzing the procB list in FIG. 2, Reg2 and Reg4 in FIG.
The procB in the list is checked. When all the shared register lists have been processed, the process priority list becomes as shown in FIG. Here, the colored elements are checked, that is, they are actually used in the process. Conversely, an element without a color is not referenced and indicates that it is a redundant element.

When the above-described process check has been completed for all of the shared registers serving as keys in the shared register list (step C5), the shared register referring process analysis unit 13 identifies the processes not checked from the process priority list. It is deleted (step C7). Then, the process of this flowchart ends, and the process returns to the process of the flowchart of FIG. At this point, the process priority list from which the redundant description in the internal table 23 has been removed is as shown in FIG.

When returning from the process of the flowchart of FIG. 7, the shared register RTL output unit 14 stores the process priority list from which the redundant description has been removed into the internal table 23.
Read from. The shared register RTL output unit 14 generates an RTL description for controlling access to the shared register according to the read process priority list, outputs the RTL description as a shared register with priority RTL description 25, and stores the RTL description 25 in the storage device 2 ( Step A5).

Here, the control unit RTL description of Reg1 (here, Verilog HDL is used) is as shown in FIG. In this example, since Reg1 is referenced from procA and procD, the shared register control unit has two write data signals (Reg1_procA, Reg1_procD) and two write request signals (Reg1_procA0, Reg1_procD0). Where Re
The value of g1 is determined by the if-else statement. If the signal of Reg1_procA0 is set, Reg1_procA is unconditionally set.
If g1_procD0 is set, Reg1_procD is written to Reg1. As a result, exclusive control with priority of procA> procD is realized.

Finally, the RTL integrating unit 15 integrates the RTL description 24 of the process and the shared register control unit with priority RTL description 25 stored in the storage device 2 and outputs them as the composite process RTL description 26. In the storage device 2 (step A6). Thus, the high-level synthesis processing in the high-level synthesis system according to this embodiment ends.

When the high-level synthesis processing is completed as described above and the composite process RTL description 26 is stored in the storage device 2, the circuit design device (even if it is realized on the data processing device 1). OK) is the composite process RTL
A logic design is performed according to the description 26, and a circuit corresponding to the operation described in the operation description 22 of the process is designed.

As described above, in the high-level synthesis system according to this embodiment, before performing high-level synthesis in circuit design, only the shared register and the priority 21 in addition to the process operation description 24 can be used by the designer. Is created and stored in the storage device 2, a composite process RTL description 26 that can exclusively control a shared register used for data exchange between processes included in the process operation description 24 is obtained. Then, by performing a logic design according to the composite RTL description 26, it is possible to design a circuit that realizes exclusive control of a shared register between processes.

That is, in order to realize exclusive control of the shared register between the processes, the designer not only describes the hardware specifications only in a predetermined operation description language, but also describes the shared register name and the priority 21. You only need to create simple information. Therefore, there is almost no burden on the designer when designing the circuit.

The shared register name and priority 21
Are created separately from the process operation description 22 and stored in the storage device 2. Therefore, even when the priority of accessing the shared register is changed for each process at a stage during the circuit design, it can be easily performed without changing the operation description 22 of the process.

The present invention is not limited to the above embodiment,
Various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the above embodiment, the process operation description 22 describes a plurality of processes collectively and is stored in the storage device 2. Then, the process conversion unit 1
6 for each process. However, the process may be described as being divided for each process from the beginning, and may be stored in the storage device 2. In this case, the process conversion unit 16 does not need a function for dividing the operation description of the process for each process.

In the above embodiment, the shared register RT
The L output unit 14 controls the priority-added shared register control unit based on the process priority list that is the analysis result of the process priority analysis unit 12 and the shared register list that is the analysis result of the shared register reference process analysis unit 13. RTL
The description 25 is generated and stored in the storage device 2. However, without creating such a list as intermediate data, the shared register RTL output unit 14 refers to the shared register name and priority list 21 and the process operation description 22 as they are (operation of the process). The description 22 includes a case where the description is divided for each process by the process conversion unit 16), and the shared register control unit with priority RTL description 25 may be generated.

In the above embodiment, the shared register name and priority 21 and the operation description 22 of the process are input from a predetermined input device at a stage before high-level synthesis in circuit design, and are stored in the storage device 2 in advance. It was assumed that.
However, the shared register name and priority 21 and the operation description 22 of the process may be created and stored as a library, and read out from the library and stored in the storage device 2 when starting high-level synthesis. .

In the above-described embodiment, an example in which a circuit composed of three processes is designed in FIG. 1 and a circuit composed of four processes is described in FIGS. Thus, it can be applied to any circuit design that uses a shared register to exchange data between processes.

In the above embodiment, the data processing device 1
Operates under program control, and is realized by execution of the program. The high-level synthesis unit 11, the process priority analysis unit 12, the shared register reference process analysis unit 13, the shared register RTL output unit 14, the RTL integration unit 15, and The process conversion unit 16 was provided. On the other hand, a program for implementing each of the units 11 to 16 may be stored in a computer-readable recording medium such as a CD-ROM and distributed.

[0071]

As described above, according to the present invention,
In order to realize exclusive control of the shared register between processes, in addition to the operation description of the process, the identification information of the shared register, which is simple information, and the priority of the process for writing data to each shared register are input. Since it suffices, no burden is imposed on the designer for the circuit design.

Further, even when the priority of accessing the shared register is changed for each process in the course of circuit design, it can be easily performed without changing the operation description of the process.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a high-level synthesis system according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of shared register names and priorities stored in a storage device of FIG. 1;

FIG. 3 is a diagram illustrating an example of an operation description of a process stored in the storage device of FIG. 1;

FIG. 4 is a diagram schematically showing the composite process RTL description of FIG. 1;

FIG. 5 is a flowchart showing the operation of the high-level synthesis system according to the embodiment of the present invention.

FIG. 6 is a flowchart showing in detail a process of “analysis of shared register name and process priority” in FIG. 5;

FIG. 7 is a flowchart showing in detail a process of “shared register reference process analysis” of FIG. 5;

FIG. 8 “Acquisition of shared register name in process” in FIG. 7
3 is a flowchart showing the details of the process.

FIG. 9 is a diagram showing another example of the operation description of the process.

10 is a diagram showing a result obtained by converting the operation description of the process of FIG. 9 by the process conversion unit of FIG. 1;

FIG. 11 is a diagram showing a shared register list stored as an internal table in FIG. 1;

12 is a diagram showing a shared register list stored as an internal table in FIG. 1 as a result of analyzing a shared register name and a priority in FIG. 3 by a process priority analysis unit.

13 is a diagram showing a process priority list stored as an internal table in FIG. 1 and a state in which the shared register reference process analysis unit in FIG. 1 refers to the shared register list in FIG. 2;

FIG. 14 is a diagram showing a process priority list generated in the state of reference shown in FIG. 13;

15 is a shared register control unit with priority RTL of FIG. 1;
It is a figure which shows a description.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 data processing device 2 storage device 11 high-level synthesis unit 12 process priority analysis unit 13 shared register reference process analysis unit 14 shared register RTL output unit 15 RTL integration unit 16 process conversion unit 21 shared register name and priority 22 process operation description 23 Internal Table 24 Process RTL Description 25 Shared Register Control Unit RTL Description with Priority 26 Complex Process RTL Description

Claims (9)

(57) [Claims] 1. A process operation description input means for inputting an operation description of a process in which operations of a plurality of processes included in a circuit to be designed are described in a predetermined operation description language; Priority input means for inputting identification information of a shared register used for transfer and priority of a process for writing data to each shared register; and a process operation description input from the process operation description input means. A high-level synthesizing unit that converts the description into a register transfer level description of the process; a process operation description input from the process operation description input unit; and a process priority for each shared register input from the priority input unit. A description of a register transfer level related to exclusive control of the shared register among the plurality of processes. A shared register control description generating unit that integrates a description of a register transfer level of a process converted by the high-level synthesizing unit and a description of a register transfer level related to exclusive control of the shared register generated by the shared register control description generating unit. A high-level synthesis system comprising: 2. The process operation description input from the process operation description input means describes the plurality of processes collectively. The process description describes the process description collectively describing the plurality of processes. In addition to dividing into operation descriptions for each process,
The high-level synthesizing unit further includes a process conversion unit that rewrites a description related to the reference to the shared register included in the operation description of each process to a description that requests to write data from each process to the shared register. 2. The high-level synthesis system according to claim 1, wherein the operation description for each divided process is converted into a description of a register transfer level. 3. A process analysis means for analyzing a process operation description input from the process operation description input means and outputting an analysis result in which a list of shared registers referred to for each process is output; A priority analysis unit that analyzes the input identification information of the shared register and the priority of the process, and outputs an analysis result in which a process referred to for each shared register is listed according to the priority; The shared register control description generating means generates a register transfer level description relating to the exclusive control of the shared register among the plurality of processes, based on the analysis result of the process analyzing means and the analysis result of the priority order analyzing means. The high-level synthesis system according to claim 1, wherein: 4. The shared register control description generating means refers to a list of shared registers output from the process analyzing means and referenced for each process, and is referenced for each shared register output by the priority order analyzing means. The process that does not refer to each shared register is deleted from the elements of the list according to the priority of the process to be executed.Based on the list in which the processes that do not refer to this shared register are deleted, the process between the plurality of processes is performed. 4. The high-level synthesis system according to claim 3, wherein a description of a register transfer level related to exclusive control of a shared register is generated. 5. The process according to claim 1, wherein the priority of the process of writing data of each shared register input from said priority input means includes a case where default priority is set. The high-level synthesis system according to any one of the above items. 6. A process operation description inputting step of inputting an operation description of a process in which operations of a plurality of processes included in a circuit to be designed are described in a predetermined operation description language; A priority input step for inputting identification information of a shared register used for transfer and a priority of a process for writing data to each shared register; and an operation description of the process input in the process operation description input step. A high-level synthesis step of converting the description into a register transfer level description of the process; a process operation description input in the process operation description input step; and a process priority of each shared register input in the priority input step. On the basis of,
A shared register control description generating step of generating a register transfer level description relating to exclusive control of the shared register among the plurality of processes; a register transfer level description of the process converted in the high-level synthesis step; and the shared register control description An integrating step of integrating a description of a register transfer level relating to exclusive control of the shared register generated in the generating step. 7. A process analysis step of analyzing a process operation description input in the process operation description input step, and outputting an analysis result in which a list of shared registers to be referred to for each process is output; Analyzing the identification information of the shared register and the priority of the process input in the, and a priority analysis step of outputting an analysis result as a list according to the priority of the processes referenced for each shared register, further comprising: The shared register control description generation step includes the step of generating a register transfer level related to exclusive control of the shared register among the plurality of processes based on an analysis result in the process analysis step and an analysis result in the priority analysis step. 7. The high-level synthesis method according to claim 6, wherein the description is generated. 8. A process behavior description inputting step of inputting a behavior description of a process in which the behavior of a plurality of processes included in a circuit to be designed is described in a predetermined behavior description language; A priority input step for inputting identification information of a shared register used for transfer and a priority of a process for writing data to each shared register; and an operation description of the process input in the process operation description input step. A high-level synthesis step of converting the description into a register transfer level description of the process; a process operation description input in the process operation description input step; and a process priority for each shared register input in the priority input step. On the basis of,
A shared register control description generating step of generating a register transfer level description relating to exclusive control of the shared register among the plurality of processes; a register transfer level description of the process converted in the high-level synthesis step; and the shared register control description A computer-readable recording medium for recording a program for executing an integration step of integrating a description of a register transfer level relating to exclusive control of the shared register generated in the generation step. 9. A process analysis step of analyzing a process operation description input in the process operation description inputting step and outputting an analysis result in which a list of shared registers to be referred to for each process is output; Analyzing the identification information of the shared register and the priority of the process inputted in the step (a), and outputting a result of analysis in which the processes referred to for each shared register are listed according to the priority. The shared register control description generating step further comprises: storing the shared register between the plurality of processes based on an analysis result in the process analysis step and an analysis result in the priority order analysis step. 9. The method according to claim 8, wherein a description of a register transfer level related to exclusive control is generated. Computer readable recording medium.