JPH09135020A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH09135020A
JPH09135020A JP31590495A JP31590495A JPH09135020A JP H09135020 A JPH09135020 A JP H09135020A JP 31590495 A JP31590495 A JP 31590495A JP 31590495 A JP31590495 A JP 31590495A JP H09135020 A JPH09135020 A JP H09135020A
Authority
JP
Japan
Prior art keywords
region
cathode
gate
conductivity type
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP31590495A
Other languages
Japanese (ja)
Inventor
Yoshinobu Otsubo
義信 大坪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Electric Manufacturing Ltd
Original Assignee
Toyo Electric Manufacturing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Electric Manufacturing Ltd filed Critical Toyo Electric Manufacturing Ltd
Priority to JP31590495A priority Critical patent/JPH09135020A/en
Publication of JPH09135020A publication Critical patent/JPH09135020A/en
Withdrawn legal-status Critical Current

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  • Thyristors (AREA)

Abstract

PROBLEM TO BE SOLVED: To increase a gate-cathode avalanche strength by a method wherein a first conductivity type low-resistance region is formed in contact with the bottom of a cathode region and the impurity concentration of the low-resistance region is set higher than that of a first conductivity type region. SOLUTION: P-type gate regions 6 and a p-type region 3 are formed from the surface on one side of the surfaces of an n-type semiconductor substrate constituting an n-type high-resistance layer 2. Then, a p-type low-resistance region 4 is formed. Subsequently, after an n-type cathode region 5 is formed, patterns of insulating films 10 consisting of a silicon oxide film or the like are formed. The surface impurity concentration of the region 5 is set higher than those of the regions 3 and 4. In this case, a breakdown voltage of the bent part of the junction between the region 3 and the periphery of the region 5 is higher than that of the junction part between the region 4 and the bottom of the region 5 and most of a reverse current in a breakdown flows through the junction part between the region 4 and the bottom of the region 5. As a result, the improvement of a gate-cathode avalanche strength becomes possible.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は平面ゲート構造をもつタ
ーンオフサイリスタ等の半導体装置に関し、中でもゲー
ト・カソード間の耐圧特性の改良方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a turn-off thyristor having a flat gate structure, and more particularly to a method for improving a withstand voltage characteristic between a gate and a cathode.

【0002】[0002]

【従来の技術】平面形の相対するp形ゲート領域の間に
p形領域を設け、このp形領域の表面層にn形カソード
領域が選択形成された構造を持つ半導体装置として特公
昭60ー13310号、特開平3ー219640号等に
示されるターンオフサイリスタが公知である。上記例の
ターンオフサイリスタは、ゲート・カソード間を逆バイ
アスすることなくしてアノード・カソード間の順電圧を
阻止可能ないわゆるノーマリーオフ特性が得られると共
に、従来のサイリスタに比較して改善されたターンオン
特性が得られる特徴がある。
2. Description of the Related Art As a semiconductor device having a structure in which a p-type region is provided between opposing p-type gate regions of a plane type, and an n-type cathode region is selectively formed on the surface layer of the p-type region. The turn-off thyristors disclosed in JP-A-13310, JP-A-3-219640 and the like are known. The turn-off thyristor in the above example has a so-called normally-off characteristic that can prevent the forward voltage between the anode and the cathode without reverse biasing between the gate and the cathode, and has an improved turn-on compared to the conventional thyristor. There is a feature that the characteristics can be obtained.

【0003】上記例ではp形ゲート領域に比較してp形
領域の厚さを小さくした場合に、オフ状態でp形領域に
形成される空乏層の単位面積当たり空間電荷量をp形ゲ
ート領域の空間電荷量に比較して小さくできる事によ
り、p形領域のシート抵抗を従来のサイリスタよりも大
きくする事が可能である。さらにターンオフ特性を改善
するには、n形カソード領域の中央部直下のp形領域か
らゲート電極に至る間の抵抗の低減が有効であって、そ
のための手段として相対するp形ゲート領域の間隔及び
p形領域の幅を小さくする等、単位素子の微細化が図ら
れる。
In the above example, when the thickness of the p-type region is made smaller than that of the p-type gate region, the space charge amount per unit area of the depletion layer formed in the p-type region in the off state is calculated as the p-type gate region. The sheet resistance of the p-type region can be made larger than that of the conventional thyristor because it can be made smaller than the space charge amount. In order to further improve the turn-off characteristic, it is effective to reduce the resistance between the p-type region directly below the central portion of the n-type cathode region and the gate electrode. The unit element can be miniaturized by reducing the width of the p-type region.

【0004】[0004]

【発明が解決しようとする課題】上記例のターンオフサ
イリスタはターンオフ時にゲート・カソード間が逆バイ
アスされて降伏する際のアバランシェ耐量が不足しがち
である。このようなサイリスタの場合、p形領域にn形
カソード領域が選択形成されたpn接合の降伏電圧は周
辺の接合の曲がりの部分で最小になり易い。一方単位素
子の微細化に伴いn形カソード領域の厚さが低減され、
ひいては周辺部の接合曲がりが小さくなることにより、
接合曲がりの部分で降伏電流が大きくなる事が、アバラ
ンシェ耐量不足要因になると言える。本発明は上述した
点に鑑みて創案されたもので、その目的とするところ
は、ゲート・カソード間のアバランシェ耐量の向上に有
効な手段を提供する事、及び単位素子を多数並列配置し
て大面積化・大電流化する場合に有効な手段を提供する
ことにある。
The turn-off thyristor of the above example is apt to have an insufficient avalanche withstanding capability when the gate and cathode are reverse-biased at the time of turn-off and breakdown occurs. In the case of such a thyristor, the breakdown voltage of the pn junction in which the n-type cathode region is selectively formed in the p-type region tends to be minimized in the bent portion of the peripheral junction. On the other hand, the thickness of the n-type cathode region is reduced with the miniaturization of the unit element,
As a result, the junction bending in the peripheral area becomes smaller,
It can be said that the increase in the breakdown current at the junction bending portion causes a lack of avalanche withstand capability. The present invention has been made in view of the above-mentioned points, and an object thereof is to provide an effective means for improving the avalanche withstand capability between the gate and the cathode, and to arrange a large number of unit elements in parallel. It is to provide an effective means for increasing the area and increasing the current.

【0005】[0005]

【課題を解決するための手段】つまり、その目的を達成
するための手段は、請求項1に記載の半導体装置は平面
形の相対する第1導電形のゲート領域の間に不純物濃度
がゲート領域よりも低い第1導電形領域を設け、第1導
電形領域の表面層に第2導電形のカソード領域が選択形
成され、カソード領域表面にカソード電極が接続された
構造をもつ半導体装置において、カソード領域の低面に
接して第1導電形の低抵抗領域が形成され、かつ低抵抗
領域の不純物濃度が第1導電形領域よりも高く設定され
るものである。
That is, the semiconductor device according to claim 1 is a means for achieving the above-mentioned object. A semiconductor device having a structure in which a lower first conductivity type region is provided, a second conductivity type cathode region is selectively formed on a surface layer of the first conductivity type region, and a cathode electrode is connected to the cathode region surface. A low resistance region of the first conductivity type is formed in contact with the lower surface of the region, and the impurity concentration of the low resistance region is set higher than that of the first conductivity type region.

【0006】請求項2に記載の半導体装置は、平面形の
相対する第1導電形のゲート領域の間に不純物濃度がゲ
ート領域よりも低い第1導電形領域を設け、第1導電形
領域の表面層に第2導電形のカソード領域が選択形成さ
れた単位素子が複数個並列配置された領域を囲んで第1
導電形のフレームゲート領域が形成され、フレームゲー
ト領域の表面にゲート電極が接続され、単位素子のカソ
ード領域以外に絶縁膜が設けられ、カソード電極がカソ
ード領域表面に接続されかつ絶縁膜上に延在して設けら
れた構造をセグメントとなし、該セグメントを複数個並
列配置し、各セグメントのフレームゲート領域及びゲー
ト電極は連結され、かつ各セグメントのカソード電極は
共通の圧接電極を介して圧接接触により並列接続され、
ゲート電極の一部にはゲート取り出し電極が接続される
事を特徴とする請求項1に記載の半導体装置としての構
成を有する。
According to another aspect of the semiconductor device of the present invention, a first conductivity type region having an impurity concentration lower than that of the gate region is provided between the planarly opposed gate regions of the first conductivity type. A first region is formed by surrounding a region in which a plurality of unit devices in which a cathode region of the second conductivity type is selectively formed on the surface layer are arranged in parallel.
A conductive type frame gate region is formed, a gate electrode is connected to the surface of the frame gate region, an insulating film is provided in a portion other than the cathode region of the unit element, and the cathode electrode is connected to the cathode region surface and extends on the insulating film. The existing structure is formed as a segment, a plurality of the segments are arranged in parallel, the frame gate region and the gate electrode of each segment are connected, and the cathode electrode of each segment is pressure-contacted via a common pressure-contact electrode. Connected in parallel by
A gate take-out electrode is connected to a part of the gate electrode, and the semiconductor device has the structure according to claim 1.

【0007】また、請求項3に記載の半導体装置は、平
面形の相対する第1導電形のゲート領域の間に不純物濃
度がゲート領域よりも低い第1導電形領域を設け、第1
導電形領域の表面層に第2導電形のカソード領域が選択
形成された単位素子が複数個並列配置された領域を囲ん
で第1導電形のフレームゲート領域が形成され、フレー
ムゲート領域が一部掘り込まれ、かつ掘り込まれた表面
部に第1導電形の高濃度領域が形成され、そしてゲート
電極が掘り込まれた低面に接続され、単位素子のカソー
ド領域以外に絶縁膜が設けられ、カソード電極がカソー
ド領域表面に接続されかつ絶縁膜上に延在して設けられ
た構造をセグメントとなし、該セグメントを複数個並列
配置し、各セグメントのフレームゲート領域及びゲート
電極は連結され、かつ各セグメントのカソード電極は共
通の圧接電極を介して圧力接触により並列接続され、ゲ
ート電極の一部にゲート取り出し電極が接続される事を
特徴とする請求項1に記載の半導体装置としての構成を
有する。
According to another aspect of the semiconductor device of the present invention, a first conductivity type region having an impurity concentration lower than that of the gate region is provided between the planarly opposed first conductivity type gate regions.
A frame gate region of the first conductivity type is formed by surrounding a region in which a plurality of unit elements in which a cathode region of the second conductivity type is selectively formed on the surface layer of the conductivity type region is arranged, and the frame gate region is partially formed. A high-concentration region of the first conductivity type is formed in the dug and dug surface portion, and a gate electrode is connected to the dug low surface, and an insulating film is provided in a portion other than the cathode region of the unit element. A segment having a structure in which the cathode electrode is connected to the surface of the cathode region and extends on the insulating film, and a plurality of the segments are arranged in parallel, and the frame gate region and the gate electrode of each segment are connected, A cathode electrode of each segment is connected in parallel by pressure contact through a common pressure contact electrode, and a gate extraction electrode is connected to a part of the gate electrode. Having the configuration of a semiconductor device according to.

【0008】[0008]

【作用】請求項1に記載の半導体装置によれば、第1導
電形の低抵抗領域と第2導電形のカソード領域の低面と
の接合は曲がりを低減し形状を平坦化しやすく、かつ降
伏電圧を低抵抗領域の不純物濃度で容易に調整できる。
そして、第2導電形のカソード領域周辺の接合の曲がり
の部分に比較して、カソード領域低面部分の降伏電圧を
低く設定する事ができる。従ってゲート・カソード間が
逆バイアスされた時の降伏電流はカソード領域の低面の
接合で大であって、カソード領域周辺の接合の曲がりの
部分で小になし得ることによりアバランシェ耐量の改善
が可能になる。
According to the semiconductor device of the first aspect, the junction between the low resistance region of the first conductivity type and the lower surface of the cathode region of the second conductivity type reduces bending, makes it easy to flatten the shape, and causes breakdown. The voltage can be easily adjusted by the impurity concentration in the low resistance region.
Then, the breakdown voltage of the lower surface portion of the cathode region can be set lower than that of the bent portion of the junction around the cathode region of the second conductivity type. Therefore, the breakdown current when the gate and cathode are reverse-biased is large at the low-side junction of the cathode region, and can be made small at the bend of the junction around the cathode region, thus improving the avalanche withstand capability. become.

【0009】請求項2に記載の半導体装置によれば単位
素子が複数個並列配置されたセグメントを並列配置し
て、セグメントのカソード電極を共通の圧接電極で一括
圧接(圧接接触)することにより、素子の大面積化、大
電流化が容易になると共に、信頼生の向上および素子の
両面冷却が可能な事による熱抵抗の低減が得られる。請
求項3に記載の半導体装置によれば各セグメントのカソ
ード電極とゲート電極との段差を大きくする事が容易で
あって、圧接電極を用いてカソード電極を一括圧接する
ときにゲート・カソード電極間の絶縁距離を大きくする
事ができる、とともに素子の組立が容易になる。以下、
本発明の一実施例を図面に基づいて詳述する。
According to the semiconductor device of the second aspect, the segments in which a plurality of unit elements are arranged in parallel are arranged in parallel, and the cathode electrodes of the segments are collectively pressure-contacted (press-contact) with a common press-contact electrode. It is possible to increase the area of the element and increase the current, and it is possible to improve reliability and reduce the thermal resistance by allowing both sides of the element to be cooled. According to the semiconductor device of claim 3, it is easy to increase a step between the cathode electrode and the gate electrode of each segment, and when the cathode electrodes are collectively pressure-contacted by using the pressure-contact electrode, the gap between the gate and the cathode electrode is reduced. The insulation distance can be increased, and the element can be easily assembled. Less than,
An embodiment of the present invention will be described in detail with reference to the drawings.

【0010】[0010]

【実施例】本発明の第一の実施例の半導体装置としての
ターンオフサイリスタを図1を用いて説明する。図1は
ターンオフサイリスタを構成する単位素子の断面説明図
であって、図中、1はp形アノード領域、2はn形半導
体基板からなるn形高抵抗層、3はp形領域、4はp形
低抵抗領域、5はn形カソード領域、6はp形ゲート領
域、7はアノード電極、8はカソード電極、そして9は
ゲート電極である。本実施例の製造工程を図2を用いて
説明する。図2aに示されるようにn形高抵抗層2を構
成するn形半導体基板の一方の表面からp形ゲート領域
6とp形領域3をホウ素の選択拡散法で形成する。次に
図2bに示されるようにp形低抵抗領域4をホウ素の選
択拡散法で形成する。続いて図2cに示されるようにn
形カソード領域5をリン叉はヒ素の選択拡散法で形成し
た後に、シリコン酸化膜等からなる絶縁膜10のパターン
を形成する。引き続いて図1に示されるようにアノード
電極7、カソード電極8及びゲート電極9をアルミニウ
ムを蒸着して形成する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A turn-off thyristor as a semiconductor device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional explanatory view of a unit element constituting a turn-off thyristor, in which 1 is a p-type anode region, 2 is an n-type high resistance layer made of an n-type semiconductor substrate, 3 is a p-type region, and 4 is a p-type region. A p-type low resistance region, 5 is an n-type cathode region, 6 is a p-type gate region, 7 is an anode electrode, 8 is a cathode electrode, and 9 is a gate electrode. The manufacturing process of this embodiment will be described with reference to FIG. As shown in FIG. 2a, a p-type gate region 6 and a p-type region 3 are formed from one surface of an n-type semiconductor substrate forming the n-type high resistance layer 2 by a selective diffusion method of boron. Next, as shown in FIG. 2b, the p-type low resistance region 4 is formed by the selective diffusion method of boron. Then, as shown in FIG. 2c, n
After the cathode region 5 is formed by the phosphorus or arsenic selective diffusion method, the pattern of the insulating film 10 made of a silicon oxide film or the like is formed. Subsequently, as shown in FIG. 1, an anode electrode 7, a cathode electrode 8 and a gate electrode 9 are formed by evaporating aluminum.

【0011】接合構造例としてn形カソード領域の表面
不純物濃度が1×1020cm3 、厚さが2μmであっ
て、p形領域およびp形低抵抗領域の不純物濃度が各々
1×1016、1×1017cm3 と成される。この場合に
接合の降伏電圧はp形領域とn形カソード領域周辺の接
合の曲がりの部分が約25V、p形低抵抗領域とn形カ
ソード領域の低面の接合部分が約20vであって降伏時
の逆電流の殆どがn形カソード領域の低面の接合部分を
流れる。
As an example of the junction structure, the surface impurity concentration of the n-type cathode region is 1 × 10 20 cm 3 , the thickness is 2 μm, and the impurity concentration of the p-type region and the p-type low resistance region is 1 × 10 16 , respectively. It is composed of 1 × 10 17 cm 3 . In this case, the breakdown voltage of the junction is about 25 V at the bent portion of the junction around the p-type region and the n-type cathode region, and about 20 V at the junction portion of the low surface of the p-type low resistance region and the n-type cathode region. Most of the reverse current flows through the lower junction of the n-type cathode region.

【0012】第2の実施例としてのターンオフサイリス
タを図3を用いて説明する。図3は単位素子が複数個並
列配置された構成のセグメントの断面構造を示し、図中
の11は単位素子が並列配置された領域を囲むフレームゲ
ート領域、20はゲート電極、21はカソード電極、12はゲ
ート電極とカソード電極間の短絡を防止するためのポリ
イミド等からなる絶縁材でありその他の説明は図1と同
様である。図3に示されるセグメントは図の左右方向が
1〜3mm、図に垂直方向が0.1〜0.3mmであっ
て、このようなセグメントが例えば同心の放射状に並列
配置される。各セグメントのカソード電極21を囲むゲー
ト電極20は通常素子全体にわたって連結される。並列配
置されたカソード電極はモリブデンやタングステンから
なる共通の圧接電極21を介して圧接により並列接続され
る。なおゲート電極には素子の中央叉は外周部分でゲー
ト用の圧接電極が圧接される。
A turn-off thyristor as a second embodiment will be described with reference to FIG. FIG. 3 shows a cross-sectional structure of a segment in which a plurality of unit elements are arranged in parallel. In the figure, 11 is a frame gate region surrounding the area where the unit elements are arranged in parallel, 20 is a gate electrode, 21 is a cathode electrode, Reference numeral 12 is an insulating material made of polyimide or the like for preventing a short circuit between the gate electrode and the cathode electrode, and the other description is the same as in FIG. The segments shown in FIG. 3 have a horizontal direction of 1 to 3 mm in the drawing and a vertical direction of 0.1 to 0.3 mm in the drawing, and such segments are, for example, concentrically and radially arranged in parallel. The gate electrode 20 surrounding the cathode electrode 21 of each segment is usually connected throughout the device. The cathode electrodes arranged in parallel are connected in parallel by pressure contact via a common pressure contact electrode 21 made of molybdenum or tungsten. A gate pressure contact electrode is pressure contacted with the gate electrode at the center or outer periphery of the device.

【0013】第3の実施例としてのターンオフサイリス
タを図4に示されるセグメント断面図を用いて説明す
る。第3の実施例が第2の実施例と異なるのはフレーム
ゲート領域13が掘り込まれ、かつその表面部にp形の高
濃度領域14が形成され、そしてゲート電極30が掘り込ま
れた低面に接続された点であって、その他は第二の実施
例と同様である。第3の実施例はゲート電極とカソード
電極の段差を第2の実施例に比較して大きくするのが容
易であって、カソード電極上の圧接電極32とゲート電極
との絶縁距離を大きくする事が容易である。 本発明は
上記実施例のターンオフサイリスタのアノード領域をカ
ソード領域と同一の導電形にする事によりトランジスタ
への適用例になる。更に上記実施例で示されるカソード
電極に圧接電極が圧力接触される代わりに溶着法で接続
され得る事は明かである。
A turn-off thyristor as a third embodiment will be described with reference to the segment sectional view shown in FIG. The third embodiment differs from the second embodiment in that a frame gate region 13 is dug in, a p-type high-concentration region 14 is formed in the surface portion thereof, and a gate electrode 30 is dug in a low-density region. It is the same as the second embodiment except that it is connected to the surface. In the third embodiment, it is easy to increase the step difference between the gate electrode and the cathode electrode as compared with the second embodiment, and the insulation distance between the pressure contact electrode 32 on the cathode electrode and the gate electrode is increased. Is easy. The present invention is an application example to a transistor by making the anode region of the turn-off thyristor of the above embodiment the same conductivity type as the cathode region. Further, it is apparent that the pressure contact electrode can be connected to the cathode electrode shown in the above embodiment by a welding method instead of pressure contact.

【0014】[0014]

【発明の効果】以上説明したように本発明によれば、平
面ゲート構造をもつ半導体装置の単位素子を微細化した
ときのゲート・カソード間pn接合のアバランシェ耐量
の向上改善が得られる。さらに微細化された単位素子を
多数並列配置して、素子の大面積化、大電流化を図るの
が容易になること、そして圧力接触構造の適用による素
子の組立構造の簡素化、信頼生の向上および素子の両面
冷却が可能になる等の効果が得られる。
As described above, according to the present invention, it is possible to improve and improve the avalanche withstand capability of a gate-cathode pn junction when a unit element of a semiconductor device having a planar gate structure is miniaturized. Furthermore, it is easy to arrange a large number of miniaturized unit elements in parallel to increase the area and current of the element, and to simplify the assembly structure of the element by applying the pressure contact structure. It is possible to obtain effects such as improvement and cooling of both sides of the element.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1は本発明の第1の実施例におけるターンオ
フサイリスタを示す単位素子の断面説明図である。
FIG. 1 is a cross-sectional explanatory view of a unit element showing a turn-off thyristor in a first embodiment of the present invention.

【図2】図2は第1の実施例のターンオフサイリスタの
製造工程を示す単位素子の説明図である。
FIG. 2 is an explanatory diagram of a unit element showing a manufacturing process of the turn-off thyristor of the first embodiment.

【図3】図3は本発明の第2の実施例におけるターンオ
フサイリスタを示すセグメントの断面説明図である。
FIG. 3 is an explanatory cross-sectional view of a segment showing a turn-off thyristor according to a second embodiment of the present invention.

【図4】図4は本発明の第3の実施例におけるターンオ
フサイリスタを示すセグメントの断面説明図である。
FIG. 4 is a cross-sectional explanatory view of a segment showing a turn-off thyristor according to a third embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 p形アノード領域 2 n形高抵抗層 3 p形領域 4 p形低抵抗領域 5 n形カソード領域 6 p形ゲート領域 7 アノード電極 8 カソード電極 9 ゲート電極 10 絶縁膜 11 フレームゲート電極 12 絶縁材 13 フレームゲート電極 14 p形の高濃度領域 15 絶縁材 20 ゲート電極 21 カソード電極 22 圧接電極 30 ゲート電極 31 カソード電極 32 圧接電極 1 p-type anode region 2 n-type high resistance layer 3 p-type region 4 p-type low resistance region 5 n-type cathode region 6 p-type gate region 7 anode electrode 8 cathode electrode 9 gate electrode 10 insulating film 11 frame gate electrode 12 insulating material 13 Frame gate electrode 14 P-type high concentration region 15 Insulating material 20 Gate electrode 21 Cathode electrode 22 Pressure contact electrode 30 Gate electrode 31 Cathode electrode 32 Pressure contact electrode

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 平面形の相対する第1導電形のゲート領
域の間に不純物濃度がゲート領域よりも低い第1導電形
領域を設け、この第1導電形領域の表面層に第2導電形
のカソード領域が選択形成され、このカソード領域表面
にカソード電極が接続された構造を有する半導体装置に
おいて、前記カソード領域の底面に接して第1導電形の
低抵抗領域が形成され、かつ低抵抗領域の不純物濃度が
第1導電形領域よりも高く設定される事を特徴とする半
導体装置。
1. A first conductivity type region having an impurity concentration lower than that of the gate region is provided between gate regions of the first conductivity type that are opposed to each other in a plan view, and a second conductivity type is provided in a surface layer of the first conductivity type region. In a semiconductor device having a structure in which a cathode region is selectively formed and a cathode electrode is connected to the surface of the cathode region, a low resistance region of the first conductivity type is formed in contact with the bottom surface of the cathode region, and the low resistance region is formed. The impurity concentration of the semiconductor device is set higher than that of the first conductivity type region.
【請求項2】 平面形の相対する第1導電形のゲート領
域の間に不純物濃度がゲート領域よりも低い第1導電形
領域を設け、第1導電形領域の表面層に第2導電形のカ
ソード領域が選択形成された単位素子が複数個並列配置
された領域を囲んで第1導電形のフレームゲート領域が
形成され、フレームゲート領域の表面にゲート電極が接
続され、単位素子のカソード領域以外に絶縁膜が設けら
れ、カソード電極がカソード領域表面に接続されかつ絶
縁膜上に延在して設けられた構造をセグメントとなし、
該セグメントを複数個並列配置し、各セグメントのフレ
ームゲート領域及びゲート電極は連結され、かつ各セグ
メントのカソード電極は共通の圧接電極を介して圧接接
触により並列接続され、ゲート電極の一部にはゲート取
り出し電極が接続される事を特徴とする請求項1記載の
半導体装置。
2. A first conductivity type region having an impurity concentration lower than that of the gate region is provided between the gate regions of the first conductivity type that are opposed to each other in a plan view, and a surface layer of the first conductivity type region is formed of the second conductivity type. A frame gate region of the first conductivity type is formed so as to surround a region in which a plurality of unit devices in which cathode regions are selectively formed are arranged in parallel, and a gate electrode is connected to the surface of the frame gate region, except for the cathode region of the unit device. An insulating film is provided on the cathode electrode, the cathode electrode is connected to the surface of the cathode region, and the structure is provided to extend on the insulating film to form a segment,
A plurality of the segments are arranged in parallel, the frame gate region and the gate electrode of each segment are connected, and the cathode electrodes of each segment are connected in parallel by pressure contact through a common pressure contact electrode, and a part of the gate electrode is connected. The semiconductor device according to claim 1, wherein a gate extraction electrode is connected.
【請求項3】 平面形の相対する第1導電形のゲート領
域の間に不純物濃度がゲート領域よりも低い第1導電形
領域を設け、第1導電形領域の表面層に第2導電形のカ
ソード領域が選択形成された単位素子が複数個並列配置
された領域を囲んで第1導電形のフレームゲート領域が
形成され、フレームゲート領域が一部掘り込まれ、かつ
掘り込まれた表面部に第1導電形の高濃度領域が形成さ
れ、そしてゲート電極が掘り込まれた低面に接続され、
単位素子のカソード領域以外に絶縁膜が設けられ、カソ
ード電極がカソード領域表面に接続されかつ絶縁膜上に
延在して設けられた構造をセグメントとなし、該セグメ
ントを複数個並列配置し、各セグメントのフレームゲー
ト領域及びゲート電極は連結され、かつ各セグメントの
カソード電極は共通の圧接電極を介して圧接接触により
並列接続され、ゲート電極の一部にゲート取り出し電極
が接続される事を特徴とする請求項1記載の半導体装
置。
3. A first conductivity type region having an impurity concentration lower than that of the gate region is provided between gate regions of the first conductivity type that are opposed to each other in plan view, and a surface layer of the first conductivity type region is formed of the second conductivity type. A frame gate region of the first conductivity type is formed so as to surround a region in which a plurality of unit elements in which the cathode region is selectively formed are arranged in parallel, and the frame gate region is partially dug into the dug surface. A high-concentration region of the first conductivity type is formed, and a gate electrode is connected to the dug-down low surface,
An insulating film is provided in a region other than the cathode region of the unit element, and the structure in which the cathode electrode is connected to the surface of the cathode region and extends on the insulating film is a segment, and a plurality of the segments are arranged in parallel. The frame gate region and the gate electrode of the segment are connected, and the cathode electrode of each segment is connected in parallel by pressure contact through a common pressure contact electrode, and the gate extraction electrode is connected to a part of the gate electrode. The semiconductor device according to claim 1.
JP31590495A 1995-11-09 1995-11-09 Semiconductor device Withdrawn JPH09135020A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31590495A JPH09135020A (en) 1995-11-09 1995-11-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31590495A JPH09135020A (en) 1995-11-09 1995-11-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH09135020A true JPH09135020A (en) 1997-05-20

Family

ID=18071012

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31590495A Withdrawn JPH09135020A (en) 1995-11-09 1995-11-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH09135020A (en)

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