JPH09134965A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a D-channel MOSFET mounted semiconductor device, which has little fluctuation in the threshold voltage, has little irregularity in the threshold voltage and has a high-quality gate oxide film. SOLUTION: When a P-type body diffused layer 14 is formed within the region on the side of a source in an N-type drain diffused layer 2 of a D-channel MOSFET, P-type impurity ions are implanted in the layer 2 in such a way as to reach up to one part of the region under the lower part of an N<+> gate electrode 8a at a large oblique angle using a resist film 12, which is opened with a body diffused layer formation region of the D-channel MOSFET, and the electrode 8a as masks and the layer 2 is activated. After that, an N<+> source diffused layer 15 and an N<+> drain diffused layer 16 are respectively formed in the layer 14 and the layer 2. As there is no need to perform a high- temperature drive-in treatment for making the P-type impurity ions intrude into the region under the lower part of the electrode 8a, a decrease in the threshold voltage of a D-channel MOSFET mounted semiconductor device, an irregularity in the threshold voltage of the device and the deterioration of a gate oxide film of the device due to impurity diffusion from the electrode 8a can be prevented from.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a DMOS type transistor and a method of manufacturing the same, and a structure of an LSI in which a DMOS type transistor and a bipolar transistor, a CMOS type transistor and the like are integrated on the same semiconductor substrate and a method of manufacturing the same. Is.

[0002]

2. Description of the Related Art In recent years, a DMOS type transistor (Double Diffu), which is a driving device for various devices, has been developed.
There are many proposals for integrating a semiconductor device having a sed MOS transistor structure with other devices.

14 (a), 14 (b) and 15 show an example in which a semiconductor device having a DMOS structure and its manufacturing method proposed in Japanese Patent Laid-Open No. 3-155156 are integrated with a CMOS device. (A),
This will be described with reference to FIG.

First, as shown in FIG.
After the N − -type drain diffusion layer 202, the P − -type well diffusion layer 203, and the N − -type well diffusion layer 204 are formed on the P-type semiconductor substrate 200 whose main surface is the (0) plane, the surface of the semiconductor substrate 200 is selectively oxidized. The element isolation 205 is formed by the process,
A DMOSFET formation region, an NMOSFET formation region and a PMOSFET formation region are defined.

Next, as shown in FIG. 14B, a gate oxide film 207 is formed, a polycrystalline silicon film 208 is deposited by a low pressure CVD method, and a resist film (not shown) for forming a gate electrode is used. The N + type gate electrode 208a of the DMOSFET and the N + type gate electrode 20 of the NMOSFET.
8b, after forming the N + type gate electrode 208b of the PMOSFET, the resist film is removed. Next, a new resist film 209 is formed, and this resist film 209 and DM
After selectively implanting boron ions into the source formation region in the N-type drain diffusion layer 202 of the DMOSFET using the N + type gate electrode 208a of the OSFET as a mask (dotted line portion in the figure), high temperature drive-in is performed. By performing the process, the P- type body diffusion layer 214 of the DMOSFET shown in FIG. 15A is formed.

Next, as shown in FIG. 15A, using the resist film 212 as a mask, B + ions are selectively implanted only in the PMOSFET formation region to control the threshold value of the PMOSFET, and P -Type Vt control diffusion layer 213
To form

Next, as shown in FIG. 15B, the DMO
N + type source diffusion layer 215 of SFET, N + type drain diffusion layer 216, N + type source diffusion layer 2 of NMOSFET
17, N + type drain diffusion layer 218, P + type source diffusion layer 219 of PMOSFET, P + type drain diffusion layer 22
Form 0. After that, the element is completed by forming metal wiring in each part.

As described above, a composite LSI of DMOS type transistors and CMOS type transistors is manufactured.

[0009]

However, FIG.
The semiconductor device and the manufacturing method thereof as shown in FIGS. 15A and 15B and FIGS. 15A and 15B have the following problems.

(1) In the PMOSFET, after the N + type gate electrode 208c is formed, the gate electrode 208c is formed.
C, Bt ion implantation for Vt control is performed, and P
Since the − type Vt control diffusion layer 213 is formed, the variation in the depth of the P − type Vt control diffusion layer 213 becomes large.
In that case, in the case of having such a buried channel structure, the threshold value Vt greatly changes when the depth of the P − -type Vt control diffusion layer 213 changes. Therefore, PMOSF
The threshold Vt of ET is the range of the B ion implantation (R
The film quality and the film thickness of the gate electrode 208c that affect p) vary greatly. In particular, when polycrystalline silicon is used as the material for the gate electrode, it is very difficult to control the grain size and a uniform film quality cannot be formed, so that the range of the B ion implantation (Rp) varies greatly. However, there is a problem that the variation of the threshold value Vt is very large.

(2) In DMOSFET, NMOSFET and PMOSFET, each gate electrode 208a, 2a
After forming 08b and 208c, P- of DMOSFET
High temperature drive-in is performed to form the mold body diffusion layer 214. Therefore, as the element becomes finer and the gate oxide film 207 becomes thinner, the impurities in the gate electrode pass through the gate oxide film 207 and diffuse into the channel region, causing fluctuations and variations in the threshold Vt. Not only that, since impurities diffuse in the gate oxide film 207, the reliability of the gate oxide film is lowered.

In order to avoid these problems, in the conventional manufacturing process, the gate insulating film and the gate electrode have to be individually formed in the DMOSFET and the CMOSFET.
Since the polysilicon film deposition step and the patterning step are required twice, the manufacturing cost increases and the yield decreases.

The present invention has been made in view of the above circumstances, and an object thereof is to form a fine and high-performance CMOSFET or the like by forming a body diffusion layer of a DMOSFET without high-temperature drive-in diffusion. Element and DM
The present invention provides a semiconductor device that can be integrated with an OSFET on the same substrate with high reliability and at low cost, and can maintain the characteristics of each element at high performance, and a manufacturing method thereof.

[0014]

In order to achieve the above object, the present invention provides means relating to the structure of a semiconductor device according to claims 1 to 13 and a semiconductor device according to claims 14 to 29. Measures related to the manufacturing method are taken.

Specifically, the semiconductor device according to claim 1 is premised on a semiconductor device in which at least one DMISFET is mounted in an active region surrounded by element isolation in a semiconductor substrate, and the DMISFET is provided in the active region. A first impurity diffusion layer formed by introducing a low-concentration first conductivity type; a gate insulating film formed on the active region; a gate electrode formed on the gate insulating film; A source diffusion layer formed by introducing a high-concentration first-conductivity-type impurity into a region located on one side of the gate electrode in the active region, and another side of the gate electrode in the active region. A drain diffusion layer formed by introducing a high-concentration first conductivity type impurity into a region located at, and surrounded by the first impurity diffusion layer, and surrounding the source diffusion layer in the active region. A region part reaches the lower region of the serial gate electrode is formed by introducing second conductivity type impurity threshold control level, the first and the drain diffusion layer
And a second impurity diffusion layer separated by the impurity diffusion layer.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the second impurity diffusion layer is located in a region located below the source diffusion layer in the active region, as compared with the central portion. The both ends may be configured to have a profile in which the depth of penetration into the depth of the semiconductor substrate is larger.

According to a third aspect of the present invention, in the first aspect, the second impurity diffusion layer is located above the element isolation side in a region located in the active region below the source diffusion layer. The gate electrode side may be configured to have a profile in which the depth of penetration into the depth of the semiconductor substrate is larger.

When the first impurity diffusion layer is formed by introducing impurities of the first conductivity type, the first impurity diffusion layer serves as a part of the drain of the DMISFET. The region near the surface of the second impurity diffusion layer containing the second conductivity type impurity functions as the channel region of the DMISFET. When the first impurity diffusion layer is formed by introducing the second conductivity type impurity,
The first impurity diffusion layer and the second impurity diffusion layer together with the DMI
It functions as a part of the body diffusion layer of the SFET, and the region near the surface of the first impurity diffusion layer and the second impurity diffusion layer functions as the channel region. In any case, since the second impurity diffusion layer is formed in the region below the gate electrode, the high temperature for allowing the second conductivity type impurity of the second impurity diffusion layer to penetrate into the region below the gate electrode. The structure does not require drive-in processing.
Therefore, the impurities in the gate electrode of the DMISFET are prevented from entering the channel region of the DMISFET by the high temperature drive-in process, and the fluctuation and variation of the threshold value of the DMISFET and the deterioration of the reliability of the gate insulating film are prevented. It will be.

According to a fourth aspect of the present invention, in the first aspect, the second impurity diffusion layer is provided in a region of the active region below the gate electrode, and the source diffusion layer is in the active region. Can be configured so that the depth of penetration into the depth of the semiconductor substrate is smaller than that of the region located below.

With this structure, even if the impurity ions are implanted at a normal tilt angle, the second impurity diffusion layer can be obtained that has penetrated to the region immediately below the gate electrode without performing a high temperature drive-in process. become. In particular, the second
Since the impurity concentration in the portion of the impurity diffusion layer that becomes the channel region is low, the threshold value can be reduced, while
Below the source diffusion layer, the depth of the second impurity diffusion layer can be increased and the impurity concentration can be increased, so that the operation of the parasitic bipolar transistor can be suppressed.

As described in claim 5, claim 1, claim 1
2, 3, or 4, the DMISFET is formed by introducing a high-concentration second-conductivity-type impurity into a region including a part of the inner side of the second impurity diffusion layer and not including the vicinity of the surface of the active region. A third impurity diffusion layer that has been formed can be further provided.

With this structure, the second impurity diffusion layer containing the second conductivity type impurity is used as a base, the first impurity diffusion layer containing the first conductivity type impurity and the source diffusion layer are used as the emitter,
In the parasitic bipolar transistor used as the collector,
By connecting the high-concentration third impurity diffusion layer to the base region, the base resistance is reduced. Therefore, the current amplification factor of the parasitic bipolar transistor is reduced, the operation of the parasitic bipolar transistor is suppressed, and the DMIS
The withstand voltage between the source and drain of the FET is improved.

[0023] As described in claim 6, claim 1,
2, 3 or 4, the first impurity diffusion layer is
It may be formed by introducing conductivity type impurities so that at least the first and second impurity diffusion layers function as body diffusion layers.

With this configuration, the parasitic capacitance of the first conductivity type drain diffusion layer of the DMISFET is reduced, so that D
The operation speed of the MISFET is increased. Further, if the impurity concentration of the second impurity diffusion layer is made higher than that of the first impurity diffusion layer, high breakdown voltage characteristics can be obtained.

As described in claim 7, in the semiconductor device of claim 1, a protective film formed on the gate electrode and having a function of blocking the passage of impurity ions can be further provided.

According to this structure, when the second conductivity type impurity ions are implanted to form the second impurity diffusion layer, the second conductivity type impurity ions pass from the side surface of the gate electrode and the region below the gate electrode. While reaching a portion of the gate electrode on the source side that is laterally invaded to some extent, invasion of the second conductivity type impurity ions from the upper surface of the gate electrode is almost blocked. Therefore, the position and length of the channel region formed near the surface of the second impurity diffusion layer are optimized.

As described in claim 8, claim 1,
2, 3 or 4, the first and second MISFETs having the first and second conductivity type channel structures respectively formed in the second and third active regions surrounded by the element isolation in the semiconductor substrate. Further provided, the first MISFET
A gate insulating film formed on the second active region, a gate electrode formed on the gate insulating film,
The second MISFET is formed of a source / drain diffusion layer formed by introducing a first conductivity type impurity into regions located on both sides of the gate electrode in the second active region. A gate insulating film formed on the third active region, a gate electrode formed on the gate insulating film, and a second region formed on both sides of the gate electrode in the third active region. It can be configured by a source / drain diffusion layer formed by introducing a conductivity type impurity.

With this structure, the high temperature drive-in process is not required when forming the second impurity diffusion layer of the DMISFET, so that each MISF of the CMISFET is formed.
The structure allows the implantation of ET threshold control impurities before the gate electrode is formed. Therefore, CMIS
It is no longer necessary to implant the impurity ions for controlling the threshold value through the gate electrode when forming the FET, and a semiconductor device equipped with a CMISFET in which the variation in the threshold value due to the variation in the flight distance of the impurity ions is small is obtained. Will be done.

A semiconductor device according to a ninth aspect is the semiconductor device according to the eighth aspect, wherein the gate insulating film and the gate electrode of the first and second MISFETs are made of the same material as the gate insulating film and the gate electrode of the DMISFET. It has the same thickness.

With this structure, it is possible to form the gate insulating film and the gate electrode of the DMISFET and CMISFET, which are conventionally formed in separate steps, by the same film deposition and patterning steps, which reduces the cost. And the yield can be improved.

A semiconductor device according to a tenth aspect is premised on a semiconductor device in which at least one DMISFET is mounted in an active region surrounded by element isolation in a semiconductor substrate, and the DMISFET has a low concentration in the active region. A first impurity diffusion layer formed by introducing a first conductivity type impurity or a second conductivity type impurity, a gate insulating film formed on the active region, and a gate formed on the gate insulating film. A high-concentration first-conductivity-type impurity is introduced into the electrode, the insulator sidewalls formed on both side surfaces of the gate electrode, and the region located on one side of the gate electrode in the active region. The position of the end portion on the side of the gate electrode that is formed is defined by the source diffusion layer defined by the insulator sidewall and the region located on the other side of the gate electrode in the active region. Part of a region below the gate electrode that surrounds the source diffusion layer in the active region and a drain diffusion layer that is formed by introducing a first conductivity type impurity and that is surrounded by the first impurity diffusion layer. A second impurity diffusion layer, which is formed by introducing a second conductivity type impurity having a threshold control level into a region reaching the gate electrode, and whose end portion on the gate electrode side is defined by the end portion on the source side of the gate electrode. ing.

As described in claim 11, claim 1
0, the second impurity diffusion layer has a profile in which, in a region located below the source diffusion layer in the active region, the depth of penetration into the depth of the semiconductor substrate increases toward the center. can do.

According to the structure of claim 10 or 11, the portion which becomes the channel region of the second impurity diffusion layer, that is, from the end portion of the source diffusion layer on the gate electrode side to the end portion of the second impurity diffusion layer on the gate electrode side. The length of the region is defined by the thickness of the sidewall. Therefore, the threshold value can be controlled without performing the high temperature drive-in process, so that the impurities in the gate electrode of the DMISFET can be prevented from entering the channel region of the DMISFET by the high temperature drive-in process. , DMISFET threshold fluctuations and variations, and reduction in reliability of the gate insulating film are prevented. Moreover, since the structure is such that it is not necessary to perform ion implantation with a large inclination angle when performing ion implantation,
Since the impurity concentration near the surface of the second impurity diffusion layer, which becomes the channel region, can be reduced and the impurity concentration in the back of the substrate can be increased, the operation of the parasitic bipolar transistor can be suppressed.

As described in claim 12, claim 1
0, the third DMISFET is formed by introducing a high-concentration first-conductivity-type impurity into a region including a part of the inner side of the second impurity diffusion layer and not including the vicinity of the surface of the active region. The impurity diffusion layer of can be further provided.

With this configuration, the same effect as that of claim 5 can be exerted.

As described in claim 13, claim 1
0, the first and second MISFE having first and second conductivity type channel structures respectively formed in second and third active regions surrounded by the element isolation in the semiconductor substrate.
T is further provided, and the first MISFET is connected to the second MISFET.
A gate insulating film formed on the active region, a gate electrode formed on the gate insulating film, insulator sidewalls formed on both side surfaces of the gate electrode, and the second active region. Formed by introducing impurities of the first conductivity type into regions located on both sides of the gate electrode inside, and the gate electrode side end portion is constituted by a source / drain diffusion layer defined by the insulator sidewall, The second MIS
An FET, a gate insulating film formed on the third active region, a gate electrode formed on the gate insulating film, and insulator sidewalls formed on both side surfaces of the gate electrode, Source / drain diffusions, which are formed by introducing impurities of the second conductivity type into regions located on both sides of the gate electrode in the third active region and whose gate electrode side ends are defined by the insulator sidewalls. And layers.

As described in claim 14, claim 1
3, the gate insulating film and the gate electrode of the first and second MISFETs can be made of the same material and have the same thickness as the gate insulating film and the gate electrode of the DMISFET.

With this configuration, the same effect as that of the ninth aspect can be obtained.

As described in claim 15, claim 1
3, the source of the MISFET is provided in the active region of at least one of the second and third active regions, between the region located under the gate electrode and the source / drain diffusion layer. It is preferable to provide a low-concentration source / drain diffusion layer formed by introducing a low-concentration impurity having the same conductivity type as that of the impurity introduced in the drain diffusion layer.

With this structure, a semiconductor device having a high drain breakdown voltage and suitable for a fine structure can be obtained.

A method of manufacturing a semiconductor device according to a sixteenth aspect is premised on a method of manufacturing a semiconductor device in which at least one DMISFET is mounted in an active region surrounded by element isolation in the semiconductor substrate. A first step of forming an element isolation for partitioning the element, and introducing a first conductivity type impurity or a second conductivity type impurity into the active region,
The second step of forming the first impurity diffusion layer, the third step of forming the gate insulating film and the gate electrode of the DMISFET on the active region, and the source side region of the active region are opened. Ions of the second conductivity type impurity are implanted into the active region by using the mask member, and a second region extending from a region located below the element isolation in the active region to a region located below the gate electrode is formed. And a fourth step of forming an impurity diffusion layer in the active region located on both sides of the gate electrode using the gate electrode as a mask.
A drain diffusion layer of a DMISFET surrounded by the first impurity diffusion layer and ion-implanted with conductive impurity ions, and a DMI surrounded by the second impurity diffusion layer.
And a fifth step of forming a source diffusion layer of the SFET.

As described in claim 17, claim 1
In the sixth step, in the fourth step, the gate electrode is also used as a mask, and at least one direction including a direction inclined toward a side facing the gate electrode with respect to an axis perpendicular to the surface of the semiconductor substrate Implanting ions of two-conductivity type impurities to form the second impurity diffusion layer so that the source region side end of the second impurity diffusion layer is defined by the source side end of the gate electrode. You can

As described in claim 18, claim 1
In the seventh step, it is preferable that in the fourth step, the ions of the second conductivity type impurity are implanted from a direction in which an inclination angle with respect to an axis perpendicular to the surface of the semiconductor substrate is 10 ° or more and 45 ° or less.

As described in claim 19, claim 1
7, in the fourth step, the ion of the second conductivity type impurity also includes a direction inclined to the gate electrode side.
Direction, and from a direction inclined at a large angle with respect to an axis perpendicular to the surface of the semiconductor substrate, and implanting the second impurity diffusion layer in a region located below the source diffusion layer in the active region, It is possible to form such that both end portions have a profile in which the depth of penetration into the depth of the semiconductor substrate is larger than that in the central portion.

As described in claim 20, claim 1
7, in the fourth step, the ion of the second conductivity type impurity also includes a direction inclined to the gate electrode side.
Direction and a large amount of energy is injected from a direction inclined at a small angle with respect to an axis perpendicular to the semiconductor substrate surface to position the second impurity diffusion layer below the source diffusion layer in the active region. In the region to be formed, the central portion can be formed to have a profile in which the depth of penetration into the depth of the semiconductor substrate is larger than that at both ends.

As described in claim 21, claim 2
In the fourth step, it is preferable that in the fourth step, the inclination angle with respect to the axis perpendicular to the surface of the semiconductor substrate in the direction in which the ion implantation of the second conductivity type impurity is performed is 30 ° or less.

As described in claim 22, claim 1
7, in the fourth step, ions of the second conductivity type impurity are implanted only from a direction inclined to the side facing the gate electrode, and the second impurity diffusion layer is formed into the source in the active region. In the region located below the diffusion layer, the gate electrode side can be formed to have a profile that the depth of penetration into the depth of the semiconductor substrate is larger than that of the element isolation side.

According to the method of claims 17 to 22, the second impurity diffusion layer of the DMISFET to be formed is formed only by implanting the first conductivity type impurity ions and activating them, without performing the high temperature drive-in process. So DMISFET
Impurities are prevented from diffusing from the gate electrode to the channel region. Therefore, the DMISF with a small fluctuation or variation in the threshold value and a highly reliable gate insulating film is provided.
ET will be formed.

As described in claim 23, claim 1
7, in the third step, after the insulating film and the conductive film are sequentially deposited, a first resist film that covers a gate electrode formation region is formed on the conductive film, and the first resist film is formed. The conductive film below the opening is selectively removed, and in the fourth step, a second region in which a source side region of the active region is opened is formed on the first resist film.
The resist film can be formed and the first and second resist films can be used as the mask member.

By this method, by using the resist film used for forming the gate electrode of the DMISFET, impurity ions on the upper surface side of the gate electrode with respect to the second conductivity type impurity for forming the second impurity diffusion layer are removed. It is possible to increase the blocking function.

As described in claim 24, claim 1
7, the step of forming a protective film having a function of blocking passage of the second conductivity type impurity ions on the gate electrode can be further provided before the fourth step.

According to the method of claim 23 or 24, the DMI
The function of blocking impurity ions in the gate electrode region of the SFET is enhanced.

As described in claim 25, claim 1
6, in the third step, the gate electrode is formed to have a thickness that allows ions of the second conductivity type impurity in the fourth step to pass therethrough, and in the fourth step, the fourth step is performed. A profile in which two-conductivity-type impurities are implanted so as to pass through the gate electrode, and the second impurity diffusion layer has a shallow depth in the depth of the substrate in a region located below the gate electrode in the active region. Can be formed.

By this method, the second conductivity type impurities can be made to penetrate into the region below the gate electrode without performing a high temperature drive-in process. In particular, since the impurity concentration is low in the portion of the second impurity diffusion layer that becomes the channel region, the threshold value can be reduced, while the depth of the second impurity diffusion layer is increased below the source diffusion layer. And since it is possible to increase the impurity concentration,
The operation of the parasitic bipolar transistor can be suppressed.

As described in claim 26, claim 1
6, after the fourth step, ions of a second conductivity type impurity are implanted into the active region using a mask common to the mask used in the fourth step, and at least the second impurity diffusion is performed. A step of forming a third impurity diffusion layer containing a high concentration of the second conductivity type impurity can be further provided in a region including a part of the inside of the layer and away from the surface of the active region.

By this method, since the high-concentration third impurity diffusion layer connected to a part of the second impurity diffusion layer is formed, the second impurity diffusion layer, the source diffusion layer, and the first impurity diffusion layer are formed. The base resistance of the parasitic bipolar transistor generated between the diffusion layers is reduced, and the operation of the parasitic bipolar transistor is suppressed. Therefore, a DMISFET having a high source-drain breakdown voltage is formed. Moreover, since the large-angle ion implantation for forming the second impurity diffusion layer is performed first, the semiconductor substrate is made amorphous to some extent, and in that state, the third impurity diffusion layer is formed. Since ion implantation is performed,
Even if ion implantation is performed at an angle close to 0 °, channeling can be reliably prevented. Therefore, the third impurity diffusion layer having a regular shape can be formed, and variation in threshold value can be suppressed.

As described in claim 27, claim 1
6, in the second step, a second conductivity type impurity is injected into the active region, and the second impurity diffusion layer and the second impurity diffusion layer function as a body diffusion layer of the DMISFET.
The impurity diffusion layer can be formed.

By this method, the parasitic capacitance of the first conductivity type drain diffusion layer of the DMISFET is reduced, so that the DMISFET having a high operating speed is formed. Also, the second
If the impurity concentration of the impurity diffusion layer is higher than that of the first impurity diffusion layer, DM having high withstand voltage characteristics is obtained.
ISFET can be obtained.

As described in claim 27, claim 1
6, in the first step, the second and third MISFETs for forming the first and second MISFETs surrounded by the element isolation and having the first and second conductivity type channel structures are formed on the semiconductor substrate. Further forming an active region of the above, and prior to the third step, individually implanting the threshold controlling impurities of the first and second MISFETs into the second and third active areas. Further, in the third step, the second step
And a gate insulating film and a gate electrode are formed also on the third active region, and in the fifth step, the first MISF is formed.
A step of forming a source / drain diffusion layer of ET and forming a source / drain diffusion layer of the second MISFET can be further provided.

According to this method, the threshold control impurity ions are implanted in the CMISFET before the gate electrode is formed. Therefore, when the threshold control impurity ions are implanted through the CMISFET gate electrode. Due to variations in flight distance such as
Variations and variations in the ET threshold are prevented.

A method of manufacturing a semiconductor device according to a twenty-ninth aspect is premised on a method of manufacturing a semiconductor device in which at least one DMISFET is mounted in an active region surrounded by element isolation in the semiconductor substrate. A first step of forming an element isolation for partitioning the element, and introducing a first conductivity type impurity or a second conductivity type impurity into the active region,
The second step of forming the first impurity diffusion layer, the third step of forming the gate insulating film and the gate electrode of the DMISFET on the active region, and the source side region of the active region are opened. Using the mask member and the gate electrode as a mask, ions of the second conductivity type impurity are implanted into the active region from a direction having a small inclination angle with respect to a direction perpendicular to the surface of the semiconductor substrate to form a source side region of the active region. A fourth step of forming therein a second impurity diffusion layer extending from a region located below the element isolation end to a region located below the gate electrode end in the active region; A fifth step of forming an insulator sidewall on both side surfaces of the electrode, and using the gate electrode and the insulator sidewall as a mask to form an active region on both sides of the gate electrode. By implanting the first conductivity type impurity ions, DMI surrounded by the first impurity diffusion layer
A sixth step of forming a drain diffusion layer of the SFET and a source diffusion layer of the DMISFET surrounded by the second impurity diffusion layer is provided.

By this method, even if the second conductivity type impurity in the second impurity diffusion layer does not penetrate to the vicinity of the center of the lower region of the gate electrode by the high temperature drive-in process, the channel of the second impurity diffusion layer is formed. Since the length of the portion to be the region is determined by the thickness of the sidewall, it becomes easy to control the threshold value. Moreover, since the second impurity diffusion layer is formed by ion implantation with a small tilt angle, the implantation energy is adjusted to reduce the impurity concentration in the vicinity of the surface of the second impurity diffusion layer, which will be the channel region, to reduce the threshold value. It is possible to suppress the operation of the parasitic bipolar transistor by increasing the impurity concentration in the region behind the substrate while lowering it.

As described in claim 30, claim 2
9. In the fourth step, the first step is performed from the direction in which the inclination angle with respect to the axis perpendicular to the semiconductor substrate surface is 30 ° or less.
Ions of conductive impurities can be implanted.

As described in claim 31, claim 2
9, in the first step, second and third MISFETs for forming first and second MISFETs surrounded by the element isolation and having first and second conductivity type channel structures are formed on the semiconductor substrate. Further forming an active region of the MISFET, and before the third step, a step of individually implanting the threshold controlling impurities of the first and second MISFETs into the second and third active areas. In the third step, the gate insulating film and the gate electrode are formed also on the second and third active regions, and in the fifth step, the first and second MISs are formed.
Insulator sidewalls are formed on both side surfaces of the gate electrode of the FET, and in the sixth step, the first MISF is formed.
A step of forming a source / drain diffusion layer of ET and forming a source / drain diffusion layer of the second MISFET can be further provided.

According to this method, in the CMISFET, the threshold control impurity ions are implanted before the gate electrode is formed, so that the threshold control impurity ions are implanted through the gate electrode. This prevents variations and variations in the threshold value of the CMISFET due to variations in the flight distance.

As described in claim 32, claim 3
0, after the third step and before the fifth step, at least one of the second and third active regions has a low concentration of the first conductivity type impurity using the gate electrode as a mask. It is possible to further provide a step of implanting the above ions to form a low concentration source / drain diffusion layer.

By this method, the MISFET suitable for miniaturization can be formed while adapting the manufacturing process of the DMISFET to the manufacturing process of the CMISFET having a so-called LDD structure.

[0068]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) First, a first embodiment will be described. 1 (a) to 1 (c) and 2 (a) to 2 (c)
FIG. 6A is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment.

As shown in FIG. 1A, for example, a resist mask is formed on a P-type semiconductor substrate 1 made of a silicon single crystal having a (100) plane having a specific resistance of 10 to 20 Ω · cm as a main surface, Using this, DM of the P-type semiconductor substrate 1
Phosphorus ions, for example, are implanted into the OSFET formation region and the PMOSFET formation region under the conditions that the implantation energy is 120 keV and the dose amount is 8 × 10 ¹² cm ⁻² , and another resist mask is further formed to form the NMOSFET formation region.
After implanting boron ions under the conditions of an implantation energy of 30 keV and a dose of about 1 × 10 ¹³ cm ^-2 , 1100
Heat treatment is performed at 100 ° C. for about 100 minutes. This allows the DMO
N- type drain diffusion layer 2 which is the first impurity diffusion layer of SFET, P- type well diffusion layer 3 of NMOSFET, PM
The N-type well diffusion layer 4 of the OSFET is formed.

Next, as shown in FIG. 1B, for example, 9
After oxidation is performed at a temperature of about 00 ° C. to form an oxide film having a thickness of about 20 nm, low pressure CVD at, for example, 760 ° C.
Forming a nitride film with a thickness of about 160 nm. next,
For example, using a resist film as a mask, DMOSFE
The nitride film other than the T formation region, the NMOSFET formation region, and the PMOS formation region is removed by, for example, dry etching, and thereafter, by a selective oxidation method at 1000 ° C., for example.
The element isolation 5 made of a silicon oxide film is formed with a thickness of about 500 nm.

Next, as shown in FIG. 1C, for example, using a resist film as a mask, B for controlling a threshold value (hereinafter, simply referred to as Vt) is formed in the PMOSFET forming region.
F2 ions are implanted under the conditions of about 50 keV and 2 × 10 ¹² cm ⁻² to form a P− type Vt control diffusion layer 6, for example, 9
After the gate oxide film 7 having a thickness of about 15 nm is formed by performing oxidation at 00 ° C., a polycrystalline silicon film 8 having a thickness of about 300 nm is formed by low pressure CVD at 630 ° C., for example. Next, after the polycrystalline silicon film 8 is converted to N + by POCl ₃ vapor phase diffusion at 900 ° C. for about 30 minutes, the DMOS is formed.
For example, a resist film 9 for forming a gate electrode is formed in the gate electrode forming region of the FET, NMOSFET, PMOSFET by a photolithography process.

Next, as shown in FIG. 2A, the polycrystalline silicon film 8 is patterned by dry etching using the resist film 9 for forming a gate electrode as a mask, and the N + type gate electrode 8a of the DMOSFET is formed. , NMO
N + type gate electrode 8b of SFET, N of PMOSFET
A + type gate electrode 8c is formed. Next, for example, DMOS
The resist film 12 and D having an opening in the source formation region of the FET
Using the N + type gate electrode 8a of the MOSFET as a mask,
Into the body diffusion layer forming region of the DMOSFET, boron ions are implanted in two steps from two directions forming an angle of 180 ° with each other in plan view. At that time, for example, 120k
eV, under the condition of 4 × 10 ¹³ cm ⁻² , for example, the implantation angle is 30 ° with respect to the axis perpendicular to the surface of the P-type semiconductor substrate 1, that is, the N + -type gate electrode 8a of the DMOSFET.
The first boron ion implantation is performed so that the boron ions will invade approximately the half of the source side of the lower region. Further, the semiconductor substrate 1 is rotated 180 degrees, and D
The second boron ion implantation is performed at an inclination angle of 30 ° so that the boron ions penetrate below the edge of the element isolation 5 in the MOSFET formation region.

Next, as shown in FIG. 2B, the resist film 12 is removed and heat treatment is performed at, for example, 850 ° C. for about 30 minutes to form a P − -type second impurity diffusion layer of the DMOSFET. The body diffusion layer 14 is formed.

Next, as shown in FIG. 2C, the DMOSFET forming region, N
Arsenic ions, for example, are added to the MOSFET formation region at 40 ke
V, 4 × 10 ¹⁵ cm ⁻² , and then P
In the MOSFET formation region, for example, BF2 is 40 keV, 3
Implantation is performed under the condition of about 10 ¹⁵ cm ^-2 , for example, 850 ° C.,
By performing heat treatment for about 60 minutes, DMOSFE
N + type source diffusion layer 15 of T and channel region Rchan,
N + type drain diffusion layer 16, N + type source diffusion layer 17 of NMOSFET, N + type drain diffusion layer 18, PMOS
A P + type source diffusion layer 19 and a P + type drain diffusion layer 20 of the FET are formed.

Although not shown in the drawings of this embodiment, thereafter, an NSG film of about 800 nm is formed as an interlayer insulating film by using, for example, a low pressure CVD method, and thereafter, NSG film is formed by using, for example, a resist film as a mask. The film is etched by dry etching to form a contact hole. Finally, an Al film is formed by a sputtering method, for example, as a metal wiring, and thereafter, the Al film is etched using, for example, a resist film as a mask to form an Al wiring, whereby the semiconductor device is completed.

As described above, according to this embodiment, DM
In order to form the P-type body diffusion layer 14 and the channel region Rchan of the OSFET, the resist film 12 and the DMO are formed.
When implanting boron using the N + type gate electrode 8a of the SFET as a mask, the implantation angle is 30 ° with respect to the axis perpendicular to the surface of the P type semiconductor substrate 1, and the DMOSFET is used.
Boron ions are implanted at such an angle that boron ions enter the side surface of the N + type gate electrode 8a on the side of the source region which is not covered with the resist film 12. And
Then, by performing a low temperature activation heat treatment, DM
P-type body diffusion layer 14 of OSFET and DMOSF
The channel region Rchan of ET is formed.

DMOSFETs and NMs having the above structure
By forming a semiconductor device having an OSFET and a PMOSFET, the following effects can be obtained.

The P-type body diffusion layer 14 of the DMOSFET transistor and the channel region R of the DMOSFET.
In forming chan, as described above, the ions are implanted into the P- type body diffusion layer 14 at a large inclination angle. Therefore, in the conventional method, when the channel region is formed under the gate electrode of the DMOSFET, the high temperature drive-in which is performed to sufficiently diffuse the body diffusion layer in the lateral direction in the P-type semiconductor substrate 1 is not necessary. I'm done. That is, by setting the ion implantation angle to a large tilt angle, it is possible to secure a sufficient lateral range in the P-type semiconductor substrate.
This is because the die body diffusion layer 14 can be sufficiently expanded in the lateral direction in the semiconductor substrate, and the channel region Rchan can be easily formed under the gate electrode.

From the above, the above problems (1) to
(3) can be solved as follows.

-For Problem (1) -In incorporating DMOSFET formation in a CMOS process, DMOSFET, NMOSFET, PMOS
Since the high temperature drive-in process becomes unnecessary after the gate electrode of the FET is formed, PMOSFET, NMOSFE
Before forming the gate electrode of T, for example, before forming the gate oxide film, Vt of PMOSFET and NMOSFET
Controlling ion implantation can be performed. Therefore, after the gate electrode is formed, the NMOSFET is passed through the gate electrode.
Since it is not necessary to perform ion implantation for Vt control of the PMOSFET, it is possible to completely eliminate the influence on Vt control due to variations in film quality and flight distance of ions of the gate electrode whose film thickness is difficult to control. Therefore, DMO on CMOS device
NMOSF with little Vt variation even with SFET
ET and PMOSFET can be formed.

-To the problem (2) -In incorporating the DMOSFET formation in the CMOS process, since the heat treatment for the high temperature drive-in process is not required after the gate electrode of each FET is formed, Highly doped impurities do not diffuse into the gate oxide film of each FET due to the heat treatment. Therefore, a highly reliable gate oxide film can be realized.

(Second Embodiment) FIGS. 3A to 3C.
FIG. 6A is a sectional view showing a manufacturing process for a semiconductor device according to a second embodiment of the present invention. However, steps before the step shown in FIG. 3A are the same as the steps shown in FIGS. 1A to 1C and FIG. 2A described in the first embodiment. That is, before the step shown in FIG. 3A, the resist film 12 is formed, and the resist film 12 and DMOSFE are formed.
Using the N + type gate electrode 8a of T as a mask, the DMOS
Into the body diffusion layer forming region of the FET, boron ions are implanted in two steps from two directions forming an angle of 180 ° with each other in plan view. At that time, for example, 120 keV, 4
Under the condition of × 10 ¹³ cm ⁻² , for example, the implantation angle is 30 ° with respect to the axis perpendicular to the surface of the P-type semiconductor substrate 1,
In addition, the first boron ion implantation is performed so that the boron ions penetrate into a region of about half of the source side of the lower region of the N + type gate electrode 8a of the DMOSFET. Further, the semiconductor substrate 1 is rotated 180 degrees to
The second boron ion implantation is performed at an inclination angle of 30 ° so that the boron ions penetrate below the edge of the element isolation 5 in the T formation region.

Next, as shown in FIG. 3A, again using the resist film 12 and the N + type gate electrode 8a of the DMOSFET as a mask, the body diffusion layer forming region of the DMOSFET is shown in FIG. 2A. The acceleration energy of boron ion implantation in the process becomes high acceleration energy 150
keV, 1 × 10 ¹⁴ cm ⁻² , with an implantation angle smaller than that of boron ion implantation shown in FIG. 2A, for example, 0 ° with respect to an axis perpendicular to the surface of the P-type semiconductor substrate 1. Boron ions are implanted at such an angle.

The P + type body embedded diffusion layer 32
Before performing the ion implantation for forming, the ions in the oblique direction for forming the P- body diffusion layer 14 are first performed, so that the crystals in the semiconductor substrate are made amorphous to some extent. Then, since ion implantation is performed in the vertical direction in that state, it is possible to reliably prevent channeling during ion implantation. Therefore, the P + type body-embedded diffusion layer 32 does not have an irregular shape.

Next, as shown in FIG. 3B, the resist film 12 is removed, and heat treatment is performed, for example, at 850 ° C. for about 30 minutes, so that the P − -type body diffusion layer 14 of the DMOSFET and the channel of the DMOSFET are formed. A region Rchan and a P + type body buried diffusion layer 32 which is a third impurity diffusion layer are formed. In this case, the lateral end of the P + type body buried diffusion layer 32 exists near the edge on the source side of the N + type gate electrode 8a of the DMOSFET. The depth of the P + type body diffusion layer 32 is deeper than that of the P− type body diffusion layer 14 and penetrates into the semiconductor substrate 1, and the DMOS of the P− type body diffusion layer 14 is formed.
The surface concentration just below the N + type gate electrode 8a of the FET is hardly influenced. Therefore, DMO
The Vt of the SFET is the P + type body buried diffusion layer 32.
It is determined only by the P- type body diffusion layer 14 without being affected by the above.

Next, as shown in FIG. 3C, the DMOSFET formation region, N
Arsenic ions, for example, are added to the MOSFET formation region at 40 ke
V, 4 × 10 ¹⁵ cm ⁻² , and then P
For example, BF2 ions of 40 ke are formed in the MOSFET formation region.
^{Implanted under} the conditions of V, 3 × 10 ¹⁵ cm ⁻² , for example, 85
By performing heat treatment at 0 ° C for about 60 minutes, DMO
SFET N + type source diffusion layer 15, N + type drain diffusion layer 16, NMOSFET N + type source diffusion layer 17,
An N + type drain diffusion layer 18, a P + type source diffusion layer 19 and a P + type drain diffusion layer 20 of a PMOSFET are formed.

Although not shown in the drawings of this embodiment, an NSG film having a thickness of about 800 nm is then formed as an interlayer insulating film by using, for example, a low pressure CVD method, and thereafter, an NSG film is formed by using, for example, a resist film as a mask. The film is etched by dry etching to form a contact hole. Finally, an Al film is formed by a sputtering method, for example, as a metal wiring, and thereafter, the Al film is etched using, for example, a resist film as a mask to form an Al wiring, whereby the semiconductor device is completed.

Also in this embodiment, although not shown, in the step corresponding to the step shown in FIG. 2A, the implantation angle is 30 ° with respect to the normal to the P-type semiconductor substrate 1, Further, boron ions are implanted at such an angle that boron ions enter the side surface of the D + N-type gate electrode 8a on the side of the source region which is not covered with the resist film 12, so that the P- type body diffusion layer 14 of the DMOSFET is formed.
And the channel region Rchan are formed, the above first
It is possible to obtain the same effect as that of the embodiment.

Then, a low-temperature activation heat treatment is performed thereafter, whereby the P- type body diffusion layer 14 of the DMOSFET and the channel regions Rchan and P + of the DMOSFET.
A mold body embedded diffusion layer 32 is formed.

As described above, below the P- type body diffusion layer 14 of the DMOSFET, the P + type body buried diffusion layer 32 which is the third impurity diffusion layer containing a higher concentration of P type impurities is formed. Therefore, the resistance of the entire body diffusion layer can be lowered. Therefore, DMOSFET
Even if the surface concentration of the P- type body diffusion layer 14 is lowered and the threshold voltage is lowered in order to improve the performance of the P-type body diffusion layer 14, since the high concentration P + type body embedded diffusion layer 32 exists, the resistance of the entire body diffusion layer 14 is reduced. Is kept low. And
Since the resistance of the entire body diffusion layer 14 becomes low, D
The fluctuation of the threshold voltage due to the rise of the potential of the body terminal due to the substrate current of the MOSFET is suppressed. Especially,
Even if a parasitic bipolar NPN transistor having the body diffusion layer 14 as the base, the N + type source diffusion layer 15 as the emitter, and the N − type drain diffusion layer 2 as the collector is generated, the impurity concentration of the portion corresponding to the base is Since the concentration is high, the resistance is low, so that the operation of the transistor can be suppressed. That is, the withstand voltage between the source and the drain is improved.

In addition, in this embodiment, the P − type body diffusion layer 1 is formed by performing the ion implantation with the large inclination angle of 30 °.
4 and the channel region Rchan are formed, the resist film 12 and the N + type gate electrode 8a of the DMOSFET are again used as a mask to form the P + type body buried diffusion layer 32 in the body diffusion layer forming region of the DMOSFET. The boron ions are implanted at a higher acceleration energy than that of the boron ions and at an implantation angle of 0 ° with respect to the normal to the P-type semiconductor substrate 1. Therefore,
Since the inside of the semiconductor substrate is made amorphous to some extent by the initial large-angle ion implantation, even if ion implantation is performed thereafter to form the P + -type body-embedded diffusion layer 32 from the vertical direction, channeling hardly occurs. A random impurity distribution is not caused by the subsequent impurity diffusion process. That is, variations in withstand voltage characteristics and electrical characteristics are not caused. On the other hand, before the ion implantation with a large inclination angle, the P + type body embedded diffusion layer 3 is formed.
In the case of performing ion implantation from the vertical direction for forming 2, the impurities are irregularly distributed in the semiconductor substrate due to channeling, and the irregularly distributed impurities are further diffused in the semiconductor substrate. Therefore, there is a possibility that there may be a problem that variations in electrical characteristics such as breakdown voltage become large.

Since the ion implantation for forming the P- type body diffusion layer 14 and the P + type body buried diffusion layer 32 is performed using the same mask, the ion implantation step is added once. This is all that is needed and there is only a small increase in cost to obtain this effect.

(Third Embodiment) Next, a third embodiment will be described. 4 (a), (b) and FIG.
(A), (b) is sectional drawing which shows the manufacturing process of the semiconductor device in 3rd Embodiment. However, steps before the step shown in FIG. 4C are almost the same as the steps shown in FIGS. 1A to 1C described in the first embodiment. However, in the present embodiment, before the step shown in FIG. 4A, a new resist film 12 is further formed on the resist film 9 for forming the gate electrode without removing it, and the resist films 9 and 12 are formed. Using the N + type gate electrode 8a of the DMOSFET as a mask, boron ion is implanted into the body diffusion layer forming region of the DMOSFET in two steps from two directions forming an angle of 180 ° with each other in plan view. At that time, for example, under the conditions of 120 keV and 4 × 10 ¹³ cm ⁻² , for example, the implantation angle is 30 ° with respect to the axis perpendicular to the surface of the P-type semiconductor substrate 1, and the DMOSFE is used.
The first boron ion implantation is performed so that the boron ions will penetrate into a region of approximately half of the source side of the lower region of the N + type gate electrode 8a of T. Furthermore, the semiconductor substrate 1
Is rotated by 180 degrees, and the second boron ion implantation is performed at an inclination angle of 30 ° so that boron ions penetrate below the end of the element isolation 5 in the DMOSFET formation region.

Next, as shown in FIG. 4B, again using the resist films 9 and 12 and the N + type gate electrode 8a of the DMOSFET as a mask, a body diffusion layer forming region of the DMOSFET is formed with boron, for example. The acceleration energy is higher than that of boron ion implantation in the step 10
Under the conditions of 50 keV and 1 × 10 ¹⁴ cm ^-2 , and as shown in FIG.
The boron ions are implanted under the condition that the implantation angle is smaller than that in the step 0, for example, the implantation angle is 0 ° with respect to the axis perpendicular to the surface of the P-type semiconductor substrate 1.

Next, as shown in FIG. 5A, the resist films 9 and 12 are removed, and heat treatment is performed at, for example, 850 ° C. for about 30 minutes, whereby the P--type body diffusion layer 14 of the DMOSFET, Channel region Rch of DMOSFET
An an and P + type body embedded diffusion layer 32 is formed.
In this case, the lateral end of the P + type body buried diffusion layer 32 exists near the source side edge of the N + type gate electrode 8a of the DMOSFET. In addition, the depth of the P + type body buried diffusion layer 32 is deeper than the P− type body diffusion layer 14 into the semiconductor substrate 1, and the P + type body diffusion layer 14 is directly under the N + type gate electrode 8a of the DMOSFET. It is designed to have almost no effect on the surface concentration. Therefore, Vt of DMOSFET is P +
It is determined only by the P − type body diffusion layer 14 without being affected by the type body embedded diffusion layer 32.

Next, as shown in FIG. 5B, for example, using the resist film as a mask, the DMOSFET and the NMOSF are formed.
Arsenic ions, for example, in the ET formation region at 40 keV, 4 × 1
Implanted under the condition of 0 ¹⁵ cm ^-2 , and further
For example, BF2 ions are added to the T formation region at 40 keV, 3 × 1
Implantation is carried out under the condition of about 0 ¹⁵ cm ^-2 , for example, 850 ° C.
By performing a heat treatment for about 10 minutes, the N + type source diffusion layer 15, the N + type drain diffusion layer 16 of the DMOSFET,
The N + type source diffusion layer 17 and the N + type drain diffusion layer 18 of the NMOSFET, the P + type source diffusion layer 19 and the P + type drain diffusion layer 20 of the PMOSFET are formed.

Although not shown in the drawings of this embodiment, an NSG film having a thickness of about 800 nm is then formed as an interlayer insulating film by using, for example, a low pressure CVD method, and then, an NSG film is formed by using, for example, a resist film as a mask. The film is etched by dry etching to form a contact hole. Finally, an Al film is formed by a sputtering method, for example, as a metal wiring, and thereafter, the Al film is etched using, for example, a resist film as a mask to form an Al wiring, whereby the semiconductor device is completed.

In this embodiment, in order to form the P--type body diffusion layer 14 and the channel region Rchan of the DMOSFET, the tilt angle and the acceleration energy when implanting boron ions are the same as those in the second embodiment. ,afterwards,
Since the formation of the P + type body diffusion burying layer 32 is also the same as that of the second embodiment, the same effect as that of the second embodiment can be basically exhibited.

In addition to this, in this embodiment, the DMOSF is used.
In forming the P− type body diffusion layer 14 and the P + type body buried diffusion layer 32 of ET, the resist film 12 is formed.
And DMOSFET N + type gate electrode 8a as well as D
The gate electrode forming resist film 9b used to form the N + type gate electrode 8a of the MOSFET is used as a mask. Therefore, the resist film 12 and the DMOS
Even if the mask misalignment with the N + type gate electrode 8a of the FET occurs, the N + type gate electrode 8 of the DMOSFET
Boron ions are blocked by the resist film 9 for forming a gate electrode on a. Therefore, unlike the case where the resist film 12 does not exist, boron ions do not penetrate from the upper surface of the N + type gate electrode 8a of the DMOSFET to below the gate electrode. Therefore, in the lower region of the N + type gate electrode 8a, the implanted boron ions penetrate to the portion which enters the N + type gate electrode 8a in the horizontal direction from the source side end of the N + type gate electrode 8a by approximately the same distance. +
There is an advantage that variation in the length of the channel region Rchan between the type source diffusion layer 15 and the N − type drain diffusion layer can be suppressed.

(Fourth Embodiment) Next, a fourth embodiment will be described. 6 (a) -c) and 7 (a)-
FIG. 6C is a sectional view showing a manufacturing process of the semiconductor device according to the fourth embodiment.

The steps shown in FIGS. 6A to 6C are basically the same as the steps shown in FIGS. 1A to 1C and 2A to 2C described in the first embodiment. Are almost the same. However, in the present embodiment, the DMOSF
N + type drain layer 16 and P- type body diffusion layer 1 of ET
A P-type impurity is introduced into the first impurity diffusion layer surrounding 4 to form an extremely low concentration P- type body diffusion layer 30. As a result, the body diffusion layer is composed of the two P- type body diffusion layers 30 and 14. Here, the P− type body diffusion layer 30 contains impurities with a concentration of the order of 10 ¹⁶ cm ⁻³ , and the P− type body diffusion layer 14 contains impurities with a concentration of the order of 10 ¹⁷ cm ^−3. ing.

As described above, by forming the P--type body diffusion layer having a low concentration but a higher concentration in the P--type body diffusion layer 30 having an extremely low concentration, the DMOS is formed.
The withstand voltage characteristic of the FET is improved. Further, since the periphery of the N + type drain diffusion layer 16 becomes the P− type layer, the parasitic capacitance of the N + type drain diffusion layer 16 is reduced and the operation speed of the DMOSFET is improved.

(Fifth Embodiment) Next, a fifth embodiment will be described. 8 (a) to 1 (c) and FIG.
(A) -2 (c) is sectional drawing which shows the manufacturing process of the semiconductor device in 5th Embodiment.

The steps shown in FIGS. 8A to 8C are basically the same as the steps shown in FIGS. 1A to 1C in the first embodiment. That is, the P-type semiconductor substrate 1
After forming the N- type drain diffusion layer 2 which is the first impurity diffusion layer of the DMOSFET, the P- type well diffusion layer 3 of the NMOSFET, and the N- type well diffusion layer 4 of the PMOSFET, respectively, in the DMOSFET forming region and the NMOSFE.
An element isolation 5 for partitioning the T formation region and the PMOS formation region is formed. Furthermore, a P- type V is formed in the PMOSFET formation region.
After forming the t-control diffusion layer 6 and the gate oxide film 7 on the surface of the P-type semiconductor substrate 1 in each region, a polycrystalline silicon film 8 is formed on the entire surface of the substrate, and DMOSFE is formed thereon.
A gate electrode forming resist film 9 is formed to cover the gate electrode forming regions of the T, NMOSFET and PMOSFET.
However, in the present embodiment, the thickness of the polycrystalline silicon film 8 is about 200 nm, which is the same as that of the first embodiment.
It is made thinner than 00 nm.

Next, as shown in FIG. 9A, the polycrystalline silicon film 8 is patterned by dry etching using, for example, the resist film 9 for forming a gate electrode as a mask, and the N + type gate electrode 8a of the DMOSFET is formed. , NMO
N + type gate electrode 8b of SFET, N of PMOSFET
A + type gate electrode 8c is formed. Next, for example, DMOS
The resist film 12 and D having an opening in the source formation region of the FET
Using the N + type gate electrode 8a of the MOSFET as a mask, boron ion is implanted in one step into the body diffusion layer forming region of the DMOSFET. At that time, for example, 1
Under the conditions of 40 keV and 4 × 10 ¹³ cm ⁻² , for example, the implantation angle is 7 with respect to the axis perpendicular to the surface of the P-type semiconductor substrate 1.
The boron ions are implanted at an angle of .degree., That is, in such a manner that the boron ions penetrate into about a half region on the source side of the region below the N @ + type gate electrode 8a of the DMOSFET. At this time, the N + type gate electrode 8a composed of a polycrystalline silicon film (200 nm) in which boron ions are thin
Is injected through the.

Next, as shown in FIG. 9B, the resist film 12 is removed and a heat treatment is performed at, for example, 850 ° C. for about 30 minutes to form a P − -type second impurity diffusion layer of the DMOSFET. The body diffusion layer 14 is formed.

Next, as shown in FIG. 9C, the DMOSFET forming region, N
Arsenic ions, for example, are added to the MOSFET formation region at 40 ke
V, 4 × 10 ¹⁵ cm ⁻² , and then P
In the MOSFET formation region, for example, BF2 is 40 keV, 3
Implantation is performed under the condition of about 10 ¹⁵ cm ^-2 , for example, 850 ° C
By performing low temperature heat treatment for about 60 minutes, DMO
N + type source diffusion layer 15 and channel region R of SFET
chan, N + type drain diffusion layer 16, NMOSFET N
+ Type source diffusion layer 17, N + type drain diffusion layer 18, P
A P + type source diffusion layer 19 and a P + type drain diffusion layer 20 of the MOSFET are formed.

Although not shown in the drawings of this embodiment, thereafter, an NSG film of about 800 nm is formed as an interlayer insulating film by using, for example, a low pressure CVD method, and then, for example, by using a resist film as a mask, the NSG film is formed. The film is etched by dry etching to form a contact hole. Finally, an Al film is formed by a sputtering method, for example, as a metal wiring, and thereafter, the Al film is etched using, for example, a resist film as a mask to form an Al wiring, whereby the semiconductor device is completed.

In this embodiment, when boron ions are implanted using the resist film 12 as a mask in order to form the P--type body diffusion layer 14 and the channel region Rchan of the DMOSFET, the P--type body diffusion layer 14 excluding the channel region is implanted. Is formed similarly to the first embodiment, but has a shape in which the channel region Rchan extends shallowly toward the drain side. That is, N + is injected before boron ion implantation.
When the type gate electrode 8a is thinly formed and impurity ions are implanted into the N + type gate electrode 8 when boron ions are implanted.
This is because it is designed to penetrate through a.

DMOSFE having the above structure
In the semiconductor device of the present embodiment having the T, NMOSFET and PMSFET mounted therein, impurities implanted near the end portion below the gate electrode are driven in at a high temperature by a high temperature drive-in as in the conventional method, and the impurities are laterally moved along the region directly below the gate electrode. Since it is not necessary to diffuse the above into the first embodiment, it is possible to solve the conventional problems (1) and (2) as in the first embodiment. In addition to that, the following remarkable effects can be exerted.

DMOS of DMOSFET type transistor
The channel region Rchan of the FET is formed by the impurity ions implanted through the N + type gate electrode 8a as described above. Therefore, even if the dose amount at the time of ion implantation is large and the implantation energy is large, the impurity concentration in the channel region Rchan of the P − type body diffusion layer 14 is suppressed to be thin, so that the threshold value can be made small. On the other hand, by increasing the dose amount at the time of ion implantation and increasing the implantation energy, the depth of the P − type body diffusion layer 14 below the N + type source diffusion layer 15 is increased and the impurity concentration is increased, so that parasitic There is an advantage that the operation of the bipolar transistor can be suppressed.

In the case of the DMOSFET, even if the depth of the P--type body diffusion layer 14 is slightly changed, the influence on the threshold value Vt is extremely small. Therefore, the buried channel described in the above problem (1). Structured PMOS
Fluctuations in the threshold, such as in FETs, pose almost no problem.

(Sixth Embodiment) Next, a sixth embodiment will be described. 10A to 10C are cross-sectional views showing the manufacturing process of the semiconductor device according to the sixth embodiment.

In the present embodiment, before the step shown in FIG. 10A, the steps shown in FIGS.
The same steps as those shown in FIG. 9C and FIG. 9A are performed. That is, on the P-type semiconductor substrate 1, the N-type drain diffusion layer 2, which is the first impurity diffusion layer of the DMOSFET, and the NMOS.
FET P- type well diffusion layer 3, PMOSFET N-
After forming the respective well diffusion layers 4, DMOSFE
An element isolation 5 for partitioning the T formation region, NMOSFET formation region, and PMOS formation region is formed. In addition, PMOS
After the P- type Vt control diffusion layer 6 is formed in the FET forming region and the gate oxide film 7 is formed on the surface of the P type semiconductor substrate 1 in each region, the N-type DMOSFET made of a polycrystalline silicon film having a thickness of about 200 nm is formed. + Type gate electrode 8a, NMOS
N + type gate electrode 8b of FET, N + of PMOSFET
The mold gate electrode 8c is formed. Next, using the resist film 12 having the source formation region of the DMOSFET shown in FIG. 10A opened and the N + type gate electrode 8a of the DMOSFET as a mask, one step boron ion is formed in the body diffusion layer formation region of the DMOSFET. Make an injection. At this time, also in the present embodiment, the ion implantation conditions are the same as those in the fifth embodiment. Then, similar to the fifth embodiment, in the lower region of the N + type gate electrode 8a, about a half of the source side, a boron ion is formed of a thin polycrystalline silicon film (200 nm). Done N
It is injected through the + type gate electrode 8a. Therefore, shallow implantation is performed in a region of about half of the source side of the region below the N + type gate electrode 8a.

After the above steps are performed, as shown in FIG. 10A, the body film of the DMOSFET is diffused by using the same resist film 12 and the N + type gate electrode 8a of the DMOSFET as the mask used in the above steps. In the layer formation region, for example, boron ions having a high acceleration energy of 150 keV
Under the condition that the implantation amount is about 1 × 10 ¹⁴ cm ^-2 and the implantation angle is small, for example, at an angle of 0 ° with respect to the axis perpendicular to the surface of the P-type semiconductor substrate 1, Make an injection.

Next, as shown in FIG. 10B, the resist film 12 is removed, and heat treatment is performed at, for example, 850 ° C. for about 30 minutes, whereby the P--type body diffusion layer 14 of the DMOSFET and the channel of the DMOSFET are formed. A region Rchan and a P + type body buried diffusion layer 32 which is a third impurity diffusion layer are formed. In this case, the lateral end of the P + type body-embedded diffusion layer 32 is the N + of the DMOSFET.
It exists near the center of the mold gate electrode 8a. Also,
The P + type body diffusion layer 32 is deeper than the P− type body diffusion layer 14 into the semiconductor substrate 1, and the P− type body diffusion layer 14 has N + of the DMOSFET.
The surface concentration directly below the mold gate electrode 8a is hardly affected. Therefore, the Vt of the DMOSFET is determined only by the P- type body diffusion layer 14 without being influenced by the P + type body buried diffusion layer 32.

The P + type body buried diffusion layer 32
Since the ion implantation for forming the P- body diffusion layer 14 is performed before the ion implantation for formation, the crystals in the semiconductor substrate are made amorphous to some extent. Then, since ion implantation is performed in the vertical direction in that state, it is possible to reliably prevent channeling during ion implantation. Therefore, the P + type body-embedded diffusion layer 32 does not have an irregular shape.

Next, as shown in FIG. 10C, for example, using the resist film as a mask, the DMOSFET formation region,
Arsenic ions, for example, at 40 ke are formed in the NMOSFET forming region.
V, 4 × 10 ¹⁵ cm ⁻² , and then P
For example, BF2 ions of 40 ke are formed in the MOSFET formation region.
^{Implanted under} the conditions of V, 3 × 10 ¹⁵ cm ⁻² , for example, 85
By performing heat treatment at 0 ° C for about 60 minutes, DMO
SFET N + type source diffusion layer 15, N + type drain diffusion layer 16, NMOSFET N + type source diffusion layer 17,
An N + type drain diffusion layer 18, a P + type source diffusion layer 19 and a P + type drain diffusion layer 20 of a PMOSFET are formed.

Although not shown in the drawings of this embodiment, thereafter, an NSG film having a thickness of about 800 nm is formed as an interlayer insulating film by using, for example, a low pressure CVD method, and thereafter, NSG film is formed by using, for example, a resist film as a mask. The film is etched by dry etching to form a contact hole. Finally, an Al film is formed by a sputtering method, for example, as a metal wiring, and thereafter, the Al film is etched using, for example, a resist film as a mask to form an Al wiring, whereby the semiconductor device is completed.

In the present embodiment as well, as in the fifth embodiment, the channel region Rchan has a shape that extends shallowly toward the drain side, and therefore, the same effect as in the fifth embodiment can be exhibited. . In addition, by suppressing the operation of the parasitic bipolar transistor, the withstand voltage between the source and drain can be improved.

Since the ion implantation for forming the P- type body diffusion layer 14 and the P + type body buried diffusion layer 32 is performed using the same mask, the ion implantation step is added once. This is all that is needed and there is only a small increase in cost to obtain this effect.

(Seventh Embodiment) Next, a seventh embodiment will be described. 11A to 11C are cross-sectional views showing the manufacturing process of the semiconductor device according to the seventh embodiment.

In this embodiment, before the step shown in FIG. 11A, the process shown in FIGS.
The same process as the process shown in (c) is performed. That is, the N-type drain diffusion layer 2 which is the first impurity diffusion layer of the DMOSFET, the P-type well diffusion layer 3 of the NMOSFET, and the N-type well diffusion layer 4 of the PMOSFET are formed on the P-type semiconductor substrate 1, respectively. After that, the DMOSFET formation region, N
An element isolation 5 for partitioning the MOSFET formation region and the PMOS formation region is formed. Further, after the P- type Vt control diffusion layer 6 is formed in the PMOSFET forming region and the gate oxide film 7 is formed on the surface of the P type semiconductor substrate 1 in each region, the DMOSF made of a polycrystalline silicon film having a thickness of about 300 nm is formed.
N + type gate electrode 8a of ET, N + type gate electrode 8b of NMOSFET, N + type gate electrode 8 of PMOSFET
Form c. However, in the present embodiment, the gate electrode 8
The widths a to 8c are set to be narrower than those in the above embodiments.

Next, as shown in FIG. 11A, for example, with the resist film 12 having an opening in the source forming region of the DMOSFET and the N + type gate electrode 8a of the DMOSFET as a mask, in the body diffusion layer forming region of the DMOSFET,
2 from two directions that make an angle of 180 ° with each other when viewed two-dimensionally
Step boron ion implantation is performed. At that time, for example, under the conditions of 120 keV and 4 × 10 ¹³ cm ^-2 , for example, the implantation angle is 10 ° with respect to the axis perpendicular to the surface of the P-type semiconductor substrate 1, that is, the N + -type gate electrode of the DMOSFET. The first boron ion implantation is performed so that the boron ions enter only the region below the source side end of 8a.
Furthermore, the semiconductor substrate 1 is rotated 180 degrees to
The second boron ion implantation is performed at an inclination angle of 10 ° so that the boron ions penetrate below the edge of the element isolation 5 in the FET formation region.

Next, as shown in FIG. 11B, the resist film 12 is removed and a heat treatment is performed at, for example, 850 ° C. for about 30 minutes to form a P − -type second impurity diffusion layer of the DMOSFET. The body diffusion layer 14 is formed.

Next, as shown in FIG. 11C, a silicon oxide film is deposited to a thickness of about 200 nm on the entire surface of the silicon substrate by, for example, a low pressure CVD method, and then the silicon oxide film is removed by anisotropic dry etching. Etch back is performed to form sidewalls 22 on both side surfaces of each of the gate electrodes 8a to 8c.

Next, as shown in FIG. 11D, with the resist film (not shown) and the sidewall 22 as a mask, for example, arsenic ions of 40 keV and 4 × 10 ¹⁵ are formed in the DMOSFET formation region and the NMOSFET formation region. c
By implanting under the condition of m ^-2 , and further, for example, BF2 is implanted into the PMOSFET formation region under the condition of 40 keV, 3 x 10 ¹⁵ cm ^-2 , and heat-treated at, for example, 850 ° C for about 60 minutes. N + type source diffusion layer 15 and channel region Rchan, N + type drain diffusion layer 16, NMOSFET N + type source diffusion layer 17,
An N + type drain diffusion layer 18, a P + type source diffusion layer 19 and a P + type drain diffusion layer 20 of a PMOSFET are formed.

Although not shown in the drawings of this embodiment, thereafter, an NSG film having a thickness of about 800 nm is formed as an interlayer insulating film by using, for example, a low pressure CVD method, and thereafter, NSG film is formed by using, for example, a resist film as a mask. The film is etched by dry etching to form a contact hole. Finally, an Al film is formed by a sputtering method, for example, as a metal wiring, and thereafter, the Al film is etched using, for example, a resist film as a mask to form an Al wiring, whereby the semiconductor device is completed.

In this embodiment, when forming the P--type body diffusion layer 14 and the channel region Rchan of the DMOSFET, as shown in FIG. 11A, the inclination angle of 30 is larger than the inclination angle of 30 ° in each of the above embodiments. Boron ions are implanted with a significantly small inclination angle and at an angle such that boron ions enter the side surface of the N + type gate electrode 8a of the DMOSFET on the side of the source region which is not covered with the resist film 12. Then, after that, low-temperature activation heat treatment is performed to form the P- type body diffusion layer 14 of the DMOSFET and the channel region Rchan of the DMOSFET. Further, after that, before forming the N + type source diffusion layer 15 of the DMOSFET, the NMOSFET of the DMOSFET is formed.
A side wall 22 is formed on the side surface of the + type gate electrode 8a, and the side wall 22 and the N + type gate electrode 8a are formed.
By using the resist film and the resist film as a mask, the DMOSF
The N + type source diffusion layer 15 is formed by shifting the arsenic implantation region to the source region side rather than the boron implantation region when forming the P− type body diffusion layer of ET.

DMOSFETs and NMOs having such a structure
By forming a semiconductor device equipped with SFET and PMOSFET, the following effects can be exhibited.

The P-type body diffusion layer 14 of the DMOSFET type transistor and the channel region R of the DMOSFET.
In forming the chan, as described above, after ion implantation into the body diffusion layer with a small inclination angle, the sidewall 22 is formed on the side surface of the N + type gate electrode 8a, and this sidewall is used as a mask. N + type source diffusion layer 1
5 are formed. Therefore, only by ion implantation and low-temperature activation, impurities are allowed to penetrate into the region below the gate electrode, and the channel region Rchan having a sufficient length is provided between the N + type source diffusion layer 15 and the N− drain diffusion layer 2. Can be easily formed. That is, it becomes easy to control the threshold value without performing high temperature drive-in for laterally expanding the body diffusion layer, which has been performed conventionally.
It can be seen that the same effect as that of the first embodiment can be exhibited.

Further, in this embodiment, since the boron ions are implanted at a small inclination angle (10 °) in the step shown in FIG. 11A, the depth of the P − -type body diffusion layer 14 of the DMOSFET is reduced. The depth is deeper than the depth in the first to fourth embodiments. This means that the resistance of the P- type body diffusion layer 14 becomes low, and even if the surface concentration of the P- type body diffusion layer 14 is lowered and the threshold voltage is lowered in order to improve the performance of the DMOSFET, Compared with the first embodiment, the resistance of the P- body diffusion layer can be lowered. Therefore, the fluctuation of the threshold voltage due to the rise of the potential of the body terminal due to the substrate current of the DMOSFET is suppressed. In particular, the P- type body diffusion layer 1
4 has a base, the N + type source diffusion layer 15 serves as an emitter, and the N + type drain diffusion layer 2 serves as a collector, even if an NPN type parasitic bipolar transistor is produced, the impurity concentration of the portion corresponding to the base is high. Since it has a low resistance, it is possible to suppress the operation of the parasitic bipolar transistor. That is, the withstand voltage between the source and the drain is improved. Also, DMOSFET
When N is formed simultaneously with NMOSFET and PMOSFET, sidewalls are generally attached to the gate electrodes of NMOSFET and PMOSFET. Therefore, by adopting the manufacturing method of the present embodiment, the number of steps is not increased. A semiconductor device having high withstand voltage between the source and drain of the DMOSFET can be formed.

(Modifications of First to Seventh Embodiments) First to First
In the seventh embodiment, the source and drain contact diffusion layers of the DMOSFET are the N + type source diffusion layers 1.
5, and each of the N + type drain diffusion layers 16 is a single layer, and has an LDD structure, that is, a double layer of an N- type source diffusion layer, an N + type source diffusion layer and an N- type drain diffusion layer, and an N + type drain diffusion layer. It may be a structure.

In the first to sixth embodiments, D
N + type gate electrode 8a of MOSFET, NMOSFET
Although the side wall of the insulating film is not formed on the side wall of the N + type gate electrode 8b of the above and the side surface of the N + type gate electrode 8c of the PMOSFET, it may be formed. In this case, the sidewall formation may be performed before or after the ion implantation for forming the P − type body diffusion layer 14.

Further, this sidewall may be used as an ion implantation mask for forming the source and drain contact diffusion layers.

In the first to seventh embodiments, D
N + type gate electrode 8a of MOSFET, NMOSFET
Although the N + type gate electrode 8b and the N + type gate electrode 8c of the PMOSFET are single layer films of polycrystalline silicon, they may be formed of a single layer film of a metal film, a semiconductor film or a silicide film. Alternatively, except for the fifth and sixth embodiments, a conductive film such as a metal film, a semiconductor film, a silicide film, or an insulating film such as a silicon oxide film may be formed on the polycrystalline silicon film. In particular, by forming these protective films, there is an advantage that the function of preventing passage of impurity ions during ion implantation can be strengthened.

In the first to seventh embodiments, P
Although the gate electrode of the MOSFET is N + type, it may be P + type.

Further, in the first, second and third embodiments, the low concentration drain layer of the DMOSFET is the N − type drain diffusion layer 2, but it may be an N − type epitaxial growth layer. It may be formed before the separation 5 is formed. . Similarly, P- in the fourth embodiment
The type body diffusion layer 30 may be a P − type epitaxial growth layer.

In the first to seventh embodiments, N
Although the Vt control diffusion layer of MOSFET is not formed,
It may be formed before forming the gate oxide film.

Further, in the first to seventh embodiments, the impurity ion implantation is performed in two steps, but the MISFET having the gate electrodes arranged in directions orthogonal to each other in the semiconductor device is mounted. In many cases,
In that case, 4-step ion implantation in which the implantation direction is changed every 90 ° in the plane can be performed.

In the first, second and third embodiments, after the N + type source diffusion layer 15 of the DMOSFET is formed, the P− type body diffusion layer 14 and the P + type body diffusion layer 14 which are the body diffusion layers of the DMOSFET are formed. Body embedded diffusion layer 3
2 may be formed by ion implantation.

Further, in the third embodiment, the gate electrode forming resist film 9 is used as a part of the mask for implanting the body diffusion layer, but this is not limited to the resist film.
A film processed to the same size as the N + type gate electrode 8a of the MOSFET may be used.

(Regarding Profile of P− Type Body Diffusion Layer) Next, the relationship between the implantation angle of impurity ions and the profile of the P− type body diffusion layer 14 when forming the P− type body diffusion layer 14 will be described. 12
Description will be made with reference to (a) to (c) and FIGS. 13 (a) and 13 (b).

As shown in FIG. 12A, as in each of the above-described embodiments, the resist film 12 having a relatively large thickness and a narrow opening is used as a mask to form a direction (a direction greatly inclined with respect to an axis perpendicular to the surface of the semiconductor substrate). When the ion implantation is performed in two steps from 30 °), the P − type body diffusion layer 14 has a profile in which a recess is formed near the center downward. In this case, especially, the impurity ions penetrate deeply in the lateral direction in the region below the N + type gate electrode 8a of the DMOSFET. Therefore, the length of the channel region can be sufficiently secured without performing the high temperature drive-in diffusion process.

On the other hand, as shown in FIG. 12B, two-step ion implantation is performed with a large tilt angle but a relatively small tilt angle (about 20 °) using the resist film 12 that is relatively thin and has a wide opening. When the above is performed, the P − type body diffusion layer 14 has a profile such that a convex portion is formed near the center. Even with such a method, it is possible to laterally infiltrate the impurity ions into the region below the N + type gate electrode 8a.

As shown in FIG. 12C, when ion implantation is performed from one direction inclined to the element isolation 5 side in the source formation region, the P--type body diffusion layer 14 is directed downward. The most protruding portion is the N + type gate electrode 8a
It has a profile that is offset to the side.
In this case also, the effect of the present invention can be exhibited. However, for example, the N + type source diffusion layer 1 in the first to third embodiments is used.
In the P- type body diffusion layer 14 to the extent that 5 does not come into contact with the N- type drain diffusion layer 2, that is, to prevent conduction between the N- drain diffusion layer and the N + type source diffusion layer at this portion. It is necessary that the impurity ions of 1 have entered the depth of the semiconductor substrate on the element isolation 5 side.

As shown in FIG. 13A, the gate electrode 8
a to reduce the thickness of the resist film 12 of the gate electrode 8a.
When the impurity ions are implanted through a portion not covered with (in contrast to the sixth and seventh embodiments, the inclination angle in the ion implantation direction is about 25 ° here), the gate electrode A profile having a portion with a small depth (a portion which becomes a channel region) below 8a is obtained. The tip of the shallow portion of the P- type body diffusion layer 14 is defined by the resist film 12. In this way,
By increasing the implantation energy and dose, P-
It is possible to increase the depth of the body diffusion layer 14 and increase the impurity concentration in the back of the substrate, while decreasing the impurity concentration in the vicinity of the surface of the substrate to be the channel region. That is, the threshold value can be lowered and the operation of the parasitic transistor can be suppressed.

As shown in FIG. 13B, when ion implantation with a small tilt angle is performed on the assumption that a sidewall is formed on the side surface of the gate electrode 8a in a later step, the profile is directed toward the back of the substrate. Becomes a simple convex type. In this case, the impurity ions do not penetrate so deep in the lateral direction below the gate electrode 8a, but the depth of the P − type body diffusion layer 14 increases and the resistance decreases, thereby suppressing the differential of the parasitic bipolar transistor. There are advantages. After that, an insulator sidewall is formed on a side surface of the gate electrode, and when the source diffusion layer is formed, ion implantation is performed using the insulator sidewall and the gate electrode as a mask, so that the source diffusion layer is formed. Since the end portion and the end portion of the P− type body diffusion layer 14 can be offset by an arbitrary distance (substantially equal to the film thickness of the silicon oxide film for forming the sidewall), a sufficient length of the channel region can be secured. can do. Therefore, a transistor having this profile can also exhibit excellent characteristics.

As in the conventional method, the impurity ions are implanted from a direction (<10 °) in which the ion implantation direction is hardly inclined with respect to the axis perpendicular to the surface of the semiconductor substrate, and then the high temperature drive-in process is performed. If you do
The -type body diffusion layer has a profile such that the bottom surface of the downwardly projecting portion is substantially flat.

Since the impurity ions do not function as acceptors or donors as they are implanted, heat treatment for activation is necessary. By this heat treatment,
The impurity ions diffuse to some extent, but the diffusion distance is much smaller than the diffusion distance in the conventional high temperature drive-in process. That is, in the method of the present invention, since it is not necessary to diffuse the impurity ions to a long distance, heat treatment is performed at a relatively low temperature of 850 ° C. for about 30 minutes for a long time, or at a relatively high temperature for an extremely short time. I'm done. On the other hand, in the conventional method, it is necessary to perform heat treatment at a high temperature of 1000 ° C. for about 30 minutes and for a long time. This is the major difference between the present invention and the conventional method.

[0151]

According to the present invention, in a semiconductor device having a DMISFET mounted on a semiconductor substrate, a DMI
The SFET includes a first impurity diffusion layer, a gate insulating film and a gate electrode, a source diffusion layer and a drain diffusion layer into which a first conductivity type impurity has been introduced, and a threshold value control level surrounding the source diffusion layer. Since the second impurity diffusion layer containing the second conductivity type impurity is provided, the structure is such that high temperature drive-in is not required at the time of forming the second impurity diffusion layer, and the impurity in the gate electrode to the channel region is formed. Intrusion can be prevented, and therefore, fluctuations and variations in the threshold value of the DMISFET and deterioration in reliability of the gate insulating film can be effectively prevented.

According to the tenth to fifteenth aspects, in the semiconductor device in which the DMISFET is mounted on the semiconductor substrate, the DM
The ISFET includes a first impurity diffusion layer, a gate insulating film and a gate electrode, insulator sidewalls formed on both side surfaces of the gate electrode, a source diffusion layer and a drain diffusion layer into which a first conductivity type impurity is introduced. And a second impurity diffusion layer that is formed by introducing a second conductivity type impurity having a threshold value control level and that surrounds the source diffusion layer, and the length of the portion of the second impurity diffusion layer that becomes the channel region is Since the structure is defined by the thickness of the sidewall, in addition to the effects of the first to eighth aspects, it is possible to reduce the threshold value and suppress the operation of the parasitic bipolar transistor.

According to the sixteenth to twenty-eighth aspects, as a method of manufacturing a semiconductor device having a DMISFET mounted on a semiconductor substrate, a step of forming an element isolation and a step of forming a first impurity diffusion layer in an active region. , Gate insulating film and DMIS
A step of forming a gate electrode of the FET, a step of implanting ions of the second conductivity type impurity using a mask having an opening on the source region side to form a second impurity diffusion layer,
Since the step of implanting ions of conductivity type impurities to form the drain diffusion layer and the source diffusion layer is provided, the second impurity diffusion layer is formed without performing the high temperature drive-in process, and the second diffusion layer is formed from the gate electrode of the DMISFET. It is possible to effectively prevent the impurities from diffusing to the channel region, and thus it is possible to form a DMISFET with a small fluctuation or variation in threshold value and a highly reliable gate insulating film.

According to claims 29 to 32, as a method of manufacturing a semiconductor device having a DMISFET mounted on a semiconductor substrate, a step of forming element isolation and a step of forming a first impurity diffusion layer in an active region. , Gate insulating film and DMIS
A step of forming a gate electrode of the FET, a step of implanting ions of a second conductivity type impurity to form a second impurity diffusion layer using the gate electrode as a mask, and a side surface on both side surfaces of the gate electrode. The step of forming a wall and the step of forming a drain diffusion layer and a source diffusion layer by implanting ions of the first conductivity type impurity using the sidewalls and the gate electrode as a mask are provided.
In addition to the effects of .about.26, it is possible to form a DMISFET which has a low threshold value, a small substrate resistance, and can suppress the operation of the parasitic bipolar transistor.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing respective first half steps of a manufacturing process of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view showing the latter half of the manufacturing steps of the semiconductor device according to the first embodiment.

FIG. 3 is a cross-sectional view showing the latter half of the manufacturing steps of the semiconductor device according to the second embodiment.

FIG. 4 is a cross-sectional view showing an ion implantation process for forming a P− type body diffusion layer and a P + type body buried diffusion layer in the manufacturing process of the semiconductor device according to the third embodiment.

FIG. 5 is a cross-sectional view showing a step of forming a gate electrode and a source / drain diffusion layer in the manufacturing process of the semiconductor device according to the third embodiment.

FIG. 6 is a cross-sectional view showing the first half of the manufacturing steps of the semiconductor device according to the fourth embodiment.

FIG. 7 is a cross-sectional view showing the latter half of the manufacturing steps of the semiconductor device according to the fourth embodiment.

FIG. 8 is a cross-sectional view showing the first half of the manufacturing steps of the semiconductor device according to the fifth embodiment.

FIG. 9 is a cross-sectional view showing the latter half of the manufacturing steps of the semiconductor device according to the fifth embodiment.

FIG. 10 is a cross-sectional view showing the latter half of the manufacturing steps of the semiconductor device according to the sixth embodiment.

FIG. 11 is a cross-sectional view showing the latter half of the manufacturing steps of the semiconductor device according to the seventh embodiment.

FIG. 12 shows a relationship between an implantation mode of impurity ions and a shape of a second impurity diffusion layer to be formed in a step of forming a second impurity diffusion layer in a manufacturing process of the semiconductor device according to the first embodiment. FIG.

FIG. 13 is a diagram showing a difference between an implantation mode of impurity ions and a shape of a second impurity diffusion layer to be formed in a step of forming a second impurity diffusion layer in a manufacturing process of the semiconductor device according to the sixth and seventh embodiments. It is explanatory drawing which shows a relationship.

FIG. 14 is a cross-sectional view showing the first half of each of the conventional semiconductor device manufacturing processes.

FIG. 15 is a cross-sectional view showing each step of the latter half of the manufacturing steps of the conventional semiconductor device.

[Explanation of symbols]

 1 P-type semiconductor substrate 2 N- type drain diffusion layer 3 P- type well diffusion layer 4 N- type well diffusion layer 5 Element isolation 6 P- type Vt control diffusion layer 7 Gate oxide film (gate insulating film) 8 Polycrystalline silicon Films 8a to 8c N + type gate electrode 9 Resist film for forming gate electrode 12 Resist film 14 P− type body diffusion layer 15 N + type source diffusion layer 16 N + type drain diffusion layer 17 N + type source diffusion layer 18 N + Type drain diffusion layer 19 P + type source diffusion layer 20 P + type drain diffusion layer 30 P− type body diffusion layer

Claims (32)

[Claims] 1. A semiconductor device having at least one DMISFET mounted in an active region surrounded by element isolation in a semiconductor substrate, wherein the DMISFET has a low-concentration first conductivity type impurity or second conductivity type in the active region. A first impurity diffusion layer formed by introducing a type impurity, a gate insulating film formed on the active region, a gate electrode formed on the gate insulating film, and the gate electrode in the active region. A source diffusion layer formed by introducing a high-concentration first conductivity type impurity into a region located on one side of the gate electrode, and a region located on the other side of the gate electrode in the active region. A drain diffusion layer formed by introducing a high concentration of the first conductivity type impurity and surrounded by the first impurity diffusion layer; and a drain diffusion layer surrounding the source diffusion layer in the active region and Formed by introducing a second conductivity type impurity having a threshold control level into a region reaching a part of the lower region of the gate electrode, and being separated from the drain diffusion layer by sandwiching the first impurity diffusion layer. And a second impurity diffusion layer. 2. The semiconductor device according to claim 1, wherein, in the second impurity diffusion layer, in the region located below the source diffusion layer in the active region, both end portions of the second impurity diffusion layer are formed more than the central portion of the semiconductor region. A semiconductor device having a profile with a large penetration depth into the back of the substrate. 3. The semiconductor device according to claim 1, wherein the second impurity diffusion layer is closer to the gate electrode than to the element isolation side in a region located below the source diffusion layer in the active region. A semiconductor device having a profile in which the depth of penetration into the depth of the semiconductor substrate is larger. 4. The semiconductor device according to claim 1, wherein the second impurity diffusion layer is located below the source diffusion layer in the active region in a region located below the gate electrode in the active region. A semiconductor device having a profile in which the depth of penetration into the depth of the semiconductor substrate is smaller than the depth of the region. 5. The semiconductor device according to claim 1, 2, 3, or 4, wherein the DMISFET is formed in a region including a part of a depth of the second impurity diffusion layer and not including a vicinity of a surface of the active region. A semiconductor device further comprising a third impurity diffusion layer formed by introducing a high concentration of second conductivity type impurities. 6. The semiconductor device according to claim 1, 2, 3 or 4, wherein the first impurity diffusion layer is formed by introducing a second conductivity type impurity, and at least the first and second impurities. A semiconductor device, wherein the diffusion layer functions as a body diffusion layer. 7. The semiconductor device according to claim 1, further comprising a protective film formed on the gate electrode and having a function of blocking the passage of impurity ions. 8. The semiconductor device according to claim 1, 2, 3 or 4, wherein the second and third devices are surrounded by the element isolation in the semiconductor substrate.
Further includes first and second MISFETs having first and second conductivity type channel structures respectively formed in the active regions of the first and second MISFETs, wherein the first MISFET is a gate insulating layer formed on the second active region. A film, a gate electrode formed on the gate insulating film, and a source formed by introducing a first conductivity type impurity into regions located on both sides of the gate electrode in the second active region. A drain diffusion layer, and the second MISFET includes a gate insulating film formed on the third active region, a gate electrode formed on the gate insulating film, and the third active region. A semiconductor device comprising a source / drain diffusion layer formed by introducing a second conductivity type impurity into regions located on both sides of the gate electrode in the region. 9. The semiconductor device according to claim 8, wherein the gate insulating film and the gate electrode of the first and second MISFETs are made of the same material and have the same thickness as the gate insulating film and the gate electrode of the DMISFET. A semiconductor device having. 10. A semiconductor device having at least one DMISFET mounted in an active region surrounded by element isolation in a semiconductor substrate, wherein the DMISFET is a low concentration first conductivity type impurity or a second conductivity type in the active region. A first impurity diffusion layer formed by introducing a type impurity, a gate insulating film formed on the active region, a gate electrode formed on the gate insulating film, and both side surfaces of the gate electrode. It is formed by introducing a high-concentration first-conductivity-type impurity into a region located on one side of the gate electrode in the active region and on the side wall of the insulator sidewall formed above A high-concentration first-conductivity-type impurity is added to the source diffusion layer whose position is defined by the insulator sidewall and the region located on the other side of the gate electrode in the active region. A threshold control level in a region that surrounds the source diffusion layer in the active region and reaches a part of the region below the gate electrode, and the drain diffusion layer that is formed by being filled in and is surrounded by the first impurity diffusion layer. And a second impurity diffusion layer defined by the source-side end of the gate electrode, the semiconductor being formed by introducing an impurity of the second conductivity type. apparatus. 11. The semiconductor device according to claim 10, wherein the second impurity diffusion layer penetrates deeper into the semiconductor substrate toward the center in a region located below the source diffusion layer in the active region. A semiconductor device having a profile with an increased depth. 12. The semiconductor device according to claim 10, wherein the DMISFET has a high-concentration first conductivity in a region that includes a part of the inner side of the second impurity diffusion layer and does not include the vicinity of the surface of the active region. A semiconductor device further comprising a third impurity diffusion layer formed by introducing a type impurity. 13. The semiconductor device according to claim 10, wherein the second and third devices are surrounded by the element isolation in the semiconductor substrate.
Further includes first and second MISFETs having first and second conductivity type channel structures respectively formed in the active regions of the first and second MISFETs, wherein the first MISFET is a gate insulating layer formed on the second active region. A film, a gate electrode formed on the gate insulating film, insulator sidewalls formed on both side surfaces of the gate electrode, and located on both sides of the gate electrode in the second active region. Is formed by introducing an impurity of the first conductivity type into a region where the gate electrode side is formed of a source / drain diffusion layer defined by the insulator sidewall, and the second MISFET is the third A gate insulating film formed on the active region, a gate electrode formed on the gate insulating film, insulator sidewalls formed on both side surfaces of the gate electrode, A source / drain diffusion layer formed by introducing impurities of the second conductivity type into regions located on both sides of the gate electrode in the active region of No. 3, and having gate electrode side end portions defined by the insulator sidewalls; A semiconductor device comprising: 14. The semiconductor device according to claim 13, wherein the gate insulating film and the gate electrode of the first and second MISFETs are made of the same material and have the same thickness as the gate insulating film and the gate electrode of the DMISFET. A semiconductor device having. 15. The semiconductor device according to claim 13, wherein a region located below the gate electrode and the source / drain are present in at least one of the second and third active regions. Between the diffusion layer and the M
A semiconductor device, comprising: a low-concentration source / drain diffusion layer formed by introducing a low-concentration impurity having the same conductivity type as that of an impurity introduced into the source / drain diffusion layer of the ISFET. 16. A method of manufacturing a semiconductor device in which at least one DMISFET is mounted in an active region surrounded by an element isolation in a semiconductor substrate, wherein the element isolation for partitioning the active region is formed in the semiconductor substrate. And a second step of introducing a first conductivity type impurity or a second conductivity type impurity into the active region to form a first impurity diffusion layer, and gate insulation of the DMISFET on the active region. A third step of forming a film and a gate electrode, and ion implantation of a second conductivity type impurity into the active region by using a mask member having an opening in the source side region of the active region, A fourth step of forming a second impurity diffusion layer extending from a region located below the element isolation to a region located below the gate electrode, and using the gate electrode as a mask. Ions of the first conductivity type impurity are implanted into the active regions located on both sides of the gate electrode, and the drain diffusion layer of the DMISFET surrounded by the first impurity diffusion layer and the second impurity diffusion layer are surrounded. A fifth step of forming a source diffusion layer of a DMISFET and a method of manufacturing a semiconductor device. 17. The method of manufacturing a semiconductor device according to claim 16, wherein in the fourth step, the gate electrode is also used as a mask to face the gate electrode with respect to an axis perpendicular to the surface of the semiconductor substrate. Ions of the second conductivity type impurity are implanted from at least one direction including a direction inclined to the side, and the source region side end of the second impurity diffusion layer is defined by the source side end of the gate electrode. As above second
A method of manufacturing a semiconductor device, comprising forming the impurity diffusion layer of 18. The method of manufacturing a semiconductor device according to claim 17, wherein in the fourth step, the second conductivity type is applied from a direction in which an inclination angle with respect to an axis perpendicular to the surface of the semiconductor substrate is 10 ° or more and 45 ° or less. A method of manufacturing a semiconductor device, which comprises implanting impurity ions. 19. The method of manufacturing a semiconductor device according to claim 17, wherein in the fourth step, ions of the second conductivity type impurity are included in two directions including a direction inclined to the gate electrode side, and The second impurity diffusion layer is implanted from a direction inclined at a large angle with respect to the axis perpendicular to the surface of the semiconductor substrate, and the second impurity diffusion layer is formed in the region located below the source diffusion layer in the active region, at both ends of the region from the central portion. The method for manufacturing a semiconductor device is characterized in that the portion is formed so as to have a profile in which the depth of penetration into the depth of the semiconductor substrate is larger. 20. The method of manufacturing a semiconductor device according to claim 17, wherein in the fourth step, ions of the second conductivity type impurity are included in two directions including a direction inclined to the gate electrode side, and The second impurity diffusion layer is implanted with a large amount of energy from a direction inclined at a small angle with respect to an axis perpendicular to the surface of the semiconductor substrate, and the second impurity diffusion layer is formed at both ends in a region located below the source diffusion layer in the active region. A method of manufacturing a semiconductor device, wherein the central portion is formed to have a profile in which the depth of penetration into the depth of the semiconductor substrate is larger than that of the portion. 21. The method of manufacturing a semiconductor device according to claim 20, wherein in the fourth step, an inclination angle with respect to an axis perpendicular to the surface of the semiconductor substrate in the direction of ion implantation of the second conductivity type impurity is 30 °. A method of manufacturing a semiconductor device, comprising: 22. The method of manufacturing a semiconductor device according to claim 17, wherein in the fourth step, ions of the second conductivity type impurity are implanted only from a direction inclined toward a side facing the gate electrode, The second impurity diffusion layer has a profile in which the depth of penetration into the depth of the semiconductor substrate is larger on the gate electrode side than on the element isolation side in the region located below the source diffusion layer in the active region. A method of manufacturing a semiconductor device, comprising: 23. The method of manufacturing a semiconductor device according to claim 17, wherein in the third step, the insulating film and the conductive film are sequentially deposited, and then the first electrode covering the conductive film is formed on the conductive film. Is performed to selectively remove the conductive film below the opening of the first resist film, and in the fourth step, the active film is formed on the first resist film. A method of manufacturing a semiconductor device, comprising forming a second resist film having an opening on the source side of the region and using the first and second resist films as the mask member. 24. The method of manufacturing a semiconductor device according to claim 17, wherein before the fourth step, a step of forming a protective film having a function of blocking passage of the second conductivity type impurity ions on the gate electrode. A method of manufacturing a semiconductor device, further comprising: 25. The method of manufacturing a semiconductor device according to claim 16, wherein in the third step, the gate electrode has a thickness that allows ions of the second conductivity type impurity in the fourth step to pass therethrough. In the fourth step, the second conductivity type impurity is implanted so as to pass through the gate electrode, and the second impurity diffusion layer is formed below the gate electrode in the active region. A method of manufacturing a semiconductor device, characterized in that the semiconductor device is formed so as to have a profile in which the depth inward of the substrate is shallow in the positioned region. 26. The method of manufacturing a semiconductor device according to claim 16, wherein after the fourth step, ions of the second conductivity type impurity are removed by using a mask common to the mask used in the fourth step. A third impurity diffusion that is injected into the active region and includes a high concentration of the second conductivity type impurity in a region that includes at least a part of the inner side of the second impurity diffusion layer and is away from the surface of the active region. A method of manufacturing a semiconductor device, further comprising a step of forming a layer. 27. The method of manufacturing a semiconductor device according to claim 16, wherein in the second step, a second conductivity type impurity is implanted into the active region, and the second impurity diffusion layer and DMISF are formed.
A method of manufacturing a semiconductor device, comprising forming a first impurity diffusion layer which functions as a body diffusion layer of ET. 28. The method of manufacturing a semiconductor device according to claim 16, wherein in the first step, first and second conductivity type channel structures surrounded by the element isolation are provided on a semiconductor substrate. Second and third active regions for forming a second MISFET are further formed, and the first and second MISFETs are formed in the second and third active regions before the third step. Further comprising the step of individually implanting the threshold value controlling impurities in the third step, wherein in the third step, a gate insulating film and a gate electrode are formed also on the second and third active regions, The step 5 further includes the step of forming the source / drain diffusion layers of the first MISFET and the step of forming the source / drain diffusion layers of the second MISFET. Method. 29. A method of manufacturing a semiconductor device, wherein at least one DMISFET is mounted in an active region surrounded by an element isolation in a semiconductor substrate, the first isolation forming an active region in the semiconductor substrate. And a second step of introducing a first conductivity type impurity or a second conductivity type impurity into the active region to form a first impurity diffusion layer, and gate insulation of the DMISFET on the active region. A third step of forming a film and a gate electrode, and using the mask member having the source side region of the active region opened and the gate electrode as a mask, the ions of the second conductivity type impurity are perpendicular to the surface of the semiconductor substrate. Is injected into the active region from a direction having a small inclination angle with respect to the above-mentioned direction, and is located in the source side region of the active region and below the element isolation end portion in the active region. A fourth step of forming a second impurity diffusion layer over a region located below the end of the gate electrode, and a fifth step of forming an insulator sidewall on both side surfaces of the gate electrode, Using the gate electrode and the insulator sidewall as a mask, ions of the first conductivity type impurity are implanted into the active regions located on both sides of the gate electrode to form a DMISFET surrounded by the first impurity diffusion layer. A method of manufacturing a semiconductor device, comprising: a sixth step of forming a drain diffusion layer and a source diffusion layer of a DMISFET surrounded by the second impurity diffusion layer. 30. The method of manufacturing a semiconductor device according to claim 29, wherein in the fourth step, ions of the first conductivity type impurity are introduced from a direction having an inclination angle of 30 ° or less with respect to an axis perpendicular to the surface of the semiconductor substrate. A method for manufacturing a semiconductor device, which comprises injecting. 31. The method for manufacturing a semiconductor device according to claim 29, wherein in the first step, first and second conductive type channel structures surrounded by the element isolation are provided on a semiconductor substrate. Second and third for respectively forming the second MISFET
Of the threshold voltage control impurities of the first and second MISFETs are individually implanted into the second and third active regions before the third step. Further, in the third step, a gate insulating film and a gate electrode are formed also on the second and third active regions, and in the fifth step, the first and second MISFETs are formed. Insulator sidewalls are also formed on both side surfaces of the gate electrode, and in the sixth step, source / drain diffusion layers of the first MISFET are also formed, and source / drain diffusion layers of the second MISFET are formed. A method of manufacturing a semiconductor device, further comprising: a step of forming. 32. The method of manufacturing a semiconductor device according to claim 31, wherein at least one of the second and third active regions is formed after the third step and before the fifth step. A method of manufacturing a semiconductor device, further comprising a step of implanting ions of a low concentration first conductivity type impurity using the gate electrode as a mask to form a low concentration source / drain diffusion layer.