JPH09131922A - Recorder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a draft-printing process without increasing printing time and, further, eliminate the need for an expensive CPU. SOLUTION: This recorder writes image data from a host 33 into an image memory 21, reads this, and prints it by a printing head 5. In this case, the recorder is equipped with an ASIC circuit 22 which directly transfers the image data from the host 33 to the image memory 21 by a DMA processing, the ASIC circuit 22 being provided with a thin-out circuit which thins out image data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording apparatus applied to an ink jet printing apparatus or the like for ejecting ink droplets for printing, and more particularly to receiving print information composed of dot data from a host and printing the dot data. The present invention relates to a recording device that writes data into a storage unit, reads out the written data, and prints with a print head.

[0002]

2. Description of the Related Art In a conventional print recording apparatus, the CPU of the print recording apparatus is mainly responsible for receiving the print data from the host computer and writing the print data in the storage means. Further, in this type of print recording apparatus, draft printing processing is possible for the purpose of saving ink, but the CPU was also in charge of the data thinning processing required for this purpose. Draft printing does not print all the print dot data, but thins out the print dot data according to a predetermined rule to perform rough printing.
It is used for trial printing.

[0003]

However, in the conventional print recording apparatus, it goes without saying that during the process of receiving the print data, writing the data into the storage means, and the data thinning process,
Since the CPU cannot perform other processing, there is a problem that the printing time is significantly increased as a result. Here, it is possible to employ a CPU with a high processing speed, but this is not appropriate as a solution because the manufacturing cost increases as the CPU becomes expensive.

The present invention has been made in order to solve the above-mentioned problems, and realizes the draft printing process without increasing the printing time, and further, it does not require the use of an expensive CPU. The purpose is to provide.

[0005]

In order to achieve the above object, an ink jet type printing recording apparatus according to the invention of claim 1 is
Receives print information from the host as dot data, writes the dot data as image data in the storage means,
In a recording device for reading image data written in the storage means and printing a plurality of raster lines as one line by a print head, a CPU for program-controlling the operation of each part of the device, and image data read from the storage means Based on a direct memory access (DMA) command from the CPU, which is interposed between the print head driver for driving the print head based on the above, the host, the CPU, the storage means and the print head driver. A hard logic circuit for directly transferring information to the storage means, and the hard logic circuit has a thinning circuit for thinning data when writing or reading data to or from the storage means. In the above configuration, since the hard logic circuit that directly transfers the print information from the host to the storage unit based on the DMA command is provided, the load on the CPU is reduced, and the process as a whole is speeded up. Moreover, since the hard logic circuit has a thinning circuit for thinning data,
In this respect as well, the load on the CPU is further reduced.

According to a second aspect of the present invention, there is provided an ink jet print recording apparatus, wherein:
The thinning circuit has a mask register in which mask data is written based on the thinning designation from the CPU. In the above configuration, since appropriate mask data can be written in the mask register, the degree of freedom in thinning processing increases.

According to a third aspect of the present invention, in the ink jet print recording apparatus according to the first or second aspect, the thinning circuit performs thinning processing on adjacent raster lines in a staggered manner. . In the above configuration, since the thinning processing is performed in a staggered manner on the adjacent rasters, it is possible to significantly reduce the consumption of ink without significantly degrading the image quality.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which an ink jet type print recording apparatus of the present invention is embodied in a printer will be described below with reference to the drawings. FIG. 1 is a diagram showing an external appearance of a printer 1 according to an embodiment of the present invention, in which a printing mechanism 2, a paper feeding mechanism 3, a purging device 4 and the like are shown. The printing mechanism 2 includes an inkjet print head 5
And the ink cartridge 7 for supplying ink to the print head 5, and the head unit 6 and the ink cartridge 7 are mounted on a carriage 8. Here, the carriage 8 is driven by a carriage motor 10 via a belt 9, and moves horizontally along a carriage shaft 11.
The print head 5 has a plurality of nozzles, for example, 64 nozzles in one column, and ejects ink from the nozzles corresponding to the movement of the carriage 8.

The paper feed mechanism 3 moves the print paper supplied from the paper feed cassette or the manual paper feed section while facing the print head 5, and the platen roller 12 and
Pressure roller 13 and line feed (LF) motor 31
(See FIG. 2) and the like. The printing paper supplied from a paper feed cassette or the like is held in pressure contact with the platen roller 12 and the pressure roller 13, and is moved in accordance with the rotation of the line feed motor 31. The purging device 4 eliminates the occurrence of ejection failure due to the generation of air bubbles inside the print head 5 or the deposition of ink droplets on the ejection surface during the use of the print head 5 to restore a good ejection state. Device. A cap 14 is provided at the tip of the purging device 4, and when the cap 14 covers the print head 5, a negative pressure is generated by a pump to suck the defective ink inside the print head 5. The print head 5 is recovered.

FIG. 2 is an internal block diagram showing the control system of the printer 1. An image memory (storage means) 21 for temporarily storing print data, and an ASIC (application. Application) for executing data access to the image memory 21.
A specific integrated circuit) circuit 22 and a CPU 23 that controls each part of the printer are shown. The CPU 23 includes the ASIC circuit 22 and the ROM 2
4, RAM 25, operation panel 26, motor driver 2
7, 28, a paper sensor 29, and an origin sensor 30 are connected to each other to exchange necessary data with each unit. The motor driver 27 drives the carriage motor 10, and the motor driver 28 drives the line feed motor 31. Further, the paper sensor 29 is
Origin sensor 3 is a sensor that detects the presence or absence of printing paper.
Reference numeral 0 is a sensor that detects that the print head 5 is at the origin position. The ASIC circuit 22 is, for example, a hard logic circuit such as a gate array (G / A) or a standard cell, and is connected to the host computer 33 via the Centro IF unit 32. In addition, Centro IF
The unit 32 sends 8-bit print data to the ASIC circuit 22 according to the Centronics standard specifications. ASIC circuit 22
Is also connected to a head driver 34 that drives the print head 5, and print data 34a that is serial data.
And the transfer clock 3 that takes the transfer timing of the print data
4b and a print clock 34c for adjusting the print timing of the print head 5 are output. The ASIC circuit 22 includes a CPU 23 via an address bus 23a and a data bus 23b.
Is connected to In addition, the ASIC circuit 22 is a CPU
23 while receiving the print timing signal 23d from the
An interrupt signal 23c is supplied to U23. The print timing signal 23d is a signal notifying that the carriage 8 has reached the print start point in the constant velocity area, and the interrupt signal 23c is the D signal from the ASIC circuit 22.
These signals are related to MA (direct memory access) processing, data thinning processing, and the like, and details will be described later.

FIG. 3 is a circuit block diagram showing the ASIC circuit 22 shown in FIG. 2 in more detail. AS shown
The IC circuit 22 is a controller 35 that controls each part of the circuit.
A thinning circuit 36 for thinning print data from the host computer 33 and a data transfer unit 37 for sending the print data 34a to the head driver 34 are mainly provided. The controller 35 uses the image memory 2
In addition to outputting the control signal 21a for controlling the data write (WR) and read (RD) of 1, the image memory 21
A predetermined value is set in the read address register 38 that determines the read address of Also, write address
The address value of the register 39 is incremented at a predetermined timing. The read address register 3
8 and the write address register 39 are connected to the image memory 21 via the internal address bus 21b. The controller 35 is also connected to the thinning circuit 36, and instructs the thinning circuit 36 whether or not thinning processing is necessary according to the level of the 1-bit thinning designation signal 36a. Further, the controller 35 uses the Centro IF unit 32.
Receives the strobe (stb) signal 32b output from the device, detects the reception timing of the data 32c, and outputs the interrupt inhibit signal 40a to the AND gate 40 receiving the same strobe signal 32b.

The data transfer section 37 includes an image memory 21.
Is a circuit for receiving the print data from the head driver 34 and sending it to the head driver 34, and operates based on the transfer command 37a from the controller 35 and the data latch signal 37b. The controller 35 sends the transfer command 37a to the CPU 23.
Timing signal 2 that indicates the timing to start printing from
After receiving 3d, the data transfer unit 37 outputs the print data in response to the transfer command 37a, and then outputs the print clock 34c based on the encoder signal of the carriage 8. By doing so, ink is ejected from the print head 5 in accordance with the traveling of the carriage 8. The data transfer unit 37 is connected to the image memory 21 via the internal data bus 21c, and receives the data of 64 nozzles necessary for one printing read by the controller 35 by receiving the data latch signal 37b. This print data 3
4a is serially transferred to the head driver 34 based on the transfer command 37. The interface control unit 41 controls the data 3 transferred from the host side via the Centro IF unit 32.
The reception data 32c, which is a portion for receiving 2c and is parallel data of 8 bits, is sent to the CPU 23 and the thinning circuit 36. The interface control unit 41 uses the ACK
Controlled by a control signal 32a such as BUSY or BUSY, the data 32c is received from the centro IF unit 32 in synchronization with the strobe signal 32b. The address decoder 42 is C
This is a circuit that decodes the address signal 23a sent from the PU 23 and selects a corresponding register or the like, and the data (register value or command content) sent to the data bus 23b is set in each selected register or the like. It In addition,
The thinning circuit 36 is provided with a mask register for receiving the 8-bit thinning pattern output from the CPU 23, and the controller 35 is provided with a 1-bit thinning command register and a 1-bit DMA command register. A predetermined address value is assigned to the register. Then, the thinning-out designation signal 36a is output from the controller 35 in response to the output of the thinning-out instruction register, the DMA processing of the controller 35 is executed based on the output of the DMA instruction register, and the interrupt inhibit signal 40a is sent to the AND gate 40. Is output.

FIG. 4 shows the internal structure of the thinning circuit 36 shown in FIG. As shown, the thinning circuit 3
Reference numeral 6 denotes a mask register 43 for storing the above-described thinning pattern and NOT for logically negating the thinning designation signal 36a.
The unit 44, an OR gate line 45 provided at the output of the mask register 43, and an AND gate line 46 for the print data 41a from the interface control unit 41. As is apparent, when the thinning designation signal 36a is at L level, the print data 41a from the interface control unit 41 passes through the AND gate row 46 as it is, but when the thinning designation signal 36a is at H level,
The print data 41a is masked by the thinning pattern from the mask register 43.

FIG. 5 shows the internal structure of the head driver 34 shown in FIG. Head driver 34
Is the print data 34a sent from the data transfer unit 37.
Is a circuit for driving the print head 5 based on the parallel conversion section 47, the AND gate array 48, and the driver 49.
It is composed of The parallel conversion unit 47 is a circuit that takes in the print data 34a that is serially transferred in synchronization with the transfer clock 34b, and converts 64-bit (for one nozzle of one vertical column of the print head) serial data into parallel data. Then, this parallel data is synchronized with the print clock 34c, and the AND gate train 4
8 is transmitted to the driver 49, and ink is ejected from the print head 5 in a corresponding dot pattern.

Next, the operation contents of the draft printing process of the printer having the above configuration will be described. When the computer user desires the draft printing, the “thinning-out command” is sent from the host computer 33. Next, a 1-byte "transfer command" and a 2-byte "transfer byte number" are sent out, and subsequently the print data is transferred. Note that FIG. 6 illustrates the data format of the data transmitted from the host computer 33 to the interface control unit 41 via the Centro IF unit 32. A3 now
Use paper in portrait orientation (A4 paper may be landscape orientation)
Assuming the case of printing with a dot density of 80 bpi,
Approximately 204 at maximum in the short side of 297 mm of A3 paper
Since it is possible to print 8-bit dots, in this example, the "transfer byte number" for each raster that constitutes one row with 64 rasters will be described as "256". That is, the host computer 33 uses one "transfer command".
256 bytes for one raster (2048 bits)
Will send the print data of.

By the way, in the initial state, the ASIC
The interrupt inhibit signal 40a (see FIG. 3) of the circuit 22 is at H level. Therefore, when a "thinning-out command" or "transfer command" is transferred from the host computer 33, an interrupt signal 23c for centro data reception is added to the CPU 23 in response to the strobe (stb) signal 32b at that time. . FIG. 7 shows the contents of the interrupt processing program, which will be described below with reference to the flowchart of FIG. When interrupted, CP
The U23 first determines whether or not the operation mode at that time is the "standby mode" (S1). Since it is in the “standby mode” at the timing of receiving various commands, the CPU 23 next determines whether the received command is a “transfer command” (S2). Assuming that the "thinning-out command" has been received, the CPU 23 determines that the masking register 4 of the thinning-out circuit 36 is present after the determination in step S3.
A predetermined thinning pattern is written in 3 (S4). An appropriate value can be set as the thinning pattern, but in this example, it is assumed that "10101010" is set. After that, the CPU 23 stores 1-bit data “1” of “with thinning command” in the thinning command register in the controller 35.
Is written so that the H-level thinning-out designation signal 36a is output, and the interrupt processing is finished (S5). After that, when the host computer 33 sends a "transfer command", the CPU 23 starts the interrupt processing of FIG. 7 again. Even in this state, the operation mode is "standby mode".
Therefore, the process shifts from step S1 to step S2, and then the CPU 23 transitions the operation mode from the "standby mode" to the "transfer byte number acquisition mode" and ends the interrupt processing (S6). .

As shown in FIG. 6, the host computer 33
Then sends the "number of transfer bytes" consisting of 2 bytes. In this state, the mode is the "transfer byte number acquisition mode", and therefore the process proceeds from step S1 to step S7. However, since the first byte of the "transfer byte number" has been received, it is determined in step S8. Finish interrupt processing. At the time of the next interrupt, the second byte “transfer byte number” is received. Therefore, after the determination of steps S1 → S7 → S8, the received 2-byte transfer byte number “256” is stored in the corresponding register in the controller 35. Save (S
9). The head write address value of the image memory 21 is set in the write address register 39 (S
9). Subsequently, the CPU 23 causes the ASIC circuit 22 to DM
Although the A command is sent (S10), specifically, 1-bit data "1" for "DMA execution" is set in the DMA command register in the controller 35. Then, the controller 35 starts the DMA processing with this, and sets the interrupt prohibition signal 40a to the L level.
No interruption from the Centro IF unit 23 is applied to No. 3. After the above interrupt prohibition processing, the CPU 23
Switches the operation mode from the "transfer byte count acquisition mode" to the "transfer mode" and ends the interrupt processing (S1).
1). After that, the centro IF unit 32 sequentially sends the print data, but the CPU 23 is not interrupted,
Data writing to the image memory 21 is started by the DMA processing of the controller 35. That is, after that, the ASIC circuit 22 does not exchange data with the CPU 23, and the buses 23a, 2 of the CPU 23 are not exchanged.
The print data write processing is performed via the local buses 21b and 21c independent of 3b.

Further, a predetermined data thinning process is performed in the thinning circuit 36 prior to the data writing process. Specifically, the print data 32c from the Centro IF unit 32 is ANDed via the interface control unit 41.
Although it is supplied to the gate row 46 (FIG. 4), in this example, “10” is set in the mask register 43 in step S4 of FIG.
Since 101010 "is set, the print data" XXXXXXXX "output by the interface control unit 41 is masked and sent to the internal data bus 21c. Then, the masked print data" XX " “× 0 × 0 × 0” is stored in the address designated by the write address register 39. The same applies to the following, and the print data 32c sent from the centro IF unit 32 is irrelevant to the CPU 23. , And is stored in the image memory 21 under the address designation of the write address register 39 which is sequentially incremented under the control of the controller 35.
As described above, during the DMA operation, the CPU 23 can freely use the address bus 23a and the data bus 23b, so that the separate processing unrelated to the data reception from the Centro IF unit 32 can be performed, and the processing can be smoothly performed as a whole. And speeding up are realized. By the above DMA processing,
In this example, the print data (256 bytes) of the first raster corresponding to the uppermost nozzle of the first row is written in the image memory 21 from address 0000H to 00FFH, and finally the DMA command register Is cleared to “0”, but after writing the 255th byte, the controller 35
Since 0a changes from the L level to the H level, the CPU 23 is interrupted in response to the strobe signal 32b for the print data of the 256th byte. At the time of this interrupt, the operation mode is the "transfer mode", so the CPU 23 makes a determination of steps S1 to S7,
The operation mode is changed from the "transfer mode" to the "standby mode" and the interrupt processing is finished (S12).

By the above processing, the print data (256 bytes) of the first raster of the first row is stored in the image memory 21.
Is written. The same applies to the print data of the second raster.
The print data of 256 bytes is sent according to the data format of. When the "thinning-out command" is received, the interrupt prohibition signal 40a is at the H level, so C
The PU 23 is interrupted. Since the operation mode at this time is the "standby mode", the CPU 23 executes the process of steps S1 → S2 → S3 → S4 → S5 of FIG.
t data “1” is written and the mask register 43
Write the thinning pattern to. Since the thinning pattern of the previous time (first raster) was "10101010", this time (second raster), the thinning pattern was inverted to "0101010".
1 "is set. Next, when the" transfer command "is received, the CPU 23 shifts the operation mode from the" standby mode "to the" transfer byte number acquisition mode "by the processing of steps S1 → S2 → S6. When the first byte of the "number of transfer bytes" is received, steps S1 → S7 →
When the interrupt processing is completed in the determination of S8 and the second byte is received, steps S1 → S7 → S8 → S9 → S10.
→ Transition to the "transfer mode" through the process of S11. At this stage, the number of transfer bytes "256" is stored in the register in the controller 35, and the write address
The head write address value (0100H corresponding to the second raster in this example) is set in the register 39 (S
9). Further, as the 1-bit data “1” of “DMA execution” is set in the DMA command register in the controller 35, the interrupt prohibition signal 40a becomes L level (S
10).

Thereafter, the Centro IF unit 32 sends the print data in sequence, but the CPU 23 is not interrupted and the print data of 256 bytes of the second raster is written in the image memory 21 by the DMA processing. At this time, since the print data "XXXXXXXX" is masked by the thinning pattern "01010101",
The masked print data "0x0x0x0x" is stored in the image memory 21 at addresses 0100H to 01FFH. By the above DMA processing, the print data (256 bytes) of the second raster of the first row is stored in the image memory 21.
However, like the previous time, the interrupt inhibit signal 40a is changed to the H level after the writing of the 255th byte is completed. Therefore, in response to the strobe signal 32b for the print data of the 256th byte, the CPU2
3 is interrupted, and the CPU 23 proceeds to step S1 →
The operation mode is changed to the “standby mode” by the processing of S7 → S12. Thereafter, the printing dot data of odd-numbered rasters is exactly the same, and the thinning pattern "10101010"
The print dot data of the even-numbered raster masked by 10 "is masked by the thinning pattern" 01010101 "and stored in the image memory 21. Thereafter, the print dot data of one line (one run of the print head) That is, at the stage where the print data for 64 rasters has been stored,
The CPU 23 outputs a preparation instruction for printing to the controller 35 of the ASIC circuit 22 and also causes the carriage 8 to start traveling. Then, when the carriage 8 reaches a constant speed (at the time of delivery to the print start position), the print timing signal 23d for starting print is sent to the controller 35 of the ASIC circuit 22. In response to this, A
The controller 35 of the SIC circuit 22 sequentially reads 64-bit data corresponding to the nozzles in one vertical column of the print head 5 from the print data stored in the image memory 21. Then, this is serially transferred to the head driver 34 via the data transfer unit 37. Further, the print clock 34c generated based on the encoder signal of the carriage 8 is output to the head driver 34. Based on the print clock 34c, the head driver 34 outputs the print data serially transferred immediately before that in parallel all at once, so that the piezoelectric elements corresponding to a total of 64 nozzles are selectively driven to eject ink. Make it jet.

FIG. 8 illustrates the relationship between the print head 5 having 64 nozzles and the vertically long A3 paper 50. If the 1-byte data at the address 0000H in the image memory 21 corresponds to 8 dots from the upper left corner of the paper to the right, and if the print head 5 runs once,
This indicates that printing is performed corresponding to the total print data of 64 × 256 bytes from the address H to the address 3FFFH. When the print head 5 completes one run, the line feed (LF) motor 31 feeds the paper by the print width of the print head 5. FIG. 9 shows the print position of portrait A3 size paper and the address value of the image memory 21 corresponding to the print position. In addition, the figure shows a state in which all black printing is drafted. FIG.
As shown in (a), the upper left of the portrait A3 paper corresponds to the address 0000H of the image memory, and the next position (the left end of the second raster) corresponds to the address 0100H of the image memory. Further, in the case of printing the entire black color, originally, each data in the image memory 21 is “111111”.
Although it should be 11 ", the odd-numbered rasters are masked by the thinning-out pattern" 10101010 ", and the print data of the even-numbered rasters are masked by the thinning-out pattern" 01010101 ", as shown in FIG. 9B. The print data is thinned in a zigzag pattern, and the print processing is performed based on this data, so the print surface is as shown in FIG.
It becomes a staggered shape like. In addition, in FIG.
A total of 64 black and white marks surrounded by a double frame at the left end show the correspondence with the nozzles of the print head 5 in a single vertical line.

Although one embodiment of the present invention has been described above, the present invention is not limited to this, and various modifications can be made. For example, in the above-described embodiment, the data thinning process is performed before writing the print data to the image memory 21, but it is also possible to thin the data by using the same mask data after reading the print data. In addition, the “thinning command” is transferred from the host computer to the printer side every time each raster data transfer is performed, and the thinning pattern is rewritten each time the “thinning command” is received. For the "thinning command",
It is not always necessary to transfer from the host computer to the printer side. For example, when print data of 64 rasters for one line is sequentially transferred for each raster subsequent to one “thinning command”, mask data for thinning out for each raster is determined by the CPU 23 on the printer side. May be rewritten. Further, in the above-described embodiment, the image memory 000 is displayed from the upper left corner to the upper right corner of the portrait A3 paper.
Although the addresses 0H to 00FFH are associated with each other, the correspondence relationship may be replaced with that shown in FIGS. 10 and 11. In this embodiment, print data of 8 bytes downward from the upper left corner of the vertically long A3 paper 50 is stored at addresses 0000H to 0007H (see FIG. 11A). In the case of such a correspondence relationship, not only the print data can be written in the image memory 21, but also the print data can be read out in the order of addresses. Therefore, the read address register 38
It is preferable that only incrementing is sufficient. However, in order to realize the staggered thinning-out shown in FIG. 11C, the thinning-out pattern is changed from "10101010" to "01010101" every time 8 bytes of print data is stored.
→ It is necessary to sequentially switch to “10101010” → ....

In the case of this embodiment as well, the staggered thinning processing is performed as in the embodiment shown in FIGS.
Draft printing with print quality as shown in FIG. 12 can be realized. It should be noted that FIG. 12 shows a state in which the print head 5 having 64 nozzles moves in the lateral direction and prints on the entire black print surface. FIG. 13 shows a state in which the rhombus-shaped printing surface is draft-printed, and thinned in a staggered manner to realize a preferable print image quality. In each of the above embodiments, the thinning pattern is set to "1010101".
The zigzag draft printing was realized by switching to "0" and "01010101".
This method may be unified to 010 ". According to this method, the print quality is somewhat deteriorated because the positions of the thinned dots are aligned, but it is advantageous in terms of circuit and control because it is not necessary to switch the thinning pattern. In addition, FIG.
In the example shown in FIG.
It is not necessary to be limited to “010” and “01010101”. For example, a thinning pattern of “11111111” is used for odd-numbered rasters and “00000” for even-numbered rasters.
A thinning pattern of 000 "may be used.

[0024]

As described above, according to the ink jet print recording apparatus of the first aspect of the present invention, the hard logic circuit for directly transferring the print information from the host to the storage means based on the DMA command is provided. Therefore, the load on the CPU is reduced, and the processing is speeded up as a whole. Further, since the hard logic circuit has a thinning circuit for thinning data, the burden on the CPU can be further reduced in this respect as well. Further, according to the ink jet print recording apparatus of the second aspect of the present invention, in addition to the above effects, appropriate mask data can be written in the mask register, so that the degree of freedom of the thinning process is increased. According to the ink jet type print recording apparatus of the third aspect of the present invention, in addition to the above effects, since the thinning processing is performed in a staggered manner on the adjacent rasters, the ink consumption is reduced without deteriorating the image quality. It can be greatly suppressed.

[Brief description of the drawings]

FIG. 1 is a schematic external view of an inkjet printer according to an embodiment of the present invention.

FIG. 2 is a block diagram of a control system of the inkjet printer.

FIG. 3 is an internal block diagram of an ASIC circuit of the inkjet printer.

FIG. 4 is a specific circuit configuration diagram of a thinning circuit in a control system.

FIG. 5 is a block diagram illustrating a configuration of a head driver.

FIG. 6 is a diagram showing a format of data transferred from a host to a printer.

FIG. 7 is a processing flow when a CPU receives a data reception interrupt.

FIG. 8 is a diagram showing a positional relationship between a print head and A3 printing paper.

FIG. 9 is a diagram showing a correspondence relationship between an image memory and A3 printing paper.

FIG. 10 is a diagram showing a modification of the positional relationship between the print head and A3 printing paper.

FIG. 11 is a diagram showing a modification of the correspondence relationship between the image memory and A3 printing paper.

FIG. 12 is a diagram showing print quality by draft printing.

FIG. 13 is a diagram showing print quality by draft printing.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 printer (recording device) 5 print head 21 image memory (storage means) 22 ASIC circuit (hard logic circuit) 23 CPU 33 host computer (host) 34 head driver 36 thinning circuit 43 mask register

Claims (3)

[Claims] 1. A print information is received from a host as dot data, the dot data is written as image data in a storage means, the image data written in the storage means is read, and a plurality of rasters are printed as one line. In a recording apparatus that prints by a head, a CPU that program-controls the operation of each unit of the apparatus, a print head driver that drives the print head based on image data read from the storage unit, the host, the CPU, the storage unit, and the print head A hard logic circuit which is interposed between the drivers and which directly transfers print information from the host to the storage means based on a direct memory access (DMA) command from the CPU, wherein the hard logic circuit is Data decimation processing when writing or reading data to or from storage means Recording apparatus characterized by having a thinning circuit for performing. 2. The recording apparatus according to claim 1, wherein the thinning circuit has a mask register in which mask data is written based on thinning designation from the CPU. 3. The recording apparatus according to claim 1, wherein the thinning circuit thins the adjacent raster lines in a staggered manner.