JPH09130253A - Multi-channel a/d converter and digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily adjust the gain of digital signals outputted from a multi-channel A/D converter. SOLUTION: Analog signals are converted into the digital signals by ΔΣmodulators 3a and 3b and digital decimation filters 4a and 4b, a prescribed coefficient is multiplied with the digital signals outputted from the digital decimation filters 4a and 4b in multipliers 5a and 5b and thus, the output level of the digital signals outputted from this multi-channel A/D converter is optimally adjusted.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a multi-channel A /
The present invention relates to a D converter and a digital signal processing device, and is particularly suitable for use in a digital audio device such as a digital audio tape recorder and a mini disk player.

[0002]

2. Description of the Related Art In recent years, in digital audio equipment such as a digital audio tape recorder (DAT) and a mini disk player (MD), an A / D converter for converting an analog signal into a digital signal, for example, ΔΣ
In some cases, an oversampling A / D converter including a modulator and a digital decimation filter is used.

Such an oversampling type A /
The D converter performs oversampling to push quantization noise to the high frequency side and reduce noise in the audio band.

FIG. 2 is a block diagram of a conventional digital signal processing apparatus provided with a plurality of oversampling type A / D converters as described above. The digital signal processing device shown in this figure is an oversampling type multi-channel A / D converter (hereinafter referred to as "multi-channel A / D converter") indicated by a broken line.
21 and a digital signal processor 22.

The multi-channel A / D converter 21 converts a plurality of analog signals input from the input terminals 25a and 25b into a plurality of multi-bit digital signals, and the digital signal processor 22 is a multi-channel A / D converter. 21
The digital signal output from the device is subjected to processing such as compression and correction and then output.

The multi-channel A / D converter 21 has a Δ
It is composed of Σ modulators 23a and 23b and digital decimation filters 24a and 24b. The ΔΣ modulators 22a and 22b are configured by different types of ΔΣ modulators (for example, secondary and tertiary ΔΣ modulators), and have 1-bit corresponding to the analog signal input from the input terminals 25a and 25b. It is designed to generate pulse train data.

The digital decimation filter 24a,
24b is composed of, for example, an FIR low pass filter, and is generated by the ΔΣ modulators 23a and 23b.
Quantization noise and the like of harmonic components included in a bit pulse data train are removed, and thinning operation is performed to output multi-bit digital signals. The memories 26a and 26b store impulse response coefficients supplied to the digital decimation filters 24a and 24b, respectively.

In the conventional digital signal processing apparatus thus constructed, for example, in a karaoke apparatus or the like, a voice signal input from a microphone and a musical tone signal such as karaoke can be converted into digital signals and output. It is done like this.

By the way, the multi-channel A as described above
Since the ideal noise floor level of the oversampling A / D converter that constitutes the / D converter 21 is constant, when the level of the analog signal that is normally input increases, as shown in FIG. The noise-distortion characteristic of the ΔΣ modulator is improved, and the noise distortion rate (THD + N) with respect to the input signal level is reduced.

That is, theoretically, the noise distortion rate (THD + N) with respect to the input signal level is improved until the input level of the analog signal reaches A ₁ as shown by the broken line, and the input level reaches A ₁ . Then, the waveform is clipped and deteriorates rapidly.

However, such a ΔΣ modulator is
Due to the property peculiar to high-order ΔΣ modulation, it has a noise distortion characteristic that distortion and noise increase when the level of the input analog signal increases and the modulation rate approaches 1, and it is actually input. When the analog signal corresponding to the maximum input level reaches near the maximum input level A ₁ , distortion and noise increase, and the noise-distortion characteristic rapidly deteriorates as shown by the solid line in FIG.

Therefore, the maximum input level A ₁ is applied to the ΔΣ modulator.
In order to prevent the noise distortion characteristic from deteriorating when an analog signal in the vicinity is input, for example, US Pat.
No. 1 proposes a method of setting the gain of the impulse response coefficient of the digital decimation filter to 1 or more.

In this case, when the input level of the analog signal input to the ΔΣ modulator reaches A ₂ (the input level at which the noise-distortion characteristic shown in FIG. 3 is best), the digital output from the digital decimation filter is output. The impulse response coefficient multiplied by a predetermined gain is supplied to the digital decimation filter so that the output level of the signal becomes full scale.

[0014]

However, since the conventional digital signal processing device as shown in FIG. 2 is composed of a plurality of oversampling type A / D converters, for example, the type (order) is Different Δ
If the Σ modulators 23a and 23b are used, the ΔΣ modulator 23
When the noise distortion characteristics differ depending on a and 23b, and ΔΣ modulation is performed in a range where distortion does not occur, for example, the modulation rate of the ΔΣ modulator 23a differs from 0.8, and the modulation rate of the ΔΣ modulator 23b differs from 0.5. Sometimes.

Therefore, even if the same digital decimation filters 24a and 24b are used, the input 1
Since the levels of the bit pulse train data are different, the impulse response coefficients output from the memories 26a and 26b are, for example, 1.25 and 2.0 according to the modulation rate.
It is necessary to multiply by the gain of the above and supply to the digital decimation filters 24a and 24b.

However, since such impulse response coefficients are stored in the memories 26a and 26b, the ΔΣ modulator 23a,
When the value of 23b is changed, it is difficult to adjust it so that the gain is optimum.

The present invention has been made to solve such a problem, and an object thereof is to make it possible to easily adjust the gain of a digital signal output from a multi-channel A / D converter.

[0018]

To achieve the above object, a plurality of modulating means for generating and outputting a 1-bit pulse data train from an input analog signal and a harmonic contained in the 1-bit pulse data train. A plurality of digital filter means for removing noise of wave components and generating and outputting a multi-bit digital signal, and adjusting the output level of the multi-bit digital signal according to the coefficient input from the coefficient input terminal. A multi-channel A / D converter is configured with a plurality of multiplying means capable of performing the above.

A multi-channel A / D converter,
A digital signal processing device is provided with digital signal processing means for processing a plurality of digital signals output from the multi-channel A / D converter.

According to the present invention, since the multiplication means multiplies the digital signal output from the digital filter means by a predetermined coefficient to adjust the output level, the impulse response coefficient supplied to the digital filter means is adjusted. The level of the output digital signal can be adjusted without changing the value.

[0021]

1 is a block diagram showing an example of a digital signal processing apparatus provided with a multi-channel A / D converter according to an embodiment of the present invention. The digital signal processing device shown in this figure is composed of a multi-channel A / D converter 1 and a digital signal processor 2 shown by broken lines, and the multi-channel A / D converter 21 is inputted from input terminals 6a and 6b. A plurality of analog signals are converted into a plurality of digital signals and output. The digital signal processor 2 is configured to perform processing such as compression and correction on the digital signal output from the multi-channel A / D converter 1 and output the digital signal.

The multi-channel A / D converter 1 is composed of, for example, a one-chip IC, and the ΔΣ modulators 3a and 3b and the digital decimation filters 4a and 4 are used.
b, multipliers 5a and 5b are provided. ΔΣ modulator 3
a and 3b are different types of ΔΣ modulators (for example, 2
Next, third-order ΔΣ modulator), and is configured to generate predetermined 1-bit pulse train data according to an analog signal input from the input terminals 6a and 6b.

Digital decimation filters 4a, 4
b is composed of, for example, an FIR low-pass filter or the like, removes quantization noise of harmonic components contained in the 1-bit pulse data train generated by the ΔΣ modulators 3a and 3b, and performs thinning-out operation. ΔΣ modulators 3a, 3
A multi-bit digital signal is output at a sampling frequency lower than the sampling frequency of b.

The multipliers 5a and 5b convert the digital signals output from the digital decimation filters 4a and 4b into
For example, a coefficient (hereinafter, referred to as "microcomputer") (not shown) or the like is multiplied by coefficients supplied via coefficient input terminals 7a and 7b, and a digital signal of a predetermined level is output. The memory 8 stores impulse response coefficients supplied to the digital decimation filters 4a and 4b, respectively. The gain of the impulse response coefficient stored in the memory 8 is set to 1 or less.

Hereinafter, the multi-channel A / D converter 1 constituting the digital signal processing apparatus according to the present embodiment will be described.
Will be described. If the orders of the ΔΣ modulators 3a and 3b provided in the multi-channel A / D converter 1 are different, the noise-distortion characteristics of the ΔΣ modulators 3a and 3b are also different. Therefore, ΔΣ is most efficient in a range in which no distortion occurs. Even when the modulation is performed, the modulation rate differs depending on each ΔΣ modulator. Even if the types (orders) of the ΔΣ modulators are the same, the modulation rate may differ depending on the configuration, but the same consideration will be applied at this time as well.

Here, for example, the ΔΣ modulator 3a is a secondary Δ
The Σ modulator has a modulation rate of 0.8, and the ΔΣ modulator 3b has a third-order Δ
Assuming that the modulation rate of the Σ modulator is 0.5, this ΔΣ modulator 3
The 1-bit pulse data train output from a and 3b is
The gain is 0.
8 and 0.5.

The digital signals output from the ΔΣ modulators 3a and 3b are subjected to a convolution operation in the digital decimation filters 4a and 4b and output as a multi-bit digital signal. To digital decimation filters 4a, 4b
If the gain of the impulse response coefficient supplied to the digital decimation filter 4 is, for example, 1.
The gains of the multi-bit digital signals output from a and 4b are 0.
8 and 0.5.

Next, the digital decimation filter 4
The multi-bit digital signals respectively output from a and 4b are input to the coefficient input terminals 7a and 7 in the multipliers 5a and 5b.
It is multiplied by a gain coefficient supplied from a microcomputer or the like (not shown) via b and output.

That is, in the multi-channel A / D converter 1 of the present embodiment, the multipliers 5a and 5b have coefficient input terminals 7a to "1.25" and coefficient input terminals 7b to "2".
By supplying the coefficient of, the digital signal of the same level as the input analog signal is obtained, and the output level of the digital signal is adjusted without changing the impulse response coefficient of the digital decimation filters 4a and 4b. be able to.

Further, for example, the maximum input level A shown in FIG.
ΔΣ modulator 3 when an analog signal near ₁ is input
In order to prevent the deterioration of the noise-distortion characteristics caused by a and 3b, when the level of the analog signal input to the ΔΣ modulators 3a and 3b reaches A ₂ , the multi-channel A / D converter according to the present embodiment. Even when the output level of the digital signal output from 1 is full scale, the multiplier 5
Adjustment can be easily performed by changing the values of the coefficients supplied to a and 5b.

In the digital signal processing apparatus according to this embodiment, the multipliers 5a and 5b are used for multi-channel A.
Although the case where the digital signal processor 1 is provided in the / D converter 1 has been described, the present invention is not limited to this.
Alternatively, the same processing may be performed.

[0032]

As described above, since the multi-channel A / D converter of the present invention is provided with the multiplying means for adjusting the gain of the digital signal output from the digital filter means, this multiplying means is provided. By inputting a desired coefficient, the output level of the digital signal can be easily adjusted. Further, since the impulse response coefficients of a plurality of digital filter means can be set to the same value, it is possible to reduce the memory etc. for storing the impulse response coefficients.
There is also an effect that the circuit scale and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a digital signal processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a block diagram of a conventional digital signal processing device.

FIG. 3 is a diagram showing noise distortion characteristics with respect to an input signal of a ΔΣ modulator.

[Explanation of symbols]

 1 Multi-channel A / D converter 2 Digital signal processor 3a, 3b ΔΣ modulator 4a, 4b Digital decimation filter 5a, 5b Multiplier 6a, 6b Input terminal 7a, 7b Coefficient input terminal 8 Memory

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Higashi Kawabe 134 Sony LSI Design Co., Ltd. 134 Kobe-cho, Hodogaya-ku, Yokohama-shi, Kanagawa

Claims (4)

[Claims] 1. A plurality of modulation means having different orders or modulation rates for generating and outputting a 1-bit pulse data train from an input analog signal, and noise of a harmonic component included in the 1-bit pulse data train. And to adjust the output level of the multi-bit digital signal according to the gain coefficient input from the coefficient input terminal, and the digital decimation filter means that generates and outputs the multi-bit digital signal. Multi-channel A /, characterized by comprising a plurality of multiplying means capable of
D converter. 2. The multi-channel A / D converter according to claim 1, wherein the plurality of digital decimation filter means have the same gain coefficient. 3. A plurality of modulating means having different orders or modulation rates for generating and outputting a 1-bit pulse data train from an input analog signal, and noise of a harmonic component contained in the 1-bit pulse data train. And to adjust the output level of the multi-bit digital signal according to the gain coefficient input from the coefficient input terminal, and a plurality of digital decimation filter means for generating and outputting the multi-bit digital signal. A digital signal processing device comprising: a plurality of multiplying units capable of performing the above; and a digital signal processing unit that performs a predetermined process on the digital signals output from the plurality of multiplying units and outputs the digital signals. 4. The digital signal processing apparatus according to claim 3, wherein the plurality of digital decimation filter means have the same gain coefficient.