JP3416477B2 - Delta-sigma D / A converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delta-sigma type D / A converter which realizes high conversion accuracy by oversampling and which is suitable for use in audio equipment and the like.

[0002]

2. Description of the Related Art In a digital audio device such as a compact disc player, analog voice is sampled at a predetermined frequency and recorded as digital data of an appropriate number of bits. During playback, the digital data read from the recording medium such as a compact disc is D /
The analog signal is restored by the A converter and reproduced as an audio signal through the amplifier and the speaker. At the time of reproducing the digital data, it is desired to minimize the conversion error of the D / A conversion to suppress the distortion of the reproduced signal, and various D / A conversion methods capable of obtaining high conversion accuracy can be dealt with. It is considered.

FIG. 4 is a block diagram showing the configuration of a signal processing device used in a conventional audio device or the like. The signal processing device includes a digital filter 1, a clipping circuit 21, and a D / A converter 22.

The digital filter 1 emphasizes the frequency of a specific band or shifts the phase of the digital data DG1 of a plurality of bits by performing a predetermined calculation on the digital data Din input at a constant cycle. Output. Normally, the digital filter 1 is increased in the number of output bits in order to prevent data overflow in arithmetic processing.

The clip circuit 21 converts the digital data DG1 input from the digital filter 1 into a D / A converter 22.
The digital data DG5 is output while being limited to the convertible range. That is, when the digital data DG1 input from the digital filter 1 includes “1” in the upper bits exceeding the number of bits convertible by the D / A converter 22 as a result of the arithmetic processing by the digital filter 1, the data is Replace with the maximum value in the convertible range and digital data DG
5 is output.

The D / A converter 22 has a plurality of bits (for example, 1
6-bit digital data DG5 is converted into an analog signal AN and output. For example, as shown in FIG. 3, the D / A converter 22 is supplied with 0V as a ground voltage and 5V as a power supply voltage.
The maximum amplitude that can be output with respect to the digital data DG5 of all bits "1" or all bits "0" is set so as to have a margin with respect to the ground voltage 0V and the power supply voltage 5V, as shown by the chain line. In this way, D / A
The maximum amplitude that the converter 22 can output is 0 dB (decibels).
Say. The clip level of the clip circuit 21 is set so as to correspond to this 0 dB range.

[0007]

When the D / A converter 22 employs a noise shaping group that biases the quantization noise to a high frequency band, the digital data D
The clip level of the clip circuit 21 is set so that the range that G5 can take is narrower than the convertible range of the D / A converter 22. Regarding the difference between the range that can be taken by the digital data DG5 and the convertible range of the D / A converter 22, the stability of the operation can be improved by setting it large, and the difference can be set by setting it small. Becomes wider. In other words, if the clip level of the clip circuit 21 is set low in order to obtain a reliable operation, the input dynamic range of the D / A converter 22 becomes narrow and the maximum amplitude that can be output becomes small. On the other hand, if the clipping level of the clipping circuit 21 is set to be high in order to increase the maximum amplitude, data overflow easily occurs due to the action of the noise shaping pin group, resulting in the distortion of the waveform of the analog signal AN. .

Therefore, an object of the present invention is to provide a delta-sigma type D / A converter capable of maximizing the output amplitude of an analog signal and reducing the occurrence of distortion of the analog signal. .

[0009]

In order to achieve the above-mentioned object, the invention described in claim 1 is a quantization for converting a first digital data having a large number of bits into a second digital data having a reduced number of bits. The error data indicating the quantization error at the time of quantization obtained from the difference between the circuit and the second digital data with respect to the first digital data is fed back to the input side of the quantization circuit and input at a constant cycle. And a clip circuit for limiting the first digital data to a predetermined number of bits at the input stage of the quantizing circuit. The quantizer circuit operates in a cycle shorter than the input cycle of digital data, and the noise shaping group delays the error data in accordance with the operation cycle of the quantizer circuit. Delta-sigma type D to be fed back to
The / A converter is the gist.

According to a second aspect of the present invention, the pulse width for converting the second digital data having a reduced number of bits into the 1-bit third digital data whose rising period is changed according to the data content. The gist is to further include a modulation circuit and a low-pass filter that smoothes the third digital data and outputs an analog signal.

[0011]

1 is a block diagram showing an outline of a delta-sigma type D / A converter of the present invention.

The digital filter 1 uses the digital data Di.
The digital data DG1 consisting of a plurality of bits (for example, 20 bits) in which the frequency of a specific band is emphasized or the phase is shifted by inputting n and performing a predetermined calculation is input to the delta-sigma type D / A converter 2. Output. delta·
The sigma type D / A converter 2 comprises a bit compression circuit 3, a pulse width modulation circuit 4, and a low pass filter 5.

The bit compression circuit 3 includes a digital filter 1
The digital data DG1 output from the digital data DG1 is received, and the digital data DG1 is converted into, for example, 3-bit digital data DG2 and output. In the data conversion in the bit compression circuit 3, for example, the sampling frequency fs of 4
The digital data DG1 is oversampled at a frequency of 8 times (48 fs) and quantized again in 7 steps of ± 3 to obtain 3-bit digital data DG2. At this time, quantization noise, that is, digital data DG
The error of the digital data DG2 with respect to 1 is sequentially fed back in each conversion step and added to the input side digital data DG1. Further, the digital data DG1 to which this error has been added is subjected to clipping processing for limiting the maximum value and the minimum value. According to the noise shaping group that feeds back and adds the quantization error, the quantization noise is biased toward the high frequency region side. Therefore, the quantization noise in the low frequency region is significantly reduced, and most of the quantization noise is removed by passing it through the low pass filter.

As shown in FIG. 3, the pulse width modulation circuit 4 is supplied with 0V as a ground voltage and 5V as a power supply voltage. When the input is 3 bits, the pulse width modulation circuit 4 sets 8 clocks in one data conversion period, and of this 8 clock period, the clock period corresponding to the digital data DG2 is set to "1" level (5V). It is configured to output a signal and to output a signal of "0" level (0V) in the remaining clock period. As a result, 1-bit digital data DG3 is obtained which repeats the "1" and "0" level signals in each data conversion period corresponding to the digital data DG2.

The digital data DG3 is R
By passing through the analog low-pass filter 5 composed of a C circuit or the like, a smooth analog signal AN from which high frequency components have been removed is output to the circuit in the next stage.

FIG. 2 is a block diagram showing the configuration of the bit compression circuit 3 which employs a primary noise shaping pin group. The bit compression circuit 3 includes a quantization circuit 11, a subtraction circuit 12, a latch circuit 13, an addition circuit 14, and a clip circuit 15.

The quantizing circuit 11 evaluates the signal level indicated by, for example, 18-bit digital data in seven levels of ± 3, and the corresponding 3-bit digital data DG2.
Is output. The signal on the input side and the signal on the output side of the quantization circuit 11 are respectively input to the subtraction circuit 12, and the data input to the quantization circuit 11 is subtracted from the data output from the quantization circuit 11 to perform quantization. Error data representing noise is calculated. This error data is supplied to the latch circuit 13 functioning as a delay circuit, held for one sampling period, and then input to the adder circuit 14 to be added to the next digital data DG1.

The output of the adding circuit 14 is supplied to the quantizing circuit 11 via the clipping circuit 15. The clipping circuit 15 clips the digital data (the sum of the digital data DG1 and the output of the latch circuit 13) output from the adding circuit 14 within the conversion range of the digital data of the quantizing circuit 11. That is, when the value indicated by the digital data output from the adding circuit 14 indicates a value exceeding the input range of the quantizing circuit 11, the value is set to the quantizing circuit 1.
Replaced with the maximum value of the input range of 1 digital data.
This prevents erroneous conversion of the quantization circuit 11.

Next, the operation of the delta-sigma type D / A converter 2 configured as described above will be described. Now, when the specific frequency band of the digital data Din is emphasized by the digital filter 1, the digital data DG1 is input to the adder circuit 14 of the bit compression circuit 3 without being clipped. The subtraction circuit 12 calculates error data representing the quantization noise based on the signal on the input side and the signal on the output side of the quantization circuit 11. This error data is held in the latch circuit 13 and delayed by one sampling period, then input to the adder circuit 14 and added to the digital data DG1.

Then, only when the digital data output from the adder circuit 14 exceeds the input range of the quantizer circuit 11, the digital data output from the adder circuit 14 is clipped by the clip circuit 15 and is quantized.
Is set to the maximum value of the input range of. Even when the input digital data DG1 has a value exceeding the input range of the quantizing circuit 11, the quantizing circuit 11 always achieves proper quantizing processing. Clip processing by the clip circuit 15 is
Since it is performed after adding the error data obtained from the noise shaping pin group to the digital data DG1, it is possible to set the clip level widely between the ground voltage 0V and the power supply voltage 5V. That is, since error data is not added to the output of the clipping circuit 15,
Even when the clip level is matched with the input range of the quantizing circuit 11, it is possible to prevent data exceeding the input range of the quantizing circuit 11 from being input. As a result, as shown by the solid line in FIG. 3, the output amplitude of the analog signal AN output from the low-pass filter 5 can be maximized between the ground voltage 0V and the power supply voltage 5V.

The embodiment is not limited to the above, but may be modified as follows, and in that case, the same operation and effect can be obtained. (1) In the above-described embodiment, the bit compression circuit 3 adopts a primary noise shaping group, but a bit compression circuit adopting a secondary or higher noise shaping group may be used.

[0022]

According to the present invention, the output amplitude of an analog signal can be increased to the power supply voltage, and the occurrence of distortion of the analog signal can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of a delta-sigma type D / A converter according to an embodiment.

FIG. 2 is a circuit diagram of a bit compression circuit.

FIG. 3 is a diagram showing the output characteristics of the embodiment and the conventional example.

FIG. 4 is a block diagram showing a conventional D / A converter.

[Description of Codes] 3 ... Bit compression circuit, 4 ... Pulse width modulation circuit, 5 ... Low-pass filter, 11 ... Quantization circuit, 12 ... Subtraction circuit, 1
3 ... Latch circuit, 14 ... Addition circuit, 15 ... Clip circuit.

Claims (2)

(57) [Claims] 1. A quantizing circuit for converting a large number of bits of first digital data into second digital data having a reduced number of bits, and a quantizing circuit obtained from a difference between the second digital data and the first digital data. A noise shaping group for feeding back error data indicating a quantization error at the time of quantization to the input side of the quantization circuit and adding the error data to digital data input at a constant cycle to obtain the first digital data; The first data obtained by the noise shaping group
Limit the digital data value within the input range of the above quantizer
And a clip circuit for giving to the quantizer circuit, the quantizer circuit operates in a cycle shorter than the input cycle of digital data, and the noise shaping group is the error data in accordance with the operating cycle of the quantizer circuit. Delta-sigma type D / A converter that delays and returns. 2. A pulse width modulation circuit for converting the second digital data having a reduced number of bits into 1-bit third digital data whose rising period is changed according to the data content, and the third digital data. The delta-sigma type D / A converter according to claim 1, further comprising: a low-pass filter that smoothes the digital data of 1. to output an analog signal.