JPH09129671A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JPH09129671A
JPH09129671A JP28222895A JP28222895A JPH09129671A JP H09129671 A JPH09129671 A JP H09129671A JP 28222895 A JP28222895 A JP 28222895A JP 28222895 A JP28222895 A JP 28222895A JP H09129671 A JPH09129671 A JP H09129671A
Authority
JP
Japan
Prior art keywords
lead
tape body
bonding
chip
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28222895A
Other languages
Japanese (ja)
Inventor
Hiroaki Ikuta
田 裕 秋 生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP28222895A priority Critical patent/JPH09129671A/en
Publication of JPH09129671A publication Critical patent/JPH09129671A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent lead bending during an assembly step and not to be required for a chip surface protecting potting step. SOLUTION: In a TAB tape body 1, an opening part 3 is formed at locations corresponding to its inner lead bonding (ILB) part groups, and an end part of the ILB part is supported by a marginal part of each opening part 3 of the tape body 1. The ILB part of a lead wire 2 is connected to a bump 6 on a chip 5 in the opening part 3. An opening part 4 is formed at locations corresponding to outer lead bonding(OLB) part groups of the lead wire 2 of the tape body 1 and connected to an external wire part in its interior. A portion inwardly of the opening part 3 of the tape body 1 is covered with a face of the chip 5 to be protected. As a top end of an inner lead is composed of a reinforcing structure supported by the tape 1, lead bending does not occur in an assembly step and a bonding step is excellently performed. Further, a chip surface protecting potting step is not required and an attempt is made to simplify the assembly step.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体集積回路の
ＴＡＢテープ本体を持つパッケージに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package having a TAB tape body of a semiconductor integrated circuit.

【０００２】[0002]

【従来の技術】図２は従来のパッケージの構造を示すも
のである。同図において、ポリイミドフィルム等からな
るＴＡＢテープ本体１１上にはリード線１２が被着され
ている。ＴＡＢテープ本体１１の中央部にはデバイスホ
ール及びボンディング窓として機能する正方形の開口部
１３が形成され、リード線１２のインナリードボンディ
ング部は開口部１３内に突出し、この開口部１３内に突
出したリード線に先端とチップ１５上のバンプ１６の持
続によりチップ回路との電気的接続が行われる。ＴＡＢ
テープ本体１１におけるリード線１２のアウタリードボ
ンディング部が位置する計４箇所にそれぞれ長方形の開
口部１４が形成されており、全リード線１２のアウタリ
ードボンディング部がこの開口部１４内に臨み、その内
部で外側配線部との電気的接続が行われるようになって
いる。2. Description of the Related Art FIG. 2 shows the structure of a conventional package. In the figure, a lead wire 12 is attached to a TAB tape body 11 made of a polyimide film or the like. A square opening 13 that functions as a device hole and a bonding window is formed in the center of the TAB tape body 11, and the inner lead bonding portion of the lead wire 12 projects into the opening 13 and projects into the opening 13. The tip of the lead wire and the continuity of the bump 16 on the chip 15 establish an electrical connection with the chip circuit. TAB
Rectangular opening portions 14 are formed at a total of four positions where the outer lead bonding portions of the lead wires 12 of the tape body 11 are located, and the outer lead bonding portions of all the lead wires 12 are exposed in the opening portions 14. Electrical connection with the outer wiring portion is made inside.

【０００３】[0003]

【発明が解決しようとする課題】しかしながら、上記従
来のパッケージにあっては、多数のインナリードがその
先端に支えのない状態でむき出しになっているため、取
扱い時にリード曲り等の変形が起こり易かった。However, in the above-mentioned conventional package, many inner leads are exposed without any support at the tips thereof, so that deformation such as lead bending is likely to occur during handling. It was

【０００４】また、インナリードボンディング後はチッ
プ表面が露出した状態になっているために、チップ保護
のためその表面を樹脂でコートする必要があった。Further, since the surface of the chip is exposed after the inner lead bonding, it is necessary to coat the surface of the chip with resin in order to protect the chip.

【０００５】本発明は上記問題に鑑みてなされたもの
で、その目的とするところはアセンブリ工程中でリード
曲りを生じさせることがなく、また、チップ表面保護の
ために行うポッティング工程を必要としない半導体集積
回路パッケージを提供することにある。The present invention has been made in view of the above problems, and it is an object of the present invention to prevent lead bending during the assembly process and to eliminate the need for a potting process for protecting the chip surface. It is to provide a semiconductor integrated circuit package.

【０００６】[0006]

【課題を解決するための手段】本発明の半導体パッケー
ジは、ＴＡＢテープ本体と、該ＴＡＢテープ本体に被着
されたリード線と、前記ＴＡＢテープ本体における前記
リード線のインナリードボンディング部が位置する箇所
に形成されたインナリード開口部とを備えていることを
特徴とする。In a semiconductor package of the present invention, a TAB tape body, a lead wire attached to the TAB tape body, and an inner lead bonding portion of the lead wire in the TAB tape body are located. And an inner lead opening formed at a location.

【０００７】[0007]

【発明の実施の形態】図１は本発明の一実施例に係る半
導体パッケージの構造を示すものである。同図におい
て、ポリイミドフィルム等からなるＴＡＢテープ本体１
上にはリード線２が被着されている。ＴＡＢテープ本体
１のインナリードボンディング部が位置する計４箇所に
それぞれボンディング窓としての長方形の開口部３が形
成されており、インナリードボンディング部の端部はＴ
ＡＢテープ本体１における各開口部３の周縁部によって
支持されている。リード線２のインナリードボンディン
グ部は開口部３内でチップ５上のバンプ６との接続がギ
ャングボンディングにより行われる。ＴＡＢテープ本体
１におけるリード線２のアウタリードボンディング部が
位置する計４箇所にそれぞれボンディング窓としての長
方形の開口部４が形成されており、全リード線２のアウ
タリードボンディング部がこの開口部４内に臨み、その
内部で外側配線部との接続がギャングボンディングによ
り行われるようになっている。ＴＡＢテープ本体１の開
口部３より内方の部分はチップ５の表面を覆うようにな
っている。1 shows the structure of a semiconductor package according to an embodiment of the present invention. In the figure, a TAB tape body 1 made of a polyimide film or the like
A lead wire 2 is attached to the top. Rectangular openings 3 are formed as bonding windows at a total of four locations where the inner lead bonding portions of the TAB tape body 1 are located, and the end portions of the inner lead bonding portions are T-shaped.
It is supported by the peripheral portion of each opening 3 in the AB tape body 1. The inner lead bonding portion of the lead wire 2 is connected to the bump 6 on the chip 5 in the opening 3 by gang bonding. Rectangular openings 4 as bonding windows are formed at a total of four positions where the outer lead bonding portions of the lead wires 2 in the TAB tape body 1 are located. The inner wiring is connected to the outer wiring portion by gang bonding. A portion of the TAB tape body 1 which is located inside the opening 3 covers the surface of the chip 5.

【０００８】本実施例によれば、デバイスホールを持た
ず、インナリードボンディングを行う部分のみに開口部
３が形成されており、インナリード先端がテープ１によ
って支えられた補強構造となっているため、アセンブリ
工程中でリード曲りを生じさせることがなく、ボンディ
ング工程を良好に行うことができる。According to the present embodiment, since the opening 3 is formed only in the portion where the inner lead bonding is carried out without the device hole, and the tip of the inner lead is supported by the tape 1, the reinforcing structure is provided. In addition, the bonding process can be favorably performed without causing the lead to bend during the assembly process.

【０００９】また、チップ表面保護のために行うポッテ
ィング工程を必要としないため、アセンブリ工程の簡略
化を図ることができることとなる。Further, since the potting process for protecting the chip surface is not required, the assembly process can be simplified.

【００１０】[0010]

【発明の効果】以上説明したように本発明によれば、デ
バイスホールを持たず、インナリードボンディングを行
う部分のみに開口部が形成されており、インナリード先
端がテープ１によって支えられた補強構造となっている
ため、アセンブリ工程中でリード曲りを生じさせること
がなく、ボンディング工程を良好に行うことができる。As described above, according to the present invention, there is no device hole, the opening is formed only in the portion for inner lead bonding, and the tip of the inner lead is supported by the tape 1. As a result, the lead bending is not caused during the assembly process, and the bonding process can be favorably performed.

【００１１】また、チップ表面保護のために行うポッテ
ィング工程を必要としないため、アセンブリ工程の簡略
化を図ることができることとなる。Further, since the potting process for protecting the chip surface is not required, the assembly process can be simplified.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例に係る半導体装置の構造を示
す平面図（ａ）及び一部拡大断面図（ｂ）。FIG. 1 is a plan view (a) and a partially enlarged cross-sectional view (b) showing a structure of a semiconductor device according to an embodiment of the present invention.

【図２】従来の半導体装置の構造を示す平面図（ａ）及
び一部拡大断面図（ｂ）。FIG. 2 is a plan view (a) and a partially enlarged sectional view (b) showing a structure of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

１ ＴＡＢテープ本体 ２ リード線 ３ インナリード開口部 ４ アウタリード開口部 ５ チップ ６ バンプ 1 TAB tape body 2 lead wire 3 inner lead opening 4 outer lead opening 5 chip 6 bump

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】ＴＡＢテープ本体と、 該ＴＡＢテープ本体に被着されたリード線と、 前記ＴＡＢテープ本体における前記リード線のインナリ
ードボンディング部が位置する箇所に形成されたインナ
リード開口部とを備えていることを特徴とする半導体パ
ッケージ。1. A TAB tape body, a lead wire adhered to the TAB tape body, and an inner lead opening formed in a portion of the TAB tape body where an inner lead bonding portion of the lead wire is located. A semiconductor package characterized by being provided.
JP28222895A 1995-10-30 1995-10-30 Semiconductor package Pending JPH09129671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28222895A JPH09129671A (en) 1995-10-30 1995-10-30 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28222895A JPH09129671A (en) 1995-10-30 1995-10-30 Semiconductor package

Publications (1)

Publication Number Publication Date
JPH09129671A true JPH09129671A (en) 1997-05-16

Family

ID=17649730

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28222895A Pending JPH09129671A (en) 1995-10-30 1995-10-30 Semiconductor package

Country Status (1)

Country Link
JP (1) JPH09129671A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103348460A (en) * 2011-01-31 2013-10-09 Lg伊诺特有限公司 Tap tape for electronic devices with reinforced lead crack and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103348460A (en) * 2011-01-31 2013-10-09 Lg伊诺特有限公司 Tap tape for electronic devices with reinforced lead crack and method of manufacturing the same

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