JPH09129537A - Pattern transfer method and method for manufacturing solid element and solid element using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a superimposition error of the both by a method wherein a transfer position of a second circuit pattern is corrected by data in a transfer position of a first circuit pattern, and the second circuit pattern is superimposed thereon to be transferred. SOLUTION: A first circuit pattern is transferred (1), a stage drive result at this time of transfer is monitored, and as a result of stage drive in a memory device, data of error of a transfer pattern position are acquired (2) and stored in the memory device (3). After a specific circuit pattern is processed (4), a second circuit pattern is superimposed on the first circuit pattern to be transferred. At this time, data stored are read out (5), a stage drive position is corrected based on these data, while a mask pattern is transferred (6). Thus, a specific circuit pattern can be processed with desired precision and an element can be made at high manufacturing yield.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure apparatus used for manufacturing various solid-state elements such as semiconductor elements, superconductor elements, magnetic elements, and optical integrated circuit elements, and solid-state elements manufactured using the same. Regarding

[0002]

2. Description of the Related Art In the manufacture of semiconductor integrated circuit devices and the like, an optical lithography method is mainly used in which a mask pattern formed on a mask or a reticle (hereinafter referred to as a mask) is irradiated with exposure light and transferred onto a substrate. Has been used for. In particular, a reduction projection exposure method for reducing and transferring a mask pattern onto a substrate via an imaging optical system has been mainly used for transferring a fine pattern having a design dimension of about 1 μm or less.

The resolution improvement in the reduction projection exposure method has been promoted by shortening the wavelength of exposure light and increasing the NA of the imaging optical system. Further, recently, development of high resolution technology such as a phase shift mask exposure method and a modified illumination exposure method has been advanced.

Further, the chip size has been gradually expanded with the high integration of elements. The maximum field size, which is the area that can be transferred with a single exposure light, is also gradually increasing, and in recent step-and-repeat reduction projection exposure apparatuses (hereinafter referred to as steppers), the size on the wafer substrate is 22 mm.
It has become possible to transfer a corner (31.1 mmφ) area. This method is a method in which a plurality of chips are repeatedly transferred onto a substrate by repeating step-and-repeat the mask pattern transfer by exposure light irradiation and the substrate stage movement.

A step-and-scan type reduction projection exposure apparatus (hereinafter referred to as a scanner) has also been developed as an apparatus capable of transferring a larger area. This method is a method in which a mask and a substrate are moved relative to each other according to a predetermined mask pattern reduction ratio, and an illumination region having an arc shape or a slit shape is scanned on the mask to transfer the mask pattern.

However, even if various high-resolution techniques are applied to these exposure apparatuses, the photolithography method is used to obtain 100n.
It is predicted that it is very difficult to form a fine pattern of m or less.

On the other hand, the electron beam exposure method of drawing or transferring a pattern using an electron beam has been put into practical use as one of fine processing techniques capable of forming an ultrafine pattern of 100 nm or less. The electron beam exposure method is a variable rectangular shaped electron beam direct drawing method in which a pattern is directly drawn on a substrate using an electron beam shaped in a rectangular shape, or an electron beam shaped in a certain predetermined shape is repeatedly transferred. Several exposure methods have been developed, including a cell projection method and an electron beam exposure method. However, in general, the electron beam exposure method has a problem that the throughput is lower than that of the optical lithography method in which a mask pattern is transferred at one time.

Therefore, in order to suppress the decrease in throughput in the lithography process while utilizing the ultrafine dimension processing performance of the electron beam exposure method, for example, a fine dimension pattern which cannot be transferred by the optical lithography method is used by the electron beam exposure method. , A method of mixing a plurality of lithography techniques by mix and match is used, such as transferring a relatively large pattern other than the above by an optical lithography method.

[0009]

In a scan type exposure apparatus, a substrate stage on which a substrate for transferring a mask pattern is placed and a mask stage on which the mask is placed are
The mask pattern is transferred while precisely moving in synchronization with each other in accordance with the mask pattern reduction ratio. At this time, an error in stage movement may occur. This error affects the mask pattern transfer accuracy. Especially,
The error in the pattern position due to the stage error greatly affects the overlay exposure accuracy.

Also, when a pattern is transferred using an electron beam exposure apparatus, similarly, the movement error of the substrate stage on which the substrate is placed may affect the overlay exposure accuracy. Furthermore, when a scan type exposure apparatus and an electron beam exposure apparatus are used in a mix-and-match manner, the difference in the stage movement positions of the two affects the overlay exposure accuracy.

Conventionally, since the overlay error caused by such a stage error has not been taken into consideration during the overlay exposure, there is a problem that the overlay accuracy is deteriorated.

[0012]

The above problem is caused by illuminating an illumination area of a predetermined shape with exposure light, and scanning the illumination area of the predetermined shape on a mask on which a mask pattern for transferring a first circuit pattern is formed. In addition, the substrate is scanned in synchronization with the mask with respect to an exposure region having a predetermined shape, which is obtained by projecting the illumination region having the predetermined shape on the substrate by a projection optical system, so that the first circuit pattern is formed on the substrate. When exposing the substrate, from the information on the scanning position error when the illumination area of the predetermined shape scans the mask and the information on the scanning position error when the exposure area of the predetermined shape scans the substrate, A step of obtaining information on a transfer position error of the first circuit pattern transferred onto the substrate, and a step of aligning and transferring the second circuit pattern onto the first circuit pattern on the substrate. First By using a pattern transfer method that corrects the transfer position of the second circuit pattern so as to reduce the overlay error with the first circuit pattern by using the information about the transfer position error of the circuit pattern, a predetermined exposure light is used. Illuminating an illumination area having a predetermined shape, scanning the illumination area having the predetermined shape on a mask on which a mask pattern for second circuit pattern transfer is formed, and projecting the illumination area having the predetermined shape onto a substrate by a projection optical system. By scanning the substrate in synchronization with the mask with respect to the projected exposure area of a predetermined shape, the second
When the above circuit pattern is exposed on the substrate, the illumination area having the predetermined shape is used as a mask pattern for transferring the second circuit pattern by using information about the transfer position error of the first circuit pattern transferred onto the substrate. By correcting the scanning position when scanning on the mask on which is formed, or in synchronization with the mask with respect to the exposure region of the predetermined shape projected on the substrate by the projection optical system the illumination region of the predetermined shape By correcting the scanning position at the time of scanning the substrate, it is possible to reduce the overlay error with the first circuit pattern so as to reduce the second error.
By the pattern transfer method for correcting the transfer position of the circuit pattern, the second circuit pattern is further transferred by using the electron beam exposure method, and the electron beam at the time of exposing the second circuit pattern by the electron beam is used. By correcting the deflection position by using the information regarding the transfer position error of the first circuit pattern transferred onto the substrate, or by correcting the driving position of the sample table on which the substrate is placed, the first position is corrected. This is solved by the pattern transfer method of correcting the transfer position of the second circuit pattern so as to reduce the overlay error with the circuit pattern.

In order to correct the stage error, the stage may be adjusted and driven during the transfer of the superposition pattern based on the stage drive position when the superposition pattern is transferred. Further, when the superposition pattern is transferred using the electron beam drawing apparatus, it may be performed by correcting the electron beam deflection position without performing the stage drive correction.

The correction method will be further described with reference to FIG.
First, step 1 of transferring the first circuit pattern is processed.
At this time, the stage drive result at the time of pattern transfer is monitored, the stage drive result and information regarding the transfer pattern position error are obtained from the storage device (step 2), and stored in the storage device (step 3). Since the stage position is monitored by the laser interference system, the stage position drive result is stored in the storage device via the control device. For scanners,
Information about the synchronous drive error between the substrate stage and the mask stage may be stored. At this time, information relating to mask pattern transfer such as exposure date / time, lot identifier, processed wafer identifier, transfer chip arrangement, sequence, transfer pattern identifier, exposure apparatus identifier, used mask identifier, etc. is also stored at the same time, so that process processing is performed. The process can also be managed.

The stored information can be sent to another exposure device by means of a magnetic tape, a magnetic disk device, a magneto-optical disk device or the like. In addition, if the control devices of each exposure device are connected to each other via a network,
Information can be transferred more easily. In addition, a control device that connects each exposure apparatus to each other via a network and is provided with a common storage device for storing information between the exposure apparatuses, or a control apparatus that exclusively operates this information related to mask pattern exposure By providing, it is possible to perform the work more efficiently.

After the step 4 of processing a predetermined circuit pattern is processed, the second circuit pattern is superimposed and transferred onto the first circuit pattern. At this time, the information stored as described above may be read (step 5), and the mask pattern may be transferred while correcting the stage drive position based on this information (step 6). For example, the information related to the mask pattern transfer when the superimposed pattern is transferred is called from the above-mentioned storage device, and the correction amount of the mask pattern position to be transferred may be obtained from the information related to the driving result of the substrate stage and the mask stage.

Even when the superposition pattern is transferred using the electron beam drawing apparatus, the mask pattern may be drawn while correcting the substrate stage driving position based on the information on the transfer result of the superposition pattern. It is also possible to correct the transfer pattern position by adjusting the deflection amount of the electron beam for drawing the pattern instead of the substrate stage drive position by controlling the electron lens.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) A process for processing a circuit pattern of a 1-gigabit DRAM (dynamic random access memory) class large-scale integrated circuit having a minimum design dimension of 180 nm and a transfer chip size of 20 mm × 24 mm square will be described as an example.

In this embodiment, a wiring pattern of a predetermined semiconductor memory device was transferred onto a substrate processed by a predetermined process using a KrF excimer laser exposure device (reduction ratio 4: 1).

An example of the configuration of a projection exposure apparatus that realizes the mask pattern exposure method of the present invention will be described with reference to FIG. The light emitted from the light source 31 is shaped by the masking blade 52 via the illumination optical system 30 and illuminates the mask 36.

The mask 36 is placed on a mask stage 48. Since the mask stage 48 is driven by the driving means 47 according to a control command from the main control system 49, it can be moved to a desired position. Mask stage 48
The position of is accurately monitored by the laser length measuring machine 54 as the position of the mirror 53 fixed on the stage. A pellicle 37 is provided on the mask 36 to prevent pattern transfer failure due to foreign matter.

The mask pattern drawn on the mask 36 is
It is projected on a wafer 39 which is a sample substrate through a projection lens 38. The wafer 39 is vacuum-adsorbed on the substrate stage 40. The substrate stage 40 has a projection lens 38.
Is mounted on a Z stage 41 movable in the optical axis direction, that is, the Z direction, and further mounted on an XY stage 42. Since the Z stage 41 and the XY stage 42 are driven by the respective driving means 43 and 44 according to the control command from the main control system 49, they can be moved to a desired exposure position. The position is accurately monitored by the laser length measuring device 45 as the position of the mirror 46 fixed to the Z stage 41. In addition, the surface position of the wafer 39 is measured by a focus position detecting means included in a normal exposure apparatus.
By driving the Z stage 41 according to the measurement result, the surface of the wafer 39 can always be made to coincide with the image plane of the projection lens 38.

The mask 36 is illuminated by the illumination light shaped into a slit by the masking blade 52.
The mask 36 is moved by moving the mask stage 48.
The slit-shaped illumination light scans the upper part, and the mask pattern on the mask 36 illuminated by this is transferred onto the wafer 39 which is moved in synchronization with the mask 36.

Since the mask pattern reduction ratio is 4: 1, the driving amount of the mask stage 48 is driven by a distance four times as large as the driving amount of the substrate stage 40. For example, the amount of movement of the substrate stage 40 in the Y direction is set to 4 with respect to the amount of movement of the mask stage in the Y direction, and the substrate stage 40 may be continuously moved in the Y direction in synchronization with each other.

In this embodiment, the size of the substrate on which the pattern is transferred was 6 inches φ. Therefore, in this embodiment, the exposure chip arrangement as schematically shown in FIG. Was exposed in the order shown by the arrow in the figure. In addition, 25 substrates make up one lot, the lot identifier is LOT 154, and the substrates are 01, 0 sequentially from the first.
2, ..., 24, 25.

Information on pattern placement errors obtained by accurately monitoring the driving result of the substrate stage 40 and the driving result of the mask stage 48 at the time of pattern transfer by the laser length measuring machines 45 and 54 and performing arithmetic processing on the monitoring results. Was stored in the storage device 51 via the control device 49 in a file format. The storage device 51 is configured to be able to share data with other exposure apparatuses via the network 425.

Information about the pattern arrangement stored in the storage device 51 is stored in the network device 425 as shown in FIG.
It is transferred to the control device 201 dedicated to the data processing connected to and is stored in the storage device 202. Such a device configuration is effective for collective management of information on processing processes and production management.

A predetermined gate pattern was transferred using a projection exposure apparatus. Substrate stage 40 and mask stage 4
The driving result of No. 8 was subjected to arithmetic processing to obtain information on the transfer pattern placement error caused by the synchronous driving error between the two, and the obtained result was stored in the storage device 51 in a file format.

In this embodiment, the information regarding the transfer pattern arrangement error is stored in the file format, but the storage system is not limited to this. In addition, the file has a file structure in which information on the lot identifier, the exposure date and time, the exposure device identifier, the transfer pattern identifier, the used mask identifier, and the transfer pattern arrangement error is arranged in order from the first substrate to the 25th substrate from the top of the file. However, the content, order,
The file format is not limited to this.

After the predetermined resist pattern development process, a predetermined wiring pattern was processed using the formed resist pattern as a mask. Next, an interlayer insulating film was formed on this substrate, and this time, a second circuit pattern for a predetermined electrode extraction hole was transferred using an electron beam exposure apparatus. An example of the configuration of the electron beam exposure apparatus that realizes the pattern transfer method of the present invention will be described with reference to FIG. Electrons 402 emitted from the electron gun 401 are focused by a plurality of electron lenses 403 and 404 and are deflected by the deflection lens 4.
The wafer 408 on the stage 407 is deflected by the beams 05 and 406 and is irradiated. At this time, the shape of the electron beam is determined by the two apertures 409 and 410. For example, an aperture as shown in FIG. 7 is mounted on the second aperture support base 410, and an arbitrary aperture pattern on the second aperture support base 410 is selected and used by the electron beam shaping lenses 411 and 412. Aperture support 40 at the same time
Since a rectangular aperture pattern is formed in the central part of 1, it can be used also as a variable rectangular electron beam drawing apparatus. The wafer 408 can be taken in and out of the apparatus through the sample exchange chamber 415 without breaking the high vacuum atmosphere of the sample chamber 413.

The system of the entire apparatus is controlled by a control device 423, and a storage device 424 for storing data is connected. Further, the control device 423 is a network device.
425, and is connected so as to be able to perform data communication with other exposure apparatuses and process apparatuses.

In this embodiment, the information about the pattern arrangement stored in the storage device 202 in the file format is read into the control device 423 via the network device 425. Unlike the present embodiment, when the control device and the storage device are not connected to the network device and the exposure device has a stand-alone configuration, it is possible to use a movable storage means such as a magnetic tape, a magnetic disk, or a magneto-optical disk. Information may be transferred by transferring.

Using the information on the pattern arrangement read in as described above, the transfer position at the time of transferring the predetermined electrode take-out hole pattern was corrected.

FIG. 12 is a diagram showing a result of monitoring the y-direction driving result of the substrate stage 40 with respect to a certain chip when the first circuit pattern is transferred. The horizontal axis represents the reference coordinate position used when driving the substrate stage 40, and the vertical axis represents the deviation amount from the reference coordinate position obtained from the monitor result of the substrate stage drive result. In the figure, the portion where the drive error is less than 20 nm is cut off from the actual monitor result and displayed. This is because the reproducibility of the stage drive position was about 20 nm, and it was difficult to sufficiently correct the pattern transfer position in consideration of the stage drive accuracy.

FIG. 9 shows the transfer pattern arrangement of the first circuit pattern, which is the pattern to be overlapped, using the result of FIG.
This is a dimensional schematic representation. The grid points in the figure are 2
It is the figure which showed typically the shift of the transfer pattern position in a 2 mm pitch grid point position in a 0 mm x 24 mm square transfer pattern.
Each lattice point position indicates the transfer position of the first circuit pattern with reference to the case where there is no transfer pattern position error. The y-direction distance between the lattice points 11 is reduced by 20 nm with respect to the reference length of 2 mm, and the y-direction distance between the lattice points 12 is enlarged by 20 nm with respect to the reference length of 2 mm.

In the following, description will be given using an example in which a shift in the y direction mainly occurs when the stage is scanned and transferred in the y direction, but as shown in FIG. 10, the x direction and the y direction are substantially the same. An error in the transfer pattern position may occur. However, for the x direction, which is perpendicular to the scan direction,
If the transfer chip magnification of the projection exposure apparatus is constant, the transfer pattern position is shifted and transferred. In FIG. 10, the position in the x direction between the lattice points 13 is shifted by 25 nm in the negative direction, and the position in the x direction between the lattice points 14 is 25 nm in the positive direction.
When shifting, the y-direction distance is 2 for a standard length of 2 mm
An example is shown in which the image is enlarged by 0 nm and transferred. Also in this case, the method described below can be applied and applied.

From the information on the pattern arrangement described above, for example, the information on the circuit pattern arrangement as shown in FIG. 9 can be obtained and used to correct the transfer position of the electrode take-out hole pattern. In this embodiment, the deflection lenses 405 and 406 are controlled by using the information on the pattern arrangement described above to control and correct the deflection of the electron beam, so that the electrode extraction hole pattern transfer position is aligned with the first circuit pattern transfer position. Was corrected. The pattern transfer position may be corrected by correcting the drive position of the stage 407.

FIG. 5 is a sectional view showing the manufacturing process of the device. As shown in FIG. 5A, a P-type Si semiconductor 71 is used for the substrate. An element isolation region 72 is formed on the surface by using a known element isolation technique. Next, for example, a thickness of 150 nm
Forming a word line 73 having a structure in which the polycrystalline silicon and the silicon oxide having a thickness of 200 nm are laminated, and further, for example, a silicon oxide having a thickness of 150 nm is deposited by the chemical vapor deposition method and anisotropically processed. A side spacer 74 of silicon oxide is formed on the side wall of the word line. Next, the n diffusion layer 75 is formed by a usual method.

Next, as shown in FIG. 5B, a data line 76 made of polycrystalline silicon, refractory metal silicide, or a laminated film of these is formed through a normal process. Next, as shown in FIG. 5C, a storage electrode 78 made of polycrystalline silicon is formed through a normal process. After that, tantalum pentoxide, silicon nitride, silicon oxide, a ferroelectric material, or a composite film thereof is deposited to form a capacitor insulating film 79. Polycrystalline silicon, refractory metal, refractory metal silicide, or A
A plate electrode 80 is formed by depositing a low resistance conductor such as 1, Cu.

Next, as shown in FIG. 5D, the wiring 81 is formed through a normal process. Next, a semiconductor memory element was manufactured through a normal wiring layer forming process and a passivation process. Although only typical manufacturing steps have been described here, the normal element manufacturing steps are used for other steps. In the lithography process in this element manufacturing process, the optical lithography method was applied to a part of the process, and the pattern transfer was performed using the above-described projection exposure apparatus.

Next, the pattern formed by the lithography process will be described. FIG. 6 shows a pattern layout of a memory section of a typical pattern that constitutes the manufactured semiconductor memory device.
FIG. 6A shows an example of the pattern of the manufactured first element. Reference numeral 82 is a word line, 83 is a data line, 84 is an active area, 85 is a storage electrode, and 86 is a pattern of electrode lead-out holes. In this embodiment, in the pattern shown in FIG. 6A, the projection exposure apparatus and the phase shift mask are used for transferring the patterns of the word lines 82, the data lines 83, and the active areas 84. Further, in the pattern shown in FIG. 6A, the pattern for forming the electrode extraction hole 86 and the storage electrode 85 was transferred using an electron beam exposure apparatus.

FIG. 6B shows an example of the pattern of the manufactured second element. 87 is a word line, 88 is a data line, 89 is an active region, 90 is a storage electrode, and 91 is a pattern of electrode lead-out holes. In this example, the word line,
A projection exposure apparatus was used to transfer the data line and active area patterns, and an electron beam exposure apparatus was used to transfer the electrode take-out holes and storage electrode patterns.

After the pattern was transferred as described above, the overlay error between the predetermined wiring pattern and the predetermined electrode extraction hole pattern was measured using an electron microscope, and the overlay error was found to be larger than 80 nm. No part was observed. That is, the overlay error of the two patterns was within the desired overlay error tolerance range, and the desired overlay accuracy was achieved.

By manufacturing a large-scale integrated circuit device by applying the method as described above, it is possible to process a predetermined circuit pattern with a desired accuracy, so that the device is manufactured with a high yield. It is possible. Furthermore, since processing variations can be reduced, it is possible to manufacture circuit elements having stable characteristics. That is, it is possible to manufacture devices with a high yield.

The present invention is not limited to the above-mentioned embodiments, and the present invention can be applied and applied within the scope of the gist of the present invention.

(Embodiment 2) In this embodiment, a process for processing a circuit pattern of a 256-Mbit DRAM class large-scale integrated circuit having a minimum design dimension of 250 nm and a transfer chip size of 20 mm square will be described as an example.

The structure of the exposure apparatus used in this embodiment is shown in FIG. The exposure devices 426A, 426B, 426C are controlled by the control devices 423A, 423B, 423C, respectively, and the storage devices 424A, 424B, 424C are connected to the respective control devices. The control device 20
A storage device 202 is connected to 1. Control device 42
Since 3A, 423B, 423C and 201 are connected to the network device 425, data communication between control devices is possible via the network device 425. The control device 201 and the storage device 202 are provided to exclusively manage the process processing result, processing state, etc. of each process device. A process processor (not shown) other than the lithographic apparatus is also connected to the network apparatus 425. Further, the data communication device 427 enables data communication with a control device that is not directly connected to the network device 425.

First, the first circuit pattern was transferred in the same manner as in Example 1. The first circuit pattern is the projection exposure apparatus 4
Transferred using 26A. At this time, the driving result of the substrate stage 40 and the driving result of the mask stage 48 at the time of pattern transfer are monitored by the laser length measuring machines 45 and 54, respectively, and the information on the pattern placement error obtained by arithmetic processing of the monitoring result is controlled. Storage device 424 via device 423A
The file format is stored in A. Further, the data is transferred to the control device 201 via the network device 425, and the storage device 2
No. 02 was stored and saved.

Next, the second circuit pattern was transferred using the second projection exposure apparatus 426B having the same structure as the one to which the first circuit pattern was transferred. In this embodiment, the network device 4
25, the information regarding the pattern arrangement stored in the storage device 202 in the file format via the control device 201 is read into the control device 423B. Unlike the present embodiment, when the control device and the storage device are not connected to the network device and the exposure device has a stand-alone configuration, a movable storage means such as a magnetic tape, a magnetic disk, or a magneto-optical disk is used. The information may be transferred via.

By using the information on the pattern arrangement of the first circuit pattern read as described above, the driving position of the mask stage 48 so as to reduce the overlay error of the second circuit pattern on the first circuit pattern. The second circuit pattern was transferred while correcting The pattern transfer position of the second circuit pattern may be corrected by correcting the drive position of the substrate stage 40 or by correcting the drive positions of both the substrate stage 40 and the mask stage 48.

After the pattern was transferred as described above, the overlay error between the first circuit pattern and the second circuit pattern was measured using an electron microscope, and the overlay error was larger than 100 nm. The part that was marked was not observed. That is, the overlay error of the two patterns was within the desired overlay error tolerance range, and the desired overlay accuracy was achieved.

In the pattern shown in FIG. 6B, the method described in this embodiment was used, for example, when the word line 87 was superposed and transferred to the active area 89, but the method is not limited to this. is not.

By manufacturing a large-scale integrated circuit device by applying the method as described above, it is possible to process a predetermined circuit pattern with desired accuracy, and thus the device is manufactured with a high yield. It is possible. Furthermore, since processing variations can be reduced, it is possible to manufacture circuit elements having stable characteristics. That is, it is possible to manufacture devices with a high yield.

(Embodiment 3) In this embodiment, a process of processing a circuit pattern of a 1-gigabit DRAM class large-scale integrated circuit having a minimum design dimension of 180 nm and a transfer chip size of 20 mm square will be described as an example.

First, the first circuit pattern was transferred using the electron beam exposure device 426C. At this time, the driving result of the substrate stage 407 during pattern transfer was monitored. further,
Information on the pattern placement error of the first circuit pattern obtained by arithmetic processing using the distortion error in the exposure field of the electron beam exposure apparatus when the first circuit pattern is transferred and the substrate stage drive position monitor result described above. Was stored in a file format in the storage device 424C via the control device 423C. Further, the data is transferred to the control device 201 via the network device 425 and stored and stored in the storage device 202.

Next, the second circuit pattern was transferred using the electron beam exposure device 426C. In this embodiment, the storage device 202 is connected via the network device 425 and the control device 201.
The information about the pattern arrangement stored in the file format in the inside is read into the control device 423C.

Using the information on the pattern arrangement of the first circuit pattern read as described above, the deflection lenses 405 and 406 are arranged so as to reduce the overlay error of the second circuit pattern with respect to the first circuit pattern. By controlling the deflection of the electron beam, the transfer position of the second circuit pattern was corrected. The distortion error of the electron beam exposure apparatus during the second circuit pattern exposure was corrected on the exposure apparatus side in advance by using a predetermined method before the exposure.

FIG. 11 schematically shows the pattern layout of the first circuit pattern in this embodiment. 15A and 15 between grid points
In the overlapping area of B and the overlapping area of the inter-lattice points 16A and 16B, the pattern transfer position is corrected by linear interpolation at each inter-grid point position in accordance with the shift of the transfer pattern position at each grid point position. The transfer position of the second circuit pattern may be corrected by correcting the drive position of the stage 407.

In the pattern shown in FIG. 6B, the method described in this embodiment was used, for example, when the electrode lead-out hole pattern 91 was superposed and transferred onto the data line 88, but the method is not limited to this. Not a thing.

After the pattern was transferred as described above, the overlay error between the first circuit pattern and the second circuit pattern was measured using an electron microscope, and the overlay error was larger than 100 nm. The part that was marked was not observed. That is, the overlay error of the two patterns was within the desired overlay error tolerance range, and the desired overlay accuracy was achieved.

By manufacturing a large-scale integrated circuit device by applying the method as described above, it is possible to process a predetermined circuit pattern with desired accuracy, and thus the device is manufactured with a high yield. It is possible. Furthermore, since processing variations can be reduced, it is possible to manufacture circuit elements having stable characteristics. That is, it is possible to manufacture devices with a high yield.

[0062]

According to the present invention, patterns can be transferred with high overlay accuracy.

[Brief description of the drawings]

FIG. 1 is a process flow chart showing a process according to the present invention.

FIG. 2 is a block diagram of a projection exposure apparatus used in the examples.

FIG. 3 is an explanatory diagram showing a pattern transfer sequence in an example.

FIG. 4 is a block diagram showing the configuration of an electron beam exposure apparatus used in the examples.

FIG. 5 is a cross-sectional view of an element in the process of manufacturing a semiconductor device manufactured in an example.

FIG. 6 is a plan view showing a pattern layout of a semiconductor device manufactured in an example.

FIG. 7 is a plan view showing an aperture used in an electron beam exposure apparatus.

FIG. 8 is a block diagram of an exposure apparatus group in the embodiment.

FIG. 9 is an explanatory diagram showing an example of positional deviation of a transfer pattern.

FIG. 10 is an explanatory diagram showing an example of positional deviation of a transfer pattern.

FIG. 11 is an explanatory diagram showing an example of positional deviation of a transfer pattern.

FIG. 12 is an explanatory diagram showing a drive position error of the substrate stage.

[Explanation of symbols]

1 ... Step of transferring first circuit pattern, 2 ... Step of obtaining transfer position error of first circuit pattern, 3 ... Step of storing information about transfer position error, 4 ... Step of processing circuit pattern, 5 ... A step of reading information on a transfer position error, a step of transferring the second circuit pattern while correcting the transfer position, and a step of processing the circuit pattern.

Claims (7)

[Claims] 1. An illumination area of a predetermined shape is illuminated with exposure light, and a mask on which a first circuit pattern is formed is scanned to scan the illumination area of the predetermined shape on the mask, and at the same time, the mask of the predetermined shape is formed. When exposing the first circuit pattern on the substrate by scanning the substrate in synchronization with the mask with respect to an exposure region having a predetermined shape, which is obtained by projecting an illumination region on the substrate using a projection optical system, An exposure apparatus used in the exposure includes a first detection system that detects a scanning position of a mask stage on which the mask is mounted, and a second detection system that detects a scanning position of a sample stage on which the substrate is mounted, Detecting the scanning position of the mask stage using the first detection system and detecting the scanning position of the sample stage using the second detection system; and the detected scanning position of the mask stage and scanning of the sample stage. position A step of obtaining the information about the transfer position of the first circuit pattern from information about, first on the substrate
When the second circuit pattern is aligned with the second circuit pattern and superimposed and transferred, information on the transfer position of the first circuit pattern is used to reduce an overlay error with the first circuit pattern. A pattern transfer method including the step of correcting the transfer position of the second circuit pattern and transferring the second circuit pattern in an overlapping manner. 2. The illumination area having a predetermined shape is illuminated with the exposure light and the second mask having the second circuit pattern is scanned to scan the illumination area having a predetermined shape. And scanning the substrate in synchronization with the mask with respect to an exposure region of a predetermined shape obtained by projecting the illumination region of the predetermined shape on the substrate using a projection optical system while scanning the mask. When the circuit pattern is aligned with the first circuit pattern on the substrate and is superimposed and exposed, information on the transfer position of the first circuit pattern is used to detect the first circuit pattern and the second circuit pattern. In order to reduce the amount of misalignment with the circuit pattern of
Pattern transfer method for correcting one or both of the scanning position of the mask stage on which the mask is mounted and the scanning position of the sample stage on which the substrate is mounted. 3. The second circuit pattern according to claim 1, wherein the second circuit pattern is transferred using an electron beam exposure method, and the second circuit pattern is transferred using information about a transfer position of the first circuit pattern transferred onto the substrate. Pattern transfer for correcting the transfer position of the second circuit pattern so as to reduce the overlay error with the first circuit pattern by correcting the deflection amount of the electron beam when the circuit pattern of FIG. Method. 4. The substrate according to claim 1, wherein the second circuit pattern is transferred using an electron beam exposure method, and information about a transfer position error of the first circuit pattern transferred onto the substrate is used. A pattern transfer method in which the transfer position of the second circuit pattern is corrected so as to reduce the overlay error with the first circuit pattern by correcting the drive position of the sample table on which is mounted. 5. A step of storing one or more pieces of information among information on the detected scanning position of the mask stage, information on the scanning position of the sample stage, and information on the transfer position of the first circuit pattern. The method according to claim 1 or claim 2, which is carried out before the step of transferring the two circuit patterns in an overlapping manner.
Alternatively, the pattern transfer method according to claim 3 or 4. 6. A method of manufacturing a solid-state device manufactured by using the pattern transfer method according to claim 1, 2, 3, 4 or 5. 7. A solid-state device manufactured by using the method for manufacturing a solid-state device according to claim 6.