JP3561564B2 - Method for manufacturing solid state device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to various solid-state devices such as semiconductor devices, superconductor devices, magnetic devices, and optical integrated circuit devices. of Manufacture Method About.
[0002]
[Prior art]
2. Description of the Related Art In the manufacture of semiconductor integrated circuit devices and the like, a photolithography method of irradiating a mask pattern formed on a mask or a reticle (hereinafter, collectively referred to as a mask) with exposure light and transferring the mask pattern onto a substrate has been mainly used. . In particular, a reduced projection exposure method in which a mask pattern is reduced and transferred onto a substrate via an imaging optical system has been mainly used for transferring a fine pattern having a design dimension of about 1 μm or less.
[0003]
Improvement in resolution in the reduced projection exposure method has been pursued by shortening the wavelength of exposure light and increasing the NA of the imaging optical system. Further, recently, development of high resolution techniques such as a phase shift mask exposure method and a modified illumination exposure method has been advanced.
[0004]
In addition, the chip size has been gradually increased along with the high integration of elements. The maximum field size, which is an area that can be transferred by one exposure light, also gradually increases, and a recent step-and-repeat type reduction projection exposure apparatus (hereinafter, referred to as a stepper) has a size of 22 mm square (31. (1 mmφ) can be transferred. This method is a method of repeatedly transferring a plurality of chips onto a substrate by repeatedly performing mask pattern transfer and substrate stage movement by irradiation with exposure light in a step-and-repeat manner.
[0005]
As a device capable of transferring a larger area, a step-and-scan type reduction projection exposure apparatus (hereinafter, referred to as a scanner) has also been developed. In this method, a mask pattern is transferred by scanning an illumination area such as an arc shape or a slit shape on the mask while relatively moving the mask and the substrate in accordance with a predetermined mask pattern reduction ratio.
[0006]
However, it is predicted that it is very difficult to form a fine pattern of 100 nm or less using an optical lithography method even if various high resolution techniques are applied to these exposure apparatuses.
[0007]
On the other hand, an electron beam exposure method of drawing or transferring a pattern using an electron beam has been put to practical use as one of fine processing techniques capable of forming an extremely fine pattern of 100 nm or less. The method of the electron beam exposure method is a variable rectangular shaping type electron beam direct drawing method in which a pattern is directly drawn on a substrate using a rectangular shaped electron beam, or an electron beam shaped into a predetermined figure is repeatedly transferred. Several exposure methods have been developed, such as a cell projection type electron beam exposure method. However, in general, the electron beam exposure method has a problem that the throughput is lower than that of the optical lithography method in which a mask pattern is collectively transferred.
[0008]
Therefore, in order to suppress the decrease in throughput in the lithography process while utilizing the ultra-fine dimension processing performance of the electron beam exposure method, for example, a fine dimension pattern that cannot be transferred by the photolithography method is used in the electron beam exposure method. A method of mixing and matching a plurality of lithography techniques, such as transferring a relatively large pattern by an optical lithography method, has been used.
[0009]
[Problems to be solved by the invention]
In a scan type exposure apparatus, a substrate stage on which a substrate for transferring a mask pattern is mounted and a mask stage on which a mask is mounted are relatively precisely synchronized and moved in accordance with a mask pattern reduction ratio. Transfer the mask pattern. At this time, an error in stage movement may occur. This error affects the mask pattern transfer accuracy. In particular, an error in the pattern position due to a stage error greatly affects the overlay exposure accuracy.
[0010]
Similarly, when a pattern is transferred using an electron beam exposure apparatus, a movement error of a substrate stage on which a substrate is mounted may affect overlay exposure accuracy. Further, when a scan type exposure apparatus and an electron beam exposure apparatus are used in a mix-and-match manner, the difference between the respective stage movement positions of the two will affect the overlay exposure accuracy.
[0011]
Conventionally, since the overlay error caused by such a stage error has not been taken into account during overlay exposure, there has been a problem that the overlay accuracy is deteriorated.
[0012]
[Means for Solving the Problems]
The above problem is caused by illuminating an illumination area having a predetermined shape with exposure light, scanning the illumination area having the predetermined shape on a mask on which a mask pattern for transferring a first circuit pattern is formed, and By scanning the substrate in synchronization with the mask with respect to an exposure region of a predetermined shape projected onto the substrate by the projection optical system, the first circuit pattern is exposed on the substrate when the first circuit pattern is exposed on the substrate. A first circuit pattern transferred onto the substrate from information on a scanning position error when the illumination region scans on the mask and information on a scanning position error when the predetermined-shaped exposure region scans on the substrate. Calculating the information on the transfer position error of the first circuit pattern, and transferring the position of the second circuit pattern to the first circuit pattern on the substrate, and performing the transfer by overlaying. To The pattern transfer method of correcting the transfer position of the second circuit pattern so as to reduce the overlay error with the first circuit pattern using the information to be performed further illuminates an illumination area of a predetermined shape with exposure light. A predetermined-shaped exposure area in which the predetermined-shaped illumination area is scanned on a mask on which a mask pattern for transferring a second circuit pattern is formed, and the predetermined-shaped illumination area is projected onto a substrate by a projection optical system. By exposing the second circuit pattern onto the substrate by scanning the substrate with respect to an area in synchronization with the mask, information on a transfer position error of the first circuit pattern transferred onto the substrate when exposing the second circuit pattern onto the substrate. By correcting the scanning position when scanning the illumination area of the predetermined shape on the mask on which the mask pattern for transferring the second circuit pattern is formed, or by using the illumination of the predetermined shape. By correcting the scanning position when scanning the substrate in synchronization with the mask with respect to an exposure region of a predetermined shape projected on the substrate by the projection optical system, an overlay error with the first circuit pattern is corrected. According to the pattern transfer method for correcting the transfer position of the second circuit pattern so as to reduce the size of the second circuit pattern, the second circuit pattern is further transferred using an electron beam exposure method, and the second circuit pattern is Correcting the deflection position of the electron beam at the time of line exposure using information on the transfer position error of the first circuit pattern transferred onto the substrate, or correcting the drive position of the sample stage on which the substrate is mounted Thus, the problem is solved by the pattern transfer method for correcting the transfer position of the second circuit pattern so as to reduce the overlay error with the first circuit pattern.
[0013]
In order to correct the stage error, the stage may be adjusted and driven at the time of transfer of the overlay pattern based on the stage drive position at the time of transferring the overlay pattern. When transferring the superimposed pattern using an electron beam drawing apparatus, the transfer may be performed by correcting the electron beam deflection position without performing stage drive correction.
[0014]
The correction method will be further described with reference to FIG. First, Step 1 of transferring the first circuit pattern is processed. At this time, the stage driving result at the time of pattern transfer is monitored, information on the stage driving result and the transfer pattern position error is obtained in the storage device (step 2), and stored in the storage device (step 3). Since the stage position is monitored by the laser interference system, the result of driving the stage position is stored in the storage device via the control device. In the case of a scanner, information on a synchronous drive error between the substrate stage and the mask stage may be stored. At this time, information relating to mask pattern transfer, such as exposure date and time, lot identifier, processing wafer identifier, transfer chip arrangement, order, transfer pattern identifier, exposure apparatus identifier, and used mask identifier, is also stored at the same time, so that process processing is performed. The process can also be managed.
[0015]
The stored information can be sent to another exposure device by means such as a magnetic tape, a magnetic disk device, and a magneto-optical disk device. Further, if the control devices of the respective exposure apparatuses are connected to each other via a network, information can be transferred more easily. In addition, a control device for interconnecting the respective exposure apparatuses via a network and providing a common storage device for storing information between the respective exposure apparatuses, or exclusively operating such information relating to mask pattern exposure. The work can be performed more efficiently by providing.
[0016]
After processing step 4 of processing a predetermined circuit pattern, a second circuit pattern is superimposed and transferred on the first circuit pattern. At this time, the information stored as described above is read out (step 5), and the mask pattern may be transferred while correcting the stage drive position based on this information (step 6). For example, information relating to mask pattern transfer when the pattern to be superimposed is transferred may be called from the above-described storage device, and a correction amount of a mask pattern position to be transferred may be obtained from information relating to a driving result of the substrate stage or the mask stage.
[0017]
When transferring an overlay pattern using an electron beam drawing apparatus, a mask pattern may be drawn while correcting the substrate stage drive position based on information on the transfer result of the overlay pattern. It is also possible to correct the transfer pattern position by controlling the electron lens not the substrate stage drive position but the deflection amount of the electron beam for drawing the pattern.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
(Example 1)
A process for processing a circuit pattern of a 1 gigabit DRAM (dynamic random access memory) class large-scale integrated circuit having a minimum design dimension of 180 nm and a transfer chip size of 20 mm × 24 mm square will be described as an example.
[0019]
In the present embodiment, a KrF excimer laser exposure apparatus (reduction ratio: 4: 1) was used to transfer a wiring pattern of a predetermined semiconductor memory device onto a substrate that had been subjected to a predetermined process.
[0020]
An example of the configuration of a projection exposure apparatus that realizes the mask pattern exposure method of the present invention will be described with reference to FIG. Light emitted from the light source 31 is shaped by the masking blade 52 via the illumination optical system 30 and illuminates the mask 36.
[0021]
The mask 36 is mounted on a mask stage 48. The mask stage 48 is driven by the driving means 47 in response to a control command from the main control system 49, and can be moved to a desired position. The position of the mask stage 48 is accurately monitored by a laser length measuring device 54 as the position of a mirror 53 fixed on the stage. A pellicle 37 is provided on the mask 36 for preventing pattern transfer failure due to foreign matter adhesion.
[0022]
The mask pattern drawn on the mask 36 is projected via a projection lens 38 onto a wafer 39 as a sample substrate. The wafer 39 is vacuum-sucked on the substrate stage 40. The substrate stage 40 is mounted on a Z stage 41 movable in the optical axis direction of the projection lens 38, that is, in the Z direction, and further mounted on an XY stage 42. The Z stage 41 and the XY stage 42 are driven by the respective driving units 43 and 44 in accordance with control commands from the main control system 49, and can be moved to desired exposure positions. The position is accurately monitored by the laser length measuring device 45 as the position of the mirror 46 fixed to the Z stage 41. Further, the surface position of the wafer 39 is measured by a focus position detecting means included in a normal exposure apparatus. By driving the Z stage 41 in accordance with the measurement result, the surface of the wafer 39 can always be made to coincide with the imaging plane of the projection lens 38.
[0023]
The mask 36 is illuminated by the masking blade 52 with illumination light shaped into a slit. By moving the mask stage 48, the slit-shaped illumination light scans the mask 36, and the illuminated mask pattern on the mask 36 is transferred onto the wafer 39 which is moved in synchronization with the mask 36.
[0024]
Since the mask pattern reduction ratio is 4: 1, the driving amount of the mask stage 48 is driven to be four times larger than the driving amount of the substrate stage 40. For example, the amount of movement of the substrate stage 40 in the Y direction may be 4 with respect to the amount of movement of the mask stage 1 in the Y direction, and the substrate stage 40 may be continuously moved in the Y direction in synchronization with each other.
[0025]
In this embodiment, the size of the substrate for transferring the pattern was 6 inches φ, so in this embodiment, the exposure chips were arranged as schematically shown in FIG. Exposure was performed in the order indicated by arrows. .., 24, 25 in order from the first time, and the lot identifier is LOT154.
[0026]
The driving result of the substrate stage 40 and the driving result of the mask stage 48 at the time of pattern transfer are accurately monitored by the laser length measuring devices 45 and 54, respectively. The data was stored in a file format in the storage device 51 via the storage device 49. The storage device 51 is configured so that data can be shared between other exposure apparatuses via the network 425.
[0027]
The information on the pattern arrangement stored in the storage device 51 was transferred to the control device 201 dedicated to data processing connected to the network device 425 as shown in FIG. Such an apparatus configuration is effective for collective management of information on a processing process and production management.
[0028]
A predetermined gate pattern was transferred using a projection exposure apparatus. The driving results of the substrate stage 40 and the mask stage 48 are arithmetically processed to obtain information on a transfer pattern arrangement error caused by a synchronous driving error between them, and the obtained result is stored in the storage device 51 in a file format.
[0029]
In this embodiment, the information on the transfer pattern arrangement error is stored in a file format, but the storage method is not limited to this. The file has a file structure in which information on a lot identifier, an exposure date and time, an exposure apparatus identifier, a transfer pattern identifier, a used mask identifier, and a transfer pattern arrangement error is sequentially arranged from the first substrate to the 25th substrate from the top of the file. However, the contents to be stored, the order, the file format, and the like are not limited thereto.
[0030]
After the predetermined resist pattern development process, a predetermined wiring pattern was processed using the formed resist pattern as a mask. Next, an interlayer insulating film was formed on the substrate, and a second circuit pattern for a predetermined electrode extraction hole was transferred using an electron beam exposure apparatus. A configuration example of an electron beam exposure apparatus that realizes the pattern transfer method of the present invention will be described with reference to FIG. Electrons 402 emitted from an electron gun 401 are focused by a plurality of electron lenses 403 and 404, deflected by deflection lenses 405 and 406, and irradiated on a wafer 408 on a stage 407. At this time, the shape of the electron beam is determined by the two apertures 409 and 410. For example, an aperture as shown in FIG. 7 is mounted on the second aperture support 410, and an arbitrary aperture pattern on the second aperture support 410 is selected and used by the electron beam forming lenses 411 and 412. At the same time, since a rectangular aperture pattern is formed at the center of the aperture support 401, the aperture support 401 can be used as a variable rectangular electron beam drawing apparatus. The wafer 408 can be moved in and out of the apparatus via the sample exchange chamber 415 without breaking the high vacuum atmosphere in the sample chamber 413.
[0031]
The system of the entire device is controlled by a control device 423, and a storage device 424 for storing data is connected. Further, the control device 423 is connected to the network device 425, and is connected so as to be able to perform data communication with other exposure apparatuses and process apparatuses.
[0032]
In the present embodiment, information on the pattern arrangement stored in the storage device 202 in a file format via the network device 425 is read into the control device 423. Unlike the present embodiment, when the control device and the storage device are not connected to the network device and the exposure device has a stand-alone configuration, the storage device is provided via a movable storage means such as a magnetic tape, a magnetic disk, or a magneto-optical disk. Information may be transferred.
[0033]
Using the information on the pattern arrangement read as described above, the transfer position when transferring the predetermined electrode extraction hole pattern was corrected.
[0034]
FIG. 12 is a diagram illustrating a result of monitoring a result of driving the substrate stage 40 in the y direction with respect to a certain chip when the first circuit pattern is transferred. The horizontal axis represents the reference coordinate position used when driving the substrate stage 40, and the vertical axis represents the amount of deviation from the reference coordinate position obtained from the monitoring result of the driving result of the substrate stage. In the figure, the portion where the driving error is less than 20 nm is cut off and displayed from the actual monitoring result. This is because the reproducibility of the stage drive position was about 20 nm, and it was difficult to sufficiently correct the pattern transfer position in consideration of the stage drive accuracy.
[0035]
FIG. 9 schematically shows a two-dimensional transfer pattern arrangement of the first circuit pattern, which is the pattern to be overlaid, using the results of FIG. The grid points in the figure are diagrams schematically showing shifts of transfer pattern positions at 2 mm pitch grid point positions in a 20 mm × 24 mm square transfer pattern. Each grid point position indicates a transfer position of the first circuit pattern based on a case where there is no transfer pattern position error. In this example, the distance between the lattice points 11 in the y direction is reduced by 20 nm with respect to the reference length of 2 mm, and the distance in the y direction between the lattice points 12 is enlarged by 20 nm with respect to the reference length of 2 mm.
[0036]
In the following, an example in which the stage is scanned in the y direction and the transfer is performed mainly in the y direction will be described. However, as shown in FIG. Positional errors may also occur. However, in the x direction perpendicular to the scanning direction, if the transfer chip magnification of the projection exposure apparatus is constant, the transfer pattern position is shifted and transferred. In FIG. 10, the x-direction position between the lattice points 13 is shifted by 25 nm in the minus direction, the x-direction position between the lattice points 14 is shifted by 25 nm in the plus direction, and the y-direction distance is enlarged by 20 nm with respect to the reference length of 2 mm. An example is shown. Also in this case, the method described below can be applied and applied.
[0037]
For example, information on the circuit pattern arrangement as shown in FIG. 9 is obtained from the information on the pattern arrangement described above, and the transfer position of the electrode extraction hole pattern can be corrected using this information. In the present embodiment, the deflection of the electron beam is controlled and corrected by controlling the deflecting lenses 405 and 406 using the information on the pattern arrangement described above, so that the electrode take-out hole pattern transfer position matches the first circuit pattern transfer position. Was corrected. The pattern transfer position may be corrected by correcting the drive position of the stage 407.
[0038]
FIG. 5 is a cross-sectional view showing a manufacturing process of the device. As shown in FIG. 5A, a P-type Si semiconductor 71 is used for a substrate. An element isolation region 72 is formed on the surface by using a known element isolation technique. Next, a word line 73 having a structure in which, for example, polycrystalline silicon having a thickness of 150 nm and silicon oxide having a thickness of 200 nm is stacked is formed, and silicon oxide having a thickness of, for example, 150 nm is deposited using a chemical vapor deposition method. Then, anisotropic processing is performed to form silicon oxide side spacers 74 on the side walls of the word lines. Next, an n diffusion layer 75 is formed by a usual method.
[0039]
Next, as shown in FIG. 5B, a data line 76 made of polycrystalline silicon, a high-melting-point metal silicide, or a laminated film thereof is formed through a normal process. Next, as shown in FIG. 5C, a storage electrode 78 made of polycrystalline silicon is formed through a normal process. Thereafter, tantalum pentoxide, silicon nitride, silicon oxide, a ferroelectric material, or a composite film of these materials is applied to form a capacitor insulating film 79. Subsequently, a low-resistance conductor such as polycrystalline silicon, high-melting-point metal, high-melting-point metal silicide, or Al or Cu is applied to form the plate electrode 80.
[0040]
Next, as shown in FIG. 5D, a wiring 81 is formed through a normal process. Next, a semiconductor memory element was manufactured through a normal wiring layer forming step and a passivation step. Although only typical manufacturing steps have been described here, a normal element manufacturing step is used for other steps. In the lithography process in the device manufacturing process, a photolithography method was applied to some of the processes, and the pattern was transferred using the above-described projection exposure apparatus.
[0041]
Next, the pattern formed in the lithography process will be described. FIG. 6 shows a pattern arrangement of a memory portion of a typical pattern constituting a manufactured semiconductor memory element. FIG. 6A shows an example of the pattern of the manufactured first element. 82 is a word line, 83 is a data line, 84 is an active area, 85 is a storage electrode, and 86 is a pattern of an electrode extraction hole. In this embodiment, in the pattern shown in FIG. 6A, the above-described projection exposure apparatus and the phase shift mask are used for transferring the patterns of the word line 82, the data line 83, and the active area 84. In the pattern shown in FIG. 6A, a pattern for forming the electrode extraction hole 86 and the storage electrode 85 was transferred using an electron beam exposure apparatus.
[0042]
FIG. 6B shows an example of a pattern of the manufactured second element. 87 is a word line, 88 is a data line, 89 is an active area, 90 is a storage electrode, and 91 is a pattern of an electrode extraction hole. Also in this example, a projection exposure apparatus was used to transfer patterns of word lines, data lines, and active areas, and an electron beam exposure apparatus was used to transfer patterns of electrode extraction holes and storage electrodes.
[0043]
After transferring the pattern as described above, when the overlay error between the predetermined wiring pattern and the predetermined electrode extraction hole pattern was measured using an electron microscope, the portion where the overlay error was larger than 80 nm was observed. Was not done. That is, the overlay error between the two patterns was within the desired overlay error tolerance, and the desired overlay accuracy was achieved.
[0044]
By manufacturing a large-scale integrated circuit device by applying the method described above, it is possible to process a predetermined circuit pattern with a desired accuracy, so that the device can be manufactured with a high yield. It is. Further, since the processing variation can be reduced, it is possible to manufacture a circuit element having stable characteristics. That is, it is possible to manufacture elements with a high yield.
[0045]
It should be noted that the present invention is not limited to the above-described embodiment, and the present invention can be applied and applied without departing from the gist of the present invention.
[0046]
(Example 2)
In the present embodiment, a process of processing a circuit pattern of a large-scale integrated circuit of 256 megabit DRAM class having a minimum design dimension of 250 nm and a transfer chip size of 20 mm square will be described as an example.
[0047]
FIG. 8 shows the configuration of the exposure apparatus used in this embodiment. The exposure devices 426A, 426B, and 426C are controlled by control devices 423A, 423B, and 423C, respectively, and storage devices 424A, 424B, and 424C are connected to the respective control devices. Further, a storage device 202 is connected to the control device 201. Since the control devices 423A, 423B, 423C, and 201 are connected to the network device 425, data communication between the control devices is possible via the network device 425. The control device 201 and the storage device 202 are provided to exclusively manage the processing result, processing state, and the like of each processing device. A processing apparatus (not shown) other than the lithography apparatus is also connected to the network apparatus 425. Further, the data communication device 427 can perform data communication with a control device that is not directly connected to the network device 425.
[0048]
First, a first circuit pattern was transferred in the same manner as in Example 1. The first circuit pattern was transferred using a projection exposure apparatus 426A. At this time, the result of driving the substrate stage 40 and the result of driving the mask stage 48 during pattern transfer are monitored by the laser length measuring devices 45 and 54, respectively, and information on the pattern arrangement error obtained by processing the monitored results is controlled. The data was stored in a file format in the storage device 424A via the device 423A. Further, the data is transferred to the control device 201 via the network device 425, and stored and stored in the storage device 202.
[0049]
Next, the second circuit pattern was transferred using a second projection exposure apparatus 426B having the same configuration as that of transferring the first circuit pattern. In this embodiment, the information on the pattern arrangement stored in the storage device 202 in the file format via the network device 425 and the control device 201 is read into the control device 423B. Unlike the present embodiment, when the control device and the storage device are not connected to the network device and the exposure device has a stand-alone configuration, movable storage means such as a magnetic tape, a magnetic disk, and a magneto-optical disk are used. The information may be transferred via the Internet.
[0050]
Using the information on the pattern arrangement of the first circuit pattern read as described above, the drive position of the mask stage 48 is corrected so as to reduce the overlay error of the second circuit pattern on the first circuit pattern. Then, the second circuit pattern was transferred. The pattern transfer position of the second circuit pattern may be corrected by correcting the drive position of the substrate stage 40 or by correcting the drive positions of both the substrate stage 40 and the mask stage 48.
[0051]
After transferring the pattern as described above, when the overlay error between the first circuit pattern and the second circuit pattern was measured using an electron microscope, the overlay error was greater than 100 nm. No parts were observed. That is, the overlay error between the two patterns was within the desired overlay error tolerance, and the desired overlay accuracy was achieved.
[0052]
In the pattern shown in FIG. 6B, the method described in this embodiment is used, for example, when the word line 87 is overlaid and transferred on the active region 89, but the present invention is not limited to this.
[0053]
By manufacturing a large-scale integrated circuit device by applying the method described above, it is possible to process a predetermined circuit pattern with a desired accuracy, so that the device can be manufactured with a high yield. It is. Further, since the processing variation can be reduced, it is possible to manufacture a circuit element having stable characteristics. That is, it is possible to manufacture elements with a high yield.
[0054]
(Example 3)
In the present embodiment, a process of processing a circuit pattern of a 1 gigabit DRAM-class large-scale integrated circuit having a minimum design dimension of 180 nm and a transfer chip size of 20 mm square will be described as an example.
[0055]
First, the first circuit pattern was transferred using the electron beam exposure apparatus 426C. At this time, the result of driving the substrate stage 407 during pattern transfer was monitored. Further, a distortion error in an exposure field of the electron beam exposure apparatus when the first circuit pattern is transferred and a pattern arrangement error of the first circuit pattern obtained by performing arithmetic processing using the above-described substrate stage drive position monitoring result. Is stored in a file format in the storage device 424C via the control device 423C. Further, the data is transferred to the control device 201 via the network device 425, and stored and stored in the storage device 202.
[0056]
Next, the second circuit pattern was transferred using the electron beam exposure apparatus 426C. In this embodiment, the information on the pattern arrangement stored in the storage device 202 in the file format via the network device 425 and the control device 201 is read into the control device 423C.
[0057]
By using the information on the pattern arrangement of the first circuit pattern read as described above, the deflection lenses 405 and 406 are controlled so as to reduce the overlay error of the second circuit pattern on the first circuit pattern. The transfer position of the second circuit pattern was corrected by adjusting the deflection of the electron beam. Note that the distortion error of the electron beam exposure apparatus during the exposure of the second circuit pattern was corrected on the exposure apparatus side in advance using a predetermined method before the exposure.
[0058]
FIG. 11 schematically shows the pattern arrangement of the first circuit pattern in this embodiment. In the area where the grid points 15A and 15B overlap, and in the area where the grid points 16A and 16B overlap, the pattern transfer position is linearly interpolated at each grid point position according to the shift of the transfer pattern position at each grid point position. Corrected. Note that the transfer position of the second circuit pattern may be corrected by correcting the drive position of the stage 407.
[0059]
In the pattern shown in FIG. 6B, the method described in the present embodiment is used, for example, when the electrode extraction hole pattern 91 is overlapped and transferred to the data line 88, but is not limited to this. .
[0060]
After transferring the pattern as described above, when the overlay error between the first circuit pattern and the second circuit pattern was measured using an electron microscope, the overlay error was greater than 100 nm. No parts were observed. That is, the overlay error between the two patterns was within the desired overlay error tolerance, and the desired overlay accuracy was achieved.
[0061]
By manufacturing a large-scale integrated circuit device by applying the method described above, it is possible to process a predetermined circuit pattern with a desired accuracy, so that the device can be manufactured with a high yield. It is. Further, since the processing variation can be reduced, it is possible to manufacture a circuit element having stable characteristics. That is, it is possible to manufacture elements with a high yield.
[0062]
【The invention's effect】
According to the present invention, a pattern can be transferred with high overlay accuracy.
[Brief description of the drawings]
FIG. 1 is a flowchart of a process showing a process according to the present invention.
FIG. 2 is a block diagram of a projection exposure apparatus used in the embodiment.
FIG. 3 is an explanatory diagram showing a pattern transfer order in the embodiment.
FIG. 4 is a block diagram showing a configuration of an electron beam exposure apparatus used in the embodiment.
FIG. 5 is a sectional view of an element in the process of manufacturing the semiconductor device manufactured in the example.
FIG. 6 is a plan view showing a pattern arrangement of the semiconductor device manufactured in the embodiment.
FIG. 7 is a plan view showing an aperture used in the electron beam exposure apparatus.
FIG. 8 is a block diagram of an exposure apparatus group in the embodiment.
FIG. 9 is an explanatory diagram showing an example of a displacement of a transfer pattern.
FIG. 10 is an explanatory diagram showing an example of a displacement of a transfer pattern.
FIG. 11 is an explanatory diagram showing an example of a displacement of a transfer pattern.
FIG. 12 is an explanatory diagram showing a driving position error of the substrate stage.
[Explanation of symbols]
1. Step of transferring the first circuit pattern, 2. Step of obtaining a transfer position error of the first circuit pattern, 3. Step of storing information on the transfer position error, 4. Step of processing the circuit pattern, 5. A step of reading information relating to the transfer position error; 6 a step of transferring the second circuit pattern while correcting the transfer position; 7 a step of processing the circuit pattern.

Claims (10)

Illuminating an illumination region of a predetermined shape in the exposure light, it causes to scan over a mask illumination area of the predetermined shape by scanning the mask first circuit pattern is formed, projecting the illumination area of the predetermined shape optical system when exposing the first circuit pattern on the substrate by scanning the substrate in synchronization with the mask relative to the exposure area of the predetermined shape is projected on the substrate using, in the exposure exposure apparatus and a second detection system for detecting a first detection system and the sample stage of the scanning position of mounting the substrate for detecting the scanning position of the mask stage of mounting the mask used, the first run the process and the detected scanning position, and the sample stage of the mask stage for detecting the sample stage of a scanning position using the second detecting system detects the scanning position of the mask stage by using a detection system A step of the information about the position finding information about the transfer position of the first circuit pattern, said when transferring superimposed by aligning the second circuit pattern on the first circuit pattern on the substrate first and correcting the transfer position of the second circuit pattern so as to reduce the overlay error between the first circuit pattern superimposing said second circuit pattern by using the information about the transfer position of the circuit pattern of 1 A method for manufacturing a solid state device, comprising a step of transferring. Illuminating an illumination area of the predetermined shape in the exposure light, with the illumination area of the predetermined shape is scanned over the second mask by scanning the second mask said second circuit pattern is formed , said second circuit pattern by synchronously with the mask with respect to the exposure area of the predetermined shape is projected onto the substrate for scanning the substrate with the predetermined shape projection optical system an illumination area when exposing overlay aligned with respect to the first circuit pattern on the substrate, the first circuit pattern the first circuit pattern by using the information about the transfer position and said second circuit pattern superimposing one of the scanning position and the substrate placed on the sample stage of the scanning position of said mask stage and the second mask is placed so as to reduce the displacement amount, or correct both of Method for manufacturing a solid-state device of claim 1, wherein the that. While transcription using an electron beam exposure method the second circuit pattern, when the electron beam exposure of the second circuit pattern by using the information about the transfer position of the first circuit pattern has been transferred on the substrate 2. The solid state according to claim 1 , wherein the transfer position of said second circuit pattern is corrected so as to reduce the overlay error with said first circuit pattern by correcting the deflection amount of said electron beam. Device manufacturing method . While transferring the second circuit pattern using an electron beam exposure method, the sample stage of the driving position of mounting the substrate using the information about the transfer position error of the first circuit pattern has been transferred on the substrate method for manufacturing a solid-state device of claim 1, wherein the correcting the transfer position of the second circuit pattern so as to reduce the overlay error between the first circuit pattern by correcting the. The step of storing one or more of the information on the detected scan position of the mask stage, the information on the scan position of the sample stage, and the information on the transfer position of the first circuit pattern is performed by the second circuit pattern. The method according to claim 1, wherein the method is performed before the step of superimposing and transferring. The first circuit pattern formed on the mask is transferred onto the substrate while the mask stage on which the first mask having the first circuit pattern is mounted and the sample stage on which the substrate is mounted are scanned synchronously. In doing, obtaining information on the transfer position of the first circuit pattern on the substrate based on the scan position error of the mask stage and the scan position error of the sample stage, and storing,
When transferring the second circuit pattern onto the substrate using an electron beam, the second circuit pattern is transferred onto the substrate while correcting the transfer position of the second circuit pattern using the stored information on the transfer position. Transferring the circuit pattern of the above. The correction of the transfer position of the second circuit pattern includes controlling the deflection of the electron beam. 7. The method according to claim 6, wherein the method is performed. 7. The method according to claim 6, wherein the correction of the transfer position of the second circuit pattern is performed by correcting a drive position of a second sample stage on which the substrate is mounted. A method for manufacturing a solid-state device having a step of transferring a desired circuit pattern formed on the mask to the substrate while scanning in synchronization with a mask stage on which the mask is mounted and a sample stage on which the substrate is mounted,
Using a first mask having a first circuit pattern, the first mask is formed on a substrate. 1 When transferring the circuit pattern of, the information on the transfer position of the first circuit pattern on the substrate based on the scan position error of the mask stage and the scan position error of the sample stage, and storing, afterwards,
When transferring the second circuit pattern onto the substrate using the second mask having the second circuit pattern, the transfer position of the second circuit pattern is stored using the stored information on the transfer position. Transferring the second circuit pattern to the substrate while correcting the following. 10. The method according to claim 9, wherein the correction of the transfer position of the second circuit pattern is performed by controlling a scanning speed of a mask stage or a sample stage.

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