JPH09129490A - Laminated capacitor - Google Patents
Laminated capacitorInfo
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- JPH09129490A JPH09129490A JP28005695A JP28005695A JPH09129490A JP H09129490 A JPH09129490 A JP H09129490A JP 28005695 A JP28005695 A JP 28005695A JP 28005695 A JP28005695 A JP 28005695A JP H09129490 A JPH09129490 A JP H09129490A
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- electrode
- internal
- internal electrodes
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- interval
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Abstract
Description
【0001】[0001]
【発明が属する技術分野】本発明は、積層コンデンサに
関し、特に静電容量の小さな高周波用の積層コンデンサ
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor, and more particularly to a high-frequency multilayer capacitor having a small capacitance.
【0002】[0002]
【従来の技術】図2乃至図4に従来例の積層コンデンサ
を示す。図2は分解斜視図、図3は平面図、図4は図3
のA−A線矢視方向断面図である。2. Description of the Related Art FIGS. 2 to 4 show a conventional multilayer capacitor. 2 is an exploded perspective view, FIG. 3 is a plan view, and FIG.
3 is a sectional view taken along line AA of FIG.
【0003】図において、10は積層コンデンサで、誘
電体層11と内部電極12とを交互に積層してなる素体
13と、素体13の両端部において内部電極を交互に並
列に接続している一対の外部電極14とから構成されて
いる。[0003] In the drawing, reference numeral 10 denotes a multilayer capacitor in which a dielectric body 13 formed by alternately laminating dielectric layers 11 and internal electrodes 12 and internal electrodes are alternately connected in parallel at both ends of the dielectric body 13. And a pair of external electrodes 14.
【0004】内部電極12は、誘電体層11の中央領域
付近に設けられた内部電極片12aと、外部電極14に
沿って外部電極14に接続した状態で設けられた内部電
極引出部12bとから成り、内部電極片12aは内部電
極引出部12bを介して外部電極14に接続されてい
る。The internal electrode 12 is composed of an internal electrode piece 12a provided near the central region of the dielectric layer 11 and an internal electrode lead portion 12b provided along the external electrode 14 and connected to the external electrode 14. The internal electrode piece 12a is connected to the external electrode 14 via the internal electrode lead-out portion 12b.
【0005】誘電体層11は矩形のシート上のセラミッ
ク焼結体からなり、セラミック焼結体は、例えばチタン
酸バリウム等を主成分とする誘電体磁器材料から形成さ
れている。内部電極12は金属ペーストを焼結させた金
属薄膜からなり、金属ペーストとしては、例えばPdや
Ag−Pdのような貴金属材料を主成分とするものが使
用されている。外部電極14もない部電極12と同様の
材料により形成され、表面には半田濡れ性をよくするた
めに半田メッキが施されている。[0005] The dielectric layer 11 is formed of a ceramic sintered body on a rectangular sheet, and the ceramic sintered body is formed of a dielectric ceramic material containing, for example, barium titanate as a main component. The internal electrode 12 is formed of a metal thin film obtained by sintering a metal paste. As the metal paste, for example, an electrode mainly containing a noble metal material such as Pd or Ag-Pd is used. It is formed of the same material as the part electrode 12 without the external electrode 14, and its surface is plated with solder to improve solder wettability.
【0006】[0006]
【発明が解決しようとする課題】ところで、近年、移動
通信機器等に使用される通信用の周波数が高周波帯(G
Hz帯)へ移行してきており、これに伴って移動通信機
器等に使用される積層コンデンサも高周波帯への対応を
余儀なくされている。In recent years, communication frequencies used in mobile communication devices and the like have been changed to high frequency bands (G-bands).
(Hz band), and accordingly, multilayer capacitors used in mobile communication devices and the like have to be adapted to the high frequency band.
【0007】積層コンデンサを高周波帯へ対応させるた
めには、高周波域において低容量、例えば10pF以下
の静電容量の積層コンデンサのQ値を高める必要があ
る。In order to make a multilayer capacitor compatible with a high frequency band, it is necessary to increase the Q value of a multilayer capacitor having a low capacitance, for example, a capacitance of 10 pF or less in a high frequency range.
【0008】このように高周波域において、低容量の積
層コンデンサのQ値を高めるためには、内部電極の電気
抵抗を小さくする必要がある。As described above, in order to increase the Q value of a low-capacitance multilayer capacitor in a high-frequency range, it is necessary to reduce the electric resistance of internal electrodes.
【0009】内部電極の電気抵抗を小さくする方法とし
ては、内部電極の面積を広くしたり、内部電極の厚みを
厚くしたりする方法がある。As a method of reducing the electric resistance of the internal electrode, there are methods of increasing the area of the internal electrode and increasing the thickness of the internal electrode.
【0010】しかしながら、内部電極の面積を大きくす
ると静電容量が大きくなりすぎるので、内部電極間の距
離を広げたり、積層数を減らしたりしなければならず、
このため、内部電極間の電気抵抗が高まったり、Q値が
低下したりする。However, when the area of the internal electrodes is increased, the capacitance becomes too large. Therefore, it is necessary to increase the distance between the internal electrodes and reduce the number of layers.
For this reason, the electric resistance between the internal electrodes increases or the Q value decreases.
【0011】また、内部電極を厚くすると、内部電極の
電気抵抗は下がるが、内部電極の局部的な累積によりそ
の部分は局部的に厚くなって内部歪みが増大したり、P
d等からなる内部電極の酸化膨張により、構造欠陥(デ
ラミネーション、クラック等)の発生率が大きくなって
しまう。When the internal electrode is made thicker, the electric resistance of the internal electrode is lowered. However, due to the local accumulation of the internal electrode, the portion is locally thickened and the internal strain is increased.
Due to oxidative expansion of the internal electrode made of d or the like, the incidence of structural defects (delamination, cracks, etc.) increases.
【0012】本発明の目的は上記の問題点に鑑み、高周
波域において高いQ値を有すると共に内部構造欠陥のな
い積層コンデンサを提供することにある。In view of the above problems, an object of the present invention is to provide a multilayer capacitor having a high Q value in a high frequency range and free from internal structural defects.
【0013】[0013]
【課題を解決するための手段】本発明は上記の目的を達
成するために、誘電体層を介在させ所定の間隔t1 をあ
けて平行に設けた所定幅D及び厚さt2 を有する少なく
とも2枚の内部電極からなる電極群と誘電体層とを交互
に積層してなる素体と、該素体の両端部において前記電
極群を交互に並列に接続している一対の外部電極とを有
し、前記内部電極の幅Dと、前記電極群における2枚の
内部電極間の間隔t1 との比(D/t1)が0.86以
上5.60以下の所定値となるように、且つ前記電極群
における2枚の内部電極間の間隔t1 と前記内部電極の
厚さt2 との比(t1 /t2 )が1.5以上29.0以
下の所定値となるように、前記内部電極の幅D及び厚さ
t2 並びに前記電極群における2枚の内部電極間の間隔
t1 が設定されている積層コンデンサを提案する。In order to achieve the above-mentioned object, the present invention has at least a predetermined width D and a thickness t 2 which are provided in parallel with each other with a dielectric layer interposed and at a predetermined interval t 1. An element body formed by alternately laminating an electrode group composed of two internal electrodes and a dielectric layer, and a pair of external electrodes in which the electrode groups are alternately connected in parallel at both ends of the element body are provided. So that the ratio (D / t 1 ) of the width D of the internal electrode to the interval t 1 between the two internal electrodes in the electrode group becomes a predetermined value of 0.86 or more and 5.60 or less. Also, the ratio (t 1 / t 2 ) of the distance t 1 between the two internal electrodes in the electrode group and the thickness t 2 of the internal electrodes is set to a predetermined value of 1.5 or more and 29.0 or less. the interval t 1 between the two inner electrodes in the width D and the thickness t 2 and the electrode group of the internal electrodes is set Suggest layer capacitor.
【0014】該積層コンデンサによれば、誘電体層を介
在させ所定の間隔t1 をあけて平行に設けた所定幅D及
び厚さt2 を有する少なくとも2枚の内部電極からなる
電極群と誘電体層とが交互に積層されてなる素体の両端
部において、前記電極群を交互に並列に接続する一対の
外部電極が設けられ積層コンデンサが形成される。ここ
で、前記内部電極の幅Dと、前記電極群における2枚の
内部電極間の間隔t1との比(D/t1 )が0.86以
上5.60以下の所定値となるように、且つ前記電極群
における2枚の内部電極間の間隔t1 と、前記内部電極
の厚さt2 との比(t1 /t2 )が1.5以上29.0
以下の所定値となるように、前記内部電極の幅D及び厚
さt2 並びに前記電極群における2枚の内部電極間の間
隔t1 が設定されている。According to the multilayer capacitor, an electrode group consisting of at least two internal electrodes having a predetermined width D and a thickness t 2 which are provided in parallel with each other with a dielectric layer interposed therebetween and having a predetermined interval t 1 therebetween, and a dielectric A multilayer capacitor is formed by providing a pair of external electrodes that alternately connect the electrode groups in parallel at both ends of an element body that is formed by alternately stacking body layers. Here, the ratio (D / t 1 ) of the width D of the internal electrode to the interval t 1 between the two internal electrodes in the electrode group is set to a predetermined value of 0.86 or more and 5.60 or less. The ratio (t 1 / t 2 ) of the distance t 1 between the two internal electrodes in the electrode group and the thickness t 2 of the internal electrodes is 1.5 or more and 29.0 or more.
The width D and the thickness t 2 of the internal electrode and the interval t 1 between the two internal electrodes in the electrode group are set so as to have the following predetermined values.
【0015】前記電極群における2枚の内部電極間の間
隔t1 との比(D/t1 )を0.86以上5.60以下
の所定値となるように設定することにより、2枚の内部
電極からなる電極群が同等の厚さを有する電極と同等の
働きをし、高周波域における内部電極内における損失を
小さくできると共に、電気抵抗を小さくできる。さら
に、前記電極群における2枚の内部電極間の間隔t1 と
前記内部電極の厚さt2との比(t1 /t2 )を1.5
以上29.0以下の所定値となるように設定することに
より、内部電極を必要最小限に薄く形成できるため、内
部電極の局部的な累積による内部歪みを回避できる。By setting the ratio (D / t 1 ) to the interval t 1 between the two internal electrodes in the electrode group to a predetermined value of 0.86 or more and 5.60 or less, the two electrodes The electrode group composed of the internal electrodes has the same function as an electrode having the same thickness, and it is possible to reduce the loss in the internal electrodes in the high frequency range and also reduce the electrical resistance. Furthermore, the ratio (t 1 / t 2 ) of the distance t 1 between the two internal electrodes in the electrode group and the thickness t 2 of the internal electrodes is set to 1.5.
By setting the internal electrode to a predetermined value of 29.0 or less, the internal electrode can be formed to be as thin as necessary, so that internal strain due to local accumulation of the internal electrode can be avoided.
【0016】[0016]
【発明の実施の形態】以下、図面に基づいて本発明の一
実施形態を説明する。図1は本実施形態における積層コ
ンデンサの外観図、図5は要部分解斜視図、図6は側面
断面図である。図1において、20は積層コンデンサ
で、誘電体層及び内部電極を積層してなる素体21と、
この素体21の両端部において内部電極23に接続する
ように設けられた一対の外部電極22a,22bから構
成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is an external view of the multilayer capacitor according to the present embodiment, FIG. 5 is an exploded perspective view of main parts, and FIG. 6 is a side sectional view. In FIG. 1, reference numeral 20 is a multilayer capacitor, and an element body 21 formed by laminating dielectric layers and internal electrodes,
It is composed of a pair of external electrodes 22a, 22b provided so as to be connected to the internal electrodes 23 at both ends of the element body 21.
【0017】また、素体21は図5及び図6に示すよう
に、その内部に例えば第1乃至第5の誘電体層21A〜
21Eを有し、第2の誘電体層21Bの上下面のそれぞ
れには内部電極23a,23bが形成され、1つの電極
群24aが構成されている。Further, as shown in FIGS. 5 and 6, the element body 21 has therein, for example, first to fifth dielectric layers 21A to 21A.
21E, the internal electrodes 23a and 23b are formed on the upper and lower surfaces of the second dielectric layer 21B, and one electrode group 24a is formed.
【0018】これらの内部電極23a,23bは同一形
状をなし、誘電体層21Bの長手方向一端において一方
の外部電極22aに接続され、この一端から他端側に向
けて所定長延ばして形成されている。また、これらの内
部電極23a,23bの間隔t1 は18μmに設定さ
れ、それぞれの内部電極23a,23bの幅Dは100
μm、厚さt2 は12μmに設定されている。These internal electrodes 23a and 23b have the same shape, are connected to one external electrode 22a at one longitudinal end of the dielectric layer 21B, and extend from this one end toward the other end by a predetermined length. There is. The distance t 1 between the internal electrodes 23a and 23b is set to 18 μm, and the width D of each internal electrode 23a and 23b is 100 μm.
The thickness t 2 is set to 12 μm.
【0019】同様にして、第4の誘電体層21Dの上下
面のそれぞれには内部電極23c,23dが形成され、
1つの電極群24bが構成されている。これらの内部電
極23c,23dも前述と同様に同一形状をなし、誘電
体層21Dの長手方向他端において他方の外部電極22
bに接続され、ここから一端側に向けて所定長延ばして
形成されている。また、これらの内部電極23c,23
dの間隔t1 、幅D、厚さt2 は、第2の誘電体層21
Bに形成された内部電極と同様に、18μm、100μ
m、12μmに設定されている。Similarly, internal electrodes 23c and 23d are formed on the upper and lower surfaces of the fourth dielectric layer 21D, respectively.
One electrode group 24b is configured. These internal electrodes 23c, 23d also have the same shape as described above, and the other external electrode 22 is formed at the other end in the longitudinal direction of the dielectric layer 21D.
It is connected to b and is formed by extending a predetermined length from here to one end side. In addition, these internal electrodes 23c, 23
The distance t 1 , the width D, and the thickness t 2 of d are the same as those of the second dielectric layer 21.
18 μm, 100 μ, similar to the internal electrode formed on B
m and 12 μm.
【0020】これにより、一方の電極群24aと他方の
電極群24bは、第3の誘電体層21Cを介してそのほ
ぼ中央部分において所定の面積で重なり合い、それぞれ
の平面が対向して高周波用の小さな静電容量が得られる
ようになっている。As a result, the one electrode group 24a and the other electrode group 24b overlap each other in a predetermined area in the substantially central portion thereof with the third dielectric layer 21C interposed therebetween, and their respective planes face each other for high frequency. A small capacitance is obtained.
【0021】ここで、内部電極23a〜23dの幅D
と、電極群における2枚の内部電極間の間隔t1 との比
(D/t1 )が0.86以上5.60以下の所定値とな
るように、且つ電極群における2枚の内部電極間の間隔
t1 と、内部電極の厚さt2 との比(t1 /t2 )が
1.5以上29.0以下の所定値となるように、内部電
極23a〜23dの幅D及び厚さt2 並びに電極群24
a,24bにおける2枚の内部電極間の間隔t1 を設定
することが好ましい。Here, the width D of the internal electrodes 23a-23d
And the ratio (D / t 1 ) of the distance t 1 between the two internal electrodes in the electrode group to a predetermined value of 0.86 or more and 5.60 or less, and the two internal electrodes in the electrode group. the spacing t 1 between, as the ratio of the thickness t 2 of the internal electrodes (t 1 / t 2) becomes a predetermined value of 1.5 or more 29.0 or less, and the width D of the internal electrode 23a~23d Thickness t 2 and electrode group 24
It is preferable to set the interval t 1 between the two internal electrodes at a and 24b.
【0022】即ち、D/t1 <0.86であるとき、或
いはt1 /t2 >29.0であるときは高周波域におけ
るQ値が低下してしまう。また、D/t1 >5.60で
あるときは潜在内部応力歪みが大きくなり、クラックの
発生やデラミネーションが起こりやすくなり構造欠陥が
増大する。さらに、t1 /t2 <1.5であるときは厚
い内部電極と薄い誘電体層を積層することになるため、
積層精度の悪化を招くと共に、クラックの発生や絶縁破
壊を生じやすくなる。That is, when D / t 1 <0.86 or when t 1 / t 2 > 29.0, the Q value in the high frequency range is lowered. Further, when D / t 1 > 5.60, the latent internal stress strain increases, cracks and delamination easily occur, and structural defects increase. Further, when t 1 / t 2 <1.5, a thick internal electrode and a thin dielectric layer are laminated,
This leads to deterioration of the stacking accuracy, and tends to cause cracks and dielectric breakdown.
【0023】前述の構成よりなる本実施形態によれば、
2枚の内部電極からなる電極群24a,24bが同等の
厚さを有する内部電極と同等の働きをし、高周波域にお
ける内部電極内における損失を小さくできると共に、電
気抵抗を小さくできるので、高周波域におけるQ値を高
めることができる。According to the present embodiment having the above-mentioned configuration,
The electrode groups 24a and 24b composed of two internal electrodes have the same function as the internal electrodes having the same thickness, and the loss in the internal electrodes in the high frequency region can be reduced and the electric resistance can be reduced, so that the high frequency region can be reduced. It is possible to increase the Q value at.
【0024】さらに、内部電極23a〜23dを必要最
小限に薄く形成できるため、内部電極23a〜23dの
局部的な累積による内部歪みを回避できるので、Pd等
からなる内部電極の酸化膨張によるデラミネーションや
クラック等の構造欠陥の発生率を大幅に低減することが
でき、信頼性の高い積層コンデンサを得ることができ
る。Further, since the internal electrodes 23a to 23d can be formed to be as thin as necessary, internal strain due to local accumulation of the internal electrodes 23a to 23d can be avoided, so that delamination due to oxidative expansion of the internal electrodes made of Pd or the like can be avoided. The occurrence rate of structural defects such as cracks and cracks can be significantly reduced, and a highly reliable multilayer capacitor can be obtained.
【0025】尚、本実施形態における各設定値は一例で
ありこれに限定されることはない。例えば、内部電極2
3a〜23dの間隔t1 、幅D、厚さt2 を、実験にお
いてそれぞれ58μm、50μm、2μmに設定した場
合においても、ほぼ同様の効果が得られている。また、
前述した各値の設定値範囲は実験により得られたもので
ある。Each set value in this embodiment is an example, and the present invention is not limited to this. For example, the internal electrode 2
Even when the intervals t 1 , width D, and thickness t 2 of 3a to 23d are set to 58 μm, 50 μm, and 2 μm in the experiment, respectively, almost the same effect is obtained. Also,
The set value range of each value described above is obtained by an experiment.
【0026】さらに、本実施形態では2組の電極群24
a,24bを積層してコンデンサを形成したが、複数組
の電極群を積層したコンデンサを形成しても同様の効果
を得ることができるし、また、図7に示すように同一面
上に2つの電極群を平行して設けた積層コンデンサの場
合も、各電極群において前述の設定値範囲内の設定であ
れば同様の効果が得られる。Further, in this embodiment, two sets of electrode groups 24 are provided.
Although a capacitor is formed by laminating a and 24b, the same effect can be obtained by forming a capacitor in which a plurality of electrode groups are laminated, and as shown in FIG. Also in the case of a multilayer capacitor in which two electrode groups are provided in parallel, the same effect can be obtained as long as each electrode group is set within the set value range described above.
【0027】また、本実施例では2枚の内部電極によっ
て1つの内部電極群を構成したが、3枚以上の内部電極
を用いて1つの内部電極群を構成しても良い。Further, in the present embodiment, one internal electrode group is composed of two internal electrodes, but one internal electrode group may be composed of three or more internal electrodes.
【0028】[0028]
【発明の効果】以上説明したように本発明によれば、2
枚の内部電極からなる電極群が同等の厚さを有する電極
と同等の働きをし、高周波域における内部電極内におけ
る損失を小さくできると共に、電気抵抗を小さくできる
ので、高周波域におけるQ値を高めることができる。さ
らに、内部電極を必要最小限に薄く形成できるため、内
部電極の局部的な累積による内部歪みを回避できるの
で、Pd等からなる内部電極の酸化膨張による構造欠陥
(デラミネーション、クラック等)の発生率を大幅に低
減することができ、信頼性の高い積層コンデンサを得る
ことができる。As described above, according to the present invention, 2
An electrode group consisting of a single internal electrode functions similarly to an electrode having the same thickness, and it is possible to reduce loss in the internal electrode in the high frequency range and electrical resistance, thus increasing the Q value in the high frequency range. be able to. Furthermore, since the internal electrodes can be formed to the minimum necessary thickness, internal strain due to local accumulation of the internal electrodes can be avoided, so that structural defects (delamination, cracks, etc.) due to oxidative expansion of the internal electrodes made of Pd or the like occur. The rate can be significantly reduced, and a highly reliable multilayer capacitor can be obtained.
【図1】本発明の一実施形態における積層コンデンサを
示す外観図FIG. 1 is an external view showing a multilayer capacitor according to an embodiment of the present invention.
【図2】従来例の積層コンデンサを示す分解斜視図FIG. 2 is an exploded perspective view showing a conventional multilayer capacitor.
【図3】従来例の積層コンデンサを示す平断面図FIG. 3 is a cross-sectional plan view showing a conventional multilayer capacitor.
【図4】図3のA−A線矢視方向の断面図FIG. 4 is a sectional view taken along the line AA of FIG.
【図5】本発明の一実施形態における積層コンデンサの
要部分解斜視図FIG. 5 is an exploded perspective view of essential parts of the multilayer capacitor according to the embodiment of the present invention.
【図6】本発明の一実施形態における積層コンデンサの
側面断面図FIG. 6 is a side sectional view of the multilayer capacitor according to the embodiment of the present invention.
【図7】本発明の他の実施形態を示す要部分解斜視図FIG. 7 is an exploded perspective view of essential parts showing another embodiment of the present invention.
20…積層コンデンサ、21…素体、21A〜21E…
誘電体層、22a,22b…外部電極、23,23a〜
23d…内部電極、24a,24b…電極群。20 ... Multilayer capacitor, 21 ... Element body, 21A-21E ...
Dielectric layers, 22a, 22b ... External electrodes, 23, 23a ...
23d ... internal electrodes, 24a, 24b ... electrode group.
Claims (1)
けて平行に設けた所定幅D及び厚さt2 を有する少なく
とも2枚の内部電極からなる電極群と誘電体層とを交互
に積層してなる素体と、 該素体の両端部において前記電極群を交互に並列に接続
している一対の外部電極とを有し、 前記内部電極の幅Dと、前記電極群における2枚の内部
電極間の間隔t1 との比(D/t1 )が0.86以上
5.60以下の所定値となるように、且つ前記電極群に
おける2枚の内部電極間の間隔t1 と前記内部電極の厚
さt2 との比(t1 /t2 )が1.5以上29.0以下
の所定値となるように、前記内部電極の幅D及び厚さt
2 並びに前記電極群における2枚の内部電極間の間隔t
1 が設定されていることを特徴とする積層コンデンサ。1. An electrode group composed of at least two internal electrodes having a predetermined width D and a thickness t 2 and arranged in parallel with a dielectric layer interposed at a predetermined interval t 1 and the dielectric layer are alternated. And a pair of external electrodes in which the electrode groups are alternately connected in parallel at both ends of the element body, and the width D of the internal electrode and 2 in the electrode group. The ratio (D / t 1 ) to the interval t 1 between the two internal electrodes is a predetermined value of 0.86 or more and 5.60 or less, and the interval t 1 between the two internal electrodes in the electrode group is The width D and the thickness t of the internal electrode are set so that the ratio (t 1 / t 2 ) of the internal electrode to the thickness t 2 of the internal electrode becomes a predetermined value of 1.5 or more and 29.0 or less.
2 and the interval t between two internal electrodes in the electrode group
A multilayer capacitor characterized in that 1 is set.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28005695A JPH09129490A (en) | 1995-10-27 | 1995-10-27 | Laminated capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28005695A JPH09129490A (en) | 1995-10-27 | 1995-10-27 | Laminated capacitor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09129490A true JPH09129490A (en) | 1997-05-16 |
Family
ID=17619695
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28005695A Withdrawn JPH09129490A (en) | 1995-10-27 | 1995-10-27 | Laminated capacitor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09129490A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006041058A (en) * | 2004-07-23 | 2006-02-09 | Tdk Corp | Laminated chip varistor |
WO2007020757A1 (en) * | 2005-08-19 | 2007-02-22 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
-
1995
- 1995-10-27 JP JP28005695A patent/JPH09129490A/en not_active Withdrawn
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006041058A (en) * | 2004-07-23 | 2006-02-09 | Tdk Corp | Laminated chip varistor |
WO2007020757A1 (en) * | 2005-08-19 | 2007-02-22 | Murata Manufacturing Co., Ltd. | Multilayer ceramic capacitor |
JPWO2007020757A1 (en) * | 2005-08-19 | 2009-02-19 | 株式会社村田製作所 | Multilayer ceramic capacitor |
JP4525753B2 (en) * | 2005-08-19 | 2010-08-18 | 株式会社村田製作所 | Multilayer ceramic capacitor |
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A300 | Withdrawal of application because of no request for examination |
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