JPH09128324A - Device and method for controlling data transfer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an arbitration and to prevent the deterioration of processing efficiency by providing a converting means, receiving a main storage address being the address of a main storage device where data to be transferred are stored from an external device and converting it into a cache line boundary address based on the cache line size of a cache memory. SOLUTION: An address converting part 8 receives the address of a main memory 4 where data to be transferred is stored, which is transmitted from the external device 11, and converts the address into the cache line boundary address based on the cache line size of the cache memory 3. Moreover, an address converting part 8 calculates difference between the address from the external device 11 and the cach line boundary address, supplies a value corresponding to it to an address offset counter 7 as an address offset and permits the counter 7 to store it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer control device and a data transfer control method. In particular, the present invention relates to a data transfer control device and a data transfer control method suitable for use when transferring data from an information processing device having a cache memory to an external device.

[0002]

2. Description of the Related Art Recent computers (information processing devices) have a high-speed cache memory as a memory in addition to a main memory (main storage device). In order to speed up the process, the data is copied to the cache memory, and when the CPU (central processing unit) needs to access the memory, the cache memory is accessed instead of the main memory.

FIG. 5 shows the configuration of an example of such a conventional computer system. The ROM 1 stores system programs (including microprograms) and the like. The CPU 2 is configured to execute a predetermined process while accessing the cache memory 3 or the main memory 4 as necessary under the control of the system program stored in the ROM 1. The cache memory 3 is configured to read data that is frequently accessed by the CPU 2 from the main memory 4 and store the data. The main memory 4 stores data necessary for the operation of the CPU 2, programs to be executed by the CPU 2, and the like.

The DMA bus controller 5 receives a D signal from an external device 11 via an I / O (Input / Output) bus.
When there is a request from the MA, the bus use right (control right) is adjusted with the CPU 2, and when the bus use right is acquired (arbitration can be taken), data transfer by DMA, that is, the CPU 2 Data sent from the external device 11 without passing through the cache memory 3
Is written in or read out from the data stored in the cache memory 3 and transferred to the external device 11.

The above-mentioned ROM 1, CPU 2, cache memory 3, main memory 4, DMA bus controller 5, and I / 0 bus constitute a computer main body.

The external device 11 is, for example, a board or other device for processing images and sounds, and is connected to the DMA bus controller 5 via the I / O bus. Then, the external device 11 exchanges data with the computer main body as necessary,
It is designed to perform a predetermined process.

In addition to the data to be transferred, the following signals are exchanged between the DMA bus controller 5 and the external device 11.

That is, the external device 11 sends to the DMA bus controller 5 a DMA request signal for requesting data transfer by DMA. The DMA request signal includes a DMA read request signal for requesting that the data stored in the main memory 4 be read and transferred to the external device 11, and data output by the external device 11 to be transferred to the main memory 4. There is a DMA write request signal for requesting writing.

When the DMA bus controller 5 issues a DMA enable signal indicating that DMA is possible and a DMA read request to the external device 11 when arbitration is performed, the external device 11 is sent.
In addition, a data valid signal for notifying a section in which data should be received is transmitted.

In the computer configured as described above, for example, by operating an operation unit (not shown),
When an instruction is given to execute a predetermined application program, the CPU 2 expands the application program in the main memory 4 and executes it. At this time, when it is necessary to hold the data, the CPU 2 writes the data in the cache memory 3. Further, this data is written in the main memory 4 at the same time as it is written in the cache memory 3 or thereafter.

When the CPU 2 reads the data stored in the main memory 4, it first reads the cache memory 3.
To access. If the data is stored in the cache memory 3, the CPU 2 reads the data from the cache memory 3, and if the data is not stored in the cache memory 3, the CPU 2 accesses the main memory 4 to store the data. The data is read and the data is stored in the cache memory 3.

Therefore, the CPU 2 basically accesses the high speed cache memory 3 and
Since the main memory 4 is accessed if there is no data required for the data, the data can be exchanged at a higher speed than in the case where only the main memory 4 is provided.

Data exchange between the main body and the external device 11 will be described below. External device 11
Outputs a DMA write request signal to the DMA bus controller 5 when it is necessary to transfer data to the computer main body. The DMA bus controller 5 is a DMA
When the write request signal is received, the bus usage right is adjusted with the CPU 2, and when the usage right is acquired, D
The MA permission signal is output to the external device 11.

Upon receiving the DMA permission signal, the external device 11 sends the data to be transferred to the main body to the DMA bus controller 5. The DMA bus controller 5 is
Data from the external device 11 is transferred to and stored in the cache memory 3 without going through the CPU 2. In addition,
This data is written to the main memory 4 at the same time as it is written to the cache memory 3 or thereafter.

Next, the external device 11 sends a DMA read request signal when there is data to be read from the main body.
Output to the DMA bus controller 5. Upon receiving the DMA read request signal, the DMA bus controller 5 acquires the right to use the bus and outputs the DMA permission signal to the external device 11 in the same manner as when the DMA write request signal is received. Upon receiving the DMA permission signal, the external device 11 prepares to receive data and waits for the data valid signal to be transmitted.

On the other hand, the DMA bus controller 5 is a DM
DMA is output from the external device 11 after the A permission signal is output.
The requested data is read from the cache memory 3. When the data is not stored in the cache memory 3, the DMA bus controller 5 transfers the data from the main memory 4 to the cache memory 3 and stores it.

Upon reading the data from the cache memory 3, the DMA bus controller 5 outputs the data to the external device 11 together with the data valid signal. Then, when the transfer (output) of data is completed, the DMA bus controller 5 also stops outputting the data valid signal.
The external device 11 receives the data output from the DMA bus controller 5 while the data valid signal is output from the DMA bus controller 5.

As described above, even when data is exchanged between the main unit and the external device 11,
Basically, since the high speed cache memory 3 is accessed, data can be exchanged at high speed.

In the computer itself, the data to be transmitted to the external device 11 is read from the cache memory 3 as described above, but the external device 1
The cache memory 3 cannot be seen from 1 and therefore, in the external device 11, the data to be read is specified by the address of the main memory 4 in which the data is stored. Further, in the external device 11, the size (size) of the data to be read from the main body is specified by using that address as the start address.
These addresses and sizes are output together with the DMA read request signal, for example. This also applies when writing data from the external device 11 to the main body.

[0020]

By the way, the cache memory 3 is usually divided into units called cache lines, and it is necessary to read and write data with this unit as the maximum amount of data. . Here, the capacity (size) of this cache line is
It is called the cache line size as appropriate.

Since the access to the cache line is generally performed so that the addresses can be matched, the address to start the access and the amount of data that can be accessed at one time from the address are limited. It

This limitation varies depending on the model and manufacturer, but there are the following, for example. That is, for example,
From the cache line, X (X is usually 1, 4, 8,
(16, 32, ...) When reading continuous data of a data amount only, the lower lo of the address in the main memory 4 of the data to start reading.
It may be required that the g ₂ X bits match zero.

In this case, for example, assume that the cache line size is 16 words (where 1 word is, for example, 4 bytes, and each address stores data, for example, in 1-byte units). As shown in FIG. 6 (A), when 16 words of data at addresses 0x00 to 0x3f in the main memory 4 are stored in the cache line (0x indicates that the value following it is 1).
A hexadecimal number), a range of data that can be read from the cache line with one access, and the start address thereof are as shown in FIGS.

That is, when the data is read using the address 0x00 as the start address, data of 16, 8, 4, or 1 word can be read as shown in FIGS. Also, the address 0x2
When data is read with 0 as the start address, data of 8, 4 or 1 word can be read as shown in each of FIGS. Furthermore, when data is read using the address 0x10 or 0x30 as the start address, data of 4 or 1 word can be read as shown in FIG. Then, when data is read using a head address other than the above-mentioned addresses, one word of data can be read as shown in FIG.

Therefore, the external device 11 is, for example,
As shown in FIG. 6F, addresses 0x08 to 0x3
When attempting to read the 12-word data C to N stored in 7 from the main body, as shown in FIG. 7G, at least a DMA of 1-word data is sequentially requested from addresses 0x08 and 0x0a, respectively. , And then D of 4-word data from addresses 0x10 and 0x20
MAs are sequentially requested, and addresses 0x30 and 0x3 are further requested.
4 It is necessary to sequentially request the DMA of 1-word data from each of them.

That is, in order to read 12-word data continuously stored at addresses 0x08 to 0x37,
As shown in FIG. 7, the external device 11 needs to request the DMA by dividing it into at least 6 times.

Here, in FIG. 8, addresses 0x08 to 0
The timing chart at the time of reading the data of 12 words memorize | stored continuously at x37 is shown. In addition, in the same figure (similarly also in FIG. 4 which will be described later), each signal is shown as active low.

First, in the external device 11, the DMA read request signal is changed from the H level to the L level in order to request the reading of 1-word data from the address 0x08 (FIG. 8 (A)). Arbitration (adjustment of the right to use the bus with the CPU 2) is performed in the controller 5. When the arbitration is completed, the DMA bus controller 5
The MA permission signal is set to L level for a predetermined period (see FIG. 8).
(B)), when this is received by the external device 11,
The DMA read request signal is changed from L level to H level (FIG. 8A).

Further, the DMA bus controller 5 is
After setting the MA permission signal to the L level, the cache memory 3
From the address 0x08, 1 word of data, that is,
The data C is read, the data valid signal is set to the L level, and the data C is transferred to the external device 11. Then, when the DMA bus controller 5 finishes the transfer of the data C to the external device 11, it sets the data valid signal to the H level.

In the same manner, address 0x0a to 1-word data D, address 0x10 to 4-word data E to H, address 0x20 to 4-word data I to L, address 0x30 to 1-word data M, address One word of data N from 0x34 is transferred to the external device 11.

As described above, when there is a request for DMA, arbitration occurs each time. Therefore, when DMA is requested frequently, arbitration also occurs frequently.
As a result, there has been a problem that the processing efficiency of the computer deteriorates.

The present invention has been made in view of such a situation, and makes it possible to prevent deterioration of processing efficiency.

[0033]

A data transfer control device according to claim 1 receives a main memory address, which is an address of a main memory device in which data to be transferred is stored, from an external device, and the main memory is received. Conversion means for converting the address into a cache line boundary address based on the cache line size of the cache memory; and request means for requesting the information processing device to transfer the data of the cache line size from the cache line boundary address. In response to the request of the requesting means, the storing means for storing the data of the cache line size transferred from the information processing device, and the storing means for the difference between the main memory address and the cache line boundary address Of the stored cache line size data, is it the main memory address? The data, characterized in that it comprises a notifying means for informing an external device.

A data transfer control method according to claim 3 is
From the external device, receives a main memory address that is the address of the main memory device in which the data to be transferred is stored, and converts the main memory address to a cache line boundary address based on the cache line size of the cache memory, The information processing device is requested to transfer the data of the cache line size from the cache line boundary address, and the data of the cache line size transferred from the information processing device is stored in response to the request. The data from the main memory address among the stored data of the cache line size is notified to the external device in correspondence with the difference between the memory address and the cache line boundary address.

A data transfer control device according to a fourth aspect is
A conversion that receives a main memory address, which is the address of the main memory device in which the data to be transferred is stored, from the external device, and converts the main memory address into a cache line boundary address based on the cache line size of the cache memory And a requesting means for requesting the information processing apparatus to transfer data of a cache line size from the cache line boundary address, and a cache line size transferred from the information processing apparatus in response to the request of the requesting means. Data corresponding to the cache line size stored in the storage means corresponding to the difference between the main storage address and the cache line boundary address. An output means for outputting to the device, That.

In the data transfer control device according to the first aspect, the converting means receives from the external device a main memory address which is an address of the main memory device in which the data to be transferred is stored, and the main memory address. Is converted into a cache line boundary address based on the cache line size of the cache memory. The requesting means requests the information processing apparatus to transfer the data of the cache line size from the cache line boundary address, and the storing means responds to the request of the requesting means and the cache transferred from the information processing apparatus. The line size data is stored. The notifying means notifies the external device of the data from the main memory address among the data of the cache line size stored in the memory means, corresponding to the difference between the main memory address and the cache line boundary address. Has been done.

In the data transfer control method according to the third aspect, a main memory address, which is an address of a main memory device in which data to be transferred is stored, is received from an external device, and the main memory address is used as a cache memory. Based on the cache line size of, the cache line boundary address is converted, the information processing device is requested to transfer the data of the cache line size from the cache line boundary address, and in response to the request,
Stores data of the cache line size transferred from the information processing device, and stores the data of the cache line size from the main memory address corresponding to the difference between the main memory address and the cache line boundary address. The above data is notified to an external device.

According to another aspect of the data transfer control device of the present invention, the converting means receives from the external device a main memory address which is an address of a main memory device in which data to be transferred is stored, and the main memory address is received. Is converted into a cache line boundary address based on the cache line size of the cache memory. The requesting means requests the information processing apparatus to transfer the data of the cache line size from the cache line boundary address, and the storing means responds to the request of the requesting means and the cache transferred from the information processing apparatus. The line size data is stored. The output means outputs the data from the main storage address, out of the data of the cache line size stored in the storage means, to the external device in correspondence with the difference between the main storage address and the cache line boundary address. Has been done.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below, but before that, in order to clarify the correspondence between each means of the invention described in the claims and the following embodiments. The features of the present invention are described as follows by adding a corresponding embodiment (however, an example) in parentheses after each means.

That is, the data transfer control device according to claim 1 has at least a main storage device (for example, the main memory 4 shown in FIG. 1) and a cache memory (for example, cache memory 3 shown in FIG. 1). In an information processing apparatus (for example, the computer main body shown in FIG. 1), an external device (for example, external device 1 shown in FIG. 1)
(1 etc.) is a data transfer control device that controls the transfer of data when the data to be transferred to the main memory device is stored from a cache memory. Translating means for receiving a main memory address which is an address and translating the main memory address into a cache line boundary address based on the cache line size of the cache memory (for example, the address translating unit 8 shown in FIG. 1), Requesting means (for example, the address converting unit 8 shown in FIG. 1) for requesting the information processing device to transfer the data of the cache line size from the cache line boundary address, and information corresponding to the request of the requesting means. Storage means for storing the data of the cache line size transferred from the processing device ( In example, FIFO shown in Figure 1 (First
(In First Out) the memory 10 or the like) and the data from the main storage address among the data of the cache line size stored in the storage means corresponding to the difference between the main storage address and the cache line boundary address. Informing means for informing the device (for example, the FIF shown in FIG.
O control unit 9 and the like).

The data transfer control device according to claim 2 is
A DMA controller that transfers data from a cache memory by DMA (Direct Memory Access) when the information processing device requests data transfer by the requesting means (for example, the DMA bus controller 5 shown in FIG. 1). Is further included.

The data transfer control device according to claim 4 is
In an information processing device (for example, a computer main body shown in FIG. 1) having at least a main storage device (for example, main memory 4 shown in FIG. 1) and a cache memory (for example, cache memory 3 shown in FIG. 1), A data transfer control device that controls the transfer of data when the data to be transferred to a device (for example, the external device 11 shown in FIG. 1) is read from the cache memory. To receive a main memory address which is an address of a main memory device in which data to be stored is stored, and to convert the main memory address into a cache line boundary address based on the cache line size of the cache memory (for example, FIG. 1). Address translation unit 8) and the information processing device. From the boundary boundary address, a requesting unit (for example, the address converting unit 8 shown in FIG. 1) for requesting the transfer of the data of the cache line size, and the information processing device in response to the request of the requesting unit are transferred. Storage means for storing data for the incoming cache line size (for example, the FIFO memory 1 shown in FIG.
0 or the like) and the output from the main storage address of the data of the cache line size stored in the storage means corresponding to the difference between the main storage address and the cache line boundary address to the external device. Means (for example, the FIFO control unit 9) are provided.

Of course, this description does not mean that each means is limited to the above.

FIG. 1 shows the configuration of an embodiment of a computer system to which the present invention is applied. In the figure, portions corresponding to those in FIG. 5 are denoted by the same reference numerals, and a description thereof will be omitted as appropriate below.
That is, in this computer system, the data transfer control unit 6 is newly provided, and the computer main body and the external device 11 are connected via the data transfer control unit 6 and the computer system of FIG. It is similarly configured.

The data transfer control unit 6 includes an address offset counter 7, an address conversion unit 8, a FIFO control unit 9,
And a FIFO memory 10. The address offset counter 7 is configured to store an address offset, which will be described later, supplied from the address conversion unit 8. Then, the address offset counter 7
Under the control of the FIFO control unit 9, the storage value is decremented by one.

The address conversion unit 8 receives the address (main memory address) of the main memory 4 in which the data to be transferred is stored, which is transmitted from the external device 11, and uses that address as the cache line of the cache memory 3. Based on the size, it is adapted to be converted into a cache line boundary address (cache line boundary addrress) as described later. The cache line size is notified from the computer body to the address conversion unit 8.

Further, the address conversion unit 8 calculates the difference between the address from the external device 11 and the cache line boundary address, and supplies the value corresponding to this difference to the address offset counter 7 for storage therein. It is done like this. The address conversion unit 8 is also configured to request the DMA bus controller 5 (computer main body) to transfer the data of the cache line size by DMA from the cache line boundary address.

The FIFO control unit 9 includes a FIFO memory 10
In addition to controlling, the data valid signal transmitted from the DMA bus controller 5 is received.
Further, the FIFO control unit 9 causes the FIFO memory 10 to
After the data transmitted from the DMA bus controller 5 is stored, the stored value of the address offset counter 7 is decremented by 1 each time one word of data is read from the data. And FI
The FO control unit 9 refers to the stored value of the address offset counter 7 via the address conversion unit 8 and notifies the external device 11 of the data to be received by the external device 11 based on the value. Has been done.

The FIFO memory 10 includes a FIFO control unit 9
Under the control of 1, the data of the cache line size transferred from the DMA bus controller 5 is temporarily stored and output to the external device 11 by a DMA request from the address conversion unit 8.

Next, the operation will be described. First,
Data transfer by DMA from the external device 11 to the computer body is performed in the same manner as in FIG.
That is, in this case, the output signal from the external device 11 is
The data transfer control unit 6 is bypassed and transmitted to the DMA bus controller 5.
Similarly, the output signal from is also transmitted to the external device 11 by bypassing the data transfer control unit 6.

On the other hand, when the external device 11 reads the data from the computer main body by DMA, the processing according to the flowchart of FIG. 2 is performed. That is, in this case, the external device 11 outputs the DMA read request, the start address of the requested data in the main memory 4 (hereinafter appropriately referred to as a read request address), and the data amount (size). This DMA read request is supplied to the data transfer control unit 6 together with the read request address and the data amount, and the address conversion unit 8
Is received at The address conversion unit 8 receives the read request address and the data amount together with the DMA read request, and in step S1, it is determined whether or not the read request address matches the cache line boundary address.

Now, the cache line boundary address will be described. The cache memory 3 normally stores data for each range from the address 0x0000 of the main memory 4 to the cache line size. That is, when the cache line size is, for example, 16 words as described above, the cache line has addresses 0x0000 to 0x0 of the main memory 4.
16-word data stored in 03f, 0x0040
Through 16x data stored in 0x007f, 0
Data is stored in units of 16-word data stored in x0080 to 0x00cf. In such a case, the address of the data stored at the head of the cache line in the main memory 4 is the cache line boundary address. Therefore, in this case, the cache line boundary address is 0x0.
000, 0x0040, 0x0080, 0x00c0,
...

If it is determined in step S1 that the read request address does not match the cache line boundary address, the process proceeds to step S2, and the address conversion unit 8 reads the read request address having a smaller value. It is converted into a cache line boundary address having the smallest difference from the address (hereinafter, appropriately referred to as a conversion boundary address). Further, in step S3, the difference between the read request address and the conversion boundary address ((read request address)-(conversion boundary address)) is calculated, and the difference value is the number of bytes forming one word (here, , 4 bytes as described above). Then, the quotient obtained as a result of the division is used as the address offset.
Therefore, the address offset can be said to represent the difference between the read request address and the conversion boundary address in terms of the number of words. That is, the data read after the word number of data corresponding to the address offset is read from the conversion boundary address is the data from the read request address.

Here, when the cache line size is 16 words as described above, the address offset is any value from 0 to 15.

The address translation unit 8 obtains the translation boundary address and the address offset as described above, sets the address offset in the address offset counter 7, and proceeds to step S3.

On the other hand, when it is determined in step S1 that the read request address matches the cache line boundary address, the address conversion unit 8 sets the read request address as the conversion boundary address and 0 as the address offset. The address offset counter 7 is set, and the process proceeds to step S3. In step S3, data for the cache line size having the conversion boundary address as the start address (data for the cache line size from the conversion boundary address)
The DMA read request is output from the address conversion unit 8 to the DMA bus controller 5.

Thereafter, the data transfer control unit 6 waits for the arbitration to be taken by the DMA bus controller 5 (waits for the DMA permission from the DMA bus controller 5) in step S4, and then proceeds to step S5. move on.

When the DMA bus controller 5 receives the DMA read request from the address conversion unit 8, the arbitration is performed as described above and the data is read from the cache memory 3. However, in the computer system of FIG. 1, even if the external device 11 makes a DMA read request of any data amount (extremely, for example, when a DMA read request of 1-word data is made, (However, within the range of the cache line size), data of the cache line size is read from the cache memory 3 from the conversion boundary address.

When the DMA bus controller 5 reads the data of the cache line size from the conversion boundary address from the cache memory 3, it outputs the data along with the data valid signal via the I / O bus as described above.

In step S5, as described above, D
Data output from the MA bus controller 5 for the cache line size from the conversion boundary address is
It is received and stored in the FIFO memory 10.

Then, in step S6, the FIFO control unit 9 refers to the address offset counter 7 via the address conversion unit 8 and determines whether the address offset is 0 or less. If it is determined in step S6 that the address offset is not equal to or less than 0, the process proceeds to step S7, in which the FIFO memory 10 is controlled by the FIFO control unit 9, whereby the FI
One word of data is read from the FO memory 10 and output to the external device 11. In this case,
The data valid signal supplied from the FIFO control unit 9 to the external device 11 is not made active (ON) (in this embodiment, because it is active low as described above, it is not at the L level). Therefore, step S7 FIFO
The 1-word data read from the memory 10 is not received by the external device 11.

In step S7, one word of data is read from the FIFO memory 10 and then FI
The FO control unit 9 decrements the address offset stored in the address offset counter 7 by 1 via the address conversion unit 8 and returns to step S6.

On the other hand, if it is determined in step S7 that the address offset is 0 or less, step S7.
8, the data valid signal supplied from the FIFO control unit 9 to the external device 11 is activated (ON).

Then, in step S9, one word of data is read from the FIFO memory 10, and in step S10, the data request signal is active (ON).
It is determined whether (valid) (L level). When it is determined in step S10 that the data request signal is active, the process returns to step S9, the next 1-word data is read from the FIFO memory 10,
Hereinafter, the same processing is repeated.

At the same time as the DMA read request is made, the external device 11 activates the data request signal (signal indicating that data is being requested) supplied to the FIFO control section 9 at the same time. It is designed to do. Then, the external device 11 receives the data read from the FIFO memory 10 only when both the data request signal and the data valid signal from the FIFO control unit 9 are active. Then, when the external device 11 receives the data of the data amount requested by itself, the external device 11 turns off the data valid signal (H level).

Therefore, in step S9, the FIFO memory 1
For data read from 0, the data request signal is OFF
Until it is set, it is received by the external device 11.

After that, when the external device 11 receives the data of the data amount requested by itself, the data valid signal is turned off. Therefore, in this case, step S10
From step S11, the FIFO control unit 9 turns off the data valid signal, and the process goes to step S12. In step S12, all the data remaining in the FIFO memory 10 is read out under the control of the FIFO control unit 9 (in this case, since the data request signal and the data valid signal are both OFF, the data is read out in step S12). Data is not received by the external device 11), the process ends.

According to the above processing, for example, the above-mentioned FIG.
If there is a DMA read request as shown in (F),
That is, as shown in FIG.
When the A read request is made with a read request address of 0x08 and a data amount of 12 words (12 stored in addresses 0x08 to 0x37)
When there is a DMA read request for word data C to N), the read request address 0x08 is the cache line boundary address 0x0000, 0x004.
0, 0x0080, ... Does not match any of 0, 0x0080, ..., Therefore, in step S2, the cache line boundary address 0x00 having a value smaller than the read request address and having the smallest difference from the read request address.
Is converted to 00. Then, in step S3, the conversion boundary address 0x0000 corresponds to the cache line (16
(Word) DMA read request is made.

Therefore, in this case, the FIFO memory 10 stores the 16-word data of A to P stored in the addresses 0x00 to 0x3f in step S5 as shown in FIG. When the data is stored in the FIFO memory 10 in this way, the two-word data A and B first read from the FIFO memory 10 are not the data requested by the external device 11 (such data will be referred to as non-data Request data).

On the other hand, the difference between the read request address and the conversion boundary address is 0x08 (= 0x08-0x0
0), the address offset is 0x08,
It is divided by 4 bytes, which is the number of bytes forming one word, to be 2. Therefore, the address offset matches the number of words of unrequested data. This address offset is 1 from the FIFO memory 10 in step S7.
Since the word data is decremented by 1 every time it is read, the data whose reading is started from the FIFO memory 10 after the address offset becomes 0 is stored in the read request address which the external device 11 should receive. It will be the data.

Therefore, the external device 11 may be made to receive the data read from the FIFO memory 10 after the address offset becomes zero. Therefore, when the address offset becomes 0, step S8
In, the data valid signal is activated so that the external device 11 receives the data read from the FIFO memory 10 thereafter.

In this case, since the external device 11 requests the data C to N of 12 words stored in the addresses 0x08 to 0x37, the data is stored in the addresses 0x38 and 0x3c shown in FIG. 3, respectively. The one-word data O and P are also unrequested data, like the above-mentioned data A and B. Therefore, it is necessary to prevent the external device 11 from receiving the data O and P as well. This is done as follows.

That is, since the external device 11 recognizes that the amount of data requested by itself is 12 words, when it receives the requested amount of data, it turns off the data request signal (H level), As a result, the data O and P are not received.

As a result, the external device 11 receives only the 12-word data C to N stored in the addresses 0x08 to 0x37 by one DMA request.

Next, referring to FIG. 4, the external device 11
However, the exchange of signals when a DMA read request as described with reference to FIG. 3 is made will be described. When the external device 11 requests data transfer by DMA,
The DMA read request signal supplied to the address conversion unit 8 is changed from H level to L level (FIG. 4 (A)). Further, the external device 11 also changes the data request signal supplied to the FIFO control unit 9 from H level to L level (FIG. 4 (F)).

The DMA read request signal is supplied from the address conversion unit 8 to the DMA bus controller 5, and the DMA bus controller 5 arbitrates the bus. And when arbitration is done, D
The MA bus controller 5 changes the DMA permission signal supplied to the external device 11 via the address conversion unit 8 from H level to L level for a predetermined period (FIG. 4).
(B)). Upon receiving the L level DMA permission signal, the external device 11 recognizes that arbitration has been taken, and changes the DMA read request signal from the L level to the H level (FIG. 4 (A)).

Thereafter, the data A to P corresponding to the cache line size stored at the addresses 0x00 to 0x3f as described above are transferred from the DMA bus controller 5 (FIG. 4C) and stored in the FIFO memory 10. It Then, the data A to P are sequentially read from the FIFO memory 10 (FIG. 4D) and supplied to the external device 11.

When data reading from the FIFO memory 10 is started, the address offset is decremented by 1 each time data reading from the FIFO memory 10 is performed one word (FIG. 4 (G)). When the address offset becomes 0, the data valid signal supplied from the FIFO control unit 9 to the external device 11 is changed from the H level to the L level (FIG. 4 (E)), whereby the data valid signal (FIG. 4 (E)) and the data request signal are both L
Since it becomes the level, in the external device 11, the FIF
Reception of data read from the O memory 10 is started.

When the external device 11 receives the requested data amount of 12 words, it changes the data request signal from the L level to the H level (FIG. 4).
(F)). As a result, the reception of the data read from the FIFO memory 10 at the external device 11 is stopped. Further, when the data request signal is changed from L level to H level, the FIFO control unit 9 changes the data valid signal supplied to the external device 11 from L level to H level (FIG. 4 (E)).

As described above, regardless of the DMA read request address and the data amount requested by the external device 11, the cache line boundary address is
Since the DMA of the data for the cache line size is requested, the DMA request can be made only once. Therefore, it is possible to prevent frequent occurrence of arbitration, so that it is possible to reduce the load on the computer main body and prevent deterioration of its processing efficiency.

Further, the external device 11 considers the matching of the addresses corresponding to the cache line size, and
Simplification of programming for the external device 11 (Simplification) since it is not necessary to request A in multiple times.
Can be achieved.

Further, in this embodiment, the FIFO memory 1
Since the data transferred from the DMA bus controller 5 is stored in 0, the data reception speed of the external device 11 can be flexibly dealt with.

In this embodiment, the data reading is performed by the DMA, but the present invention uses the DMA.
The present invention can also be applied to the reading of data that is not performed by.

In the present embodiment, the external device 11 is notified by the data valid signal whether or not the data read from the FIFO memory 10 is the data to be received. It is also possible to cause the FIFO control unit 9 to refer to the address offset and cause the external device 11 to output the data read from the FIFO memory 10 when the value becomes 0 or less.

Further, in the present embodiment, the case where the data stored at the consecutive addresses is read at one time has been described. However, in addition to this, for example, the data stored at the discontinuous addresses is transferred at one time. It is also possible to do so. That is, if the data to be read is stored within a range of the cache line size from a certain cache line boundary address, whether the address of the data is continuous or discontinuous is 1
It can be read in times.

According to the present embodiment, even if a DMA read request for a small amount of data such as 1 word or 2 words is issued from the external device 11, the DMA for the data of the cache line size is requested. To be done.
Therefore, when reading a small amount of data from each of the plurality of cache lines, the data of the cache line size is read by the number of the cache lines, which rather deteriorates the processing efficiency. However, in a normal application, reading a small amount of data from each of a plurality of cache lines is very rare, so such a problem hardly occurs in practice.

[0087]

According to the data transfer control device of the first aspect and the data transfer control method of the third aspect, the main address which is the address of the main storage device in which the data to be transferred is stored from the external device. The storage address is received, and the main storage address is converted into a cache line boundary address based on the cache line size of the cache memory. Then, the information processing apparatus is requested to transfer the data of the cache line size from the cache line boundary address, and the data of the cache line size transferred from the information processing apparatus is stored in response to the request. It Then, the data from the main memory address of the stored data of the cache line size is notified to the external device in correspondence with the difference between the main memory address and the cache line boundary address.

According to another aspect of the data transfer control device of the present invention, the cache line size of data stored as described above is stored in correspondence with the difference between the main memory address and the cache line boundary address. Of these, the data from the main memory address is output to the external device.

Therefore, the data required by the external device can be transferred a small number of times.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a computer system to which the present invention is applied.

FIG. 2 is a flowchart for explaining the operation of the data transfer control unit 6 of FIG.

FIG. 3 is a diagram for explaining an operation when data is transferred to an external device 11 in the computer system of FIG.

FIG. 4 is a timing chart for explaining the operation of the computer system of FIG.

FIG. 5 is a block diagram showing a configuration of an example of a conventional computer system.

FIG. 6 is a diagram for explaining restrictions on access to a cache line.

FIG. 7 is a diagram for explaining an operation when data is transferred to the external device 11 in the computer system of FIG.

8 is a timing chart for explaining the operation of the computer system of FIG.

[Explanation of symbols]

 1 ROM 2 CPU 3 cache memory 4 main memory 5 DMA bus controller 6 data transfer control unit 7 address offset counter 8 address conversion unit 9 FIFO control unit 10 FIFO memory 11 external device

Claims (4)

[Claims] 1. An information processing apparatus having at least a main storage device and a cache memory, comprising: a data transfer control device that controls the transfer of data when the data to be transferred to an external device is read from the cache memory. Receiving a main memory address, which is an address of the main memory device in which data to be transferred is stored, from the external device, and based on the cache line size of the cache memory, the main memory address Conversion means for converting to a boundary address; request means for requesting the information processing device to transfer data of the cache line size from the cache line boundary address; and, in response to a request from the request means, The cap transferred from the information processing device A storage unit for storing data of a shrine size; and a main memory of the cache line size data stored in the storage unit corresponding to a difference between the main storage address and a cache line boundary address. A data transfer control device comprising: a notification unit that notifies the external device of the data from an address. 2. The information processing apparatus, when a request for transfer of the data is made by the requesting means, DMA (Di
The data transfer control device according to claim 1, further comprising a DMA controller that transfers the data from the cache memory by rect memory access. 3. A data transfer control method for controlling the transfer of data when the data to be transferred to an external device is read from the cache memory in an information processing device having at least a main storage device and a cache memory. Receiving a main memory address, which is an address of the main memory device in which data to be transferred is stored, from the external device, and based on the cache line size of the cache memory, the main memory address Converting to a boundary address, requesting the information processing device to transfer the data of the cache line size from the cache line boundary address, and responding to the request, the data is transferred from the information processing device. Stores data for the cache line size The data from the main memory address among the stored data of the cache line size is notified to the external device in correspondence with the difference between the main memory address and the cache line boundary address. And data transfer control method. 4. An information processing apparatus having at least a main storage device and a cache memory, wherein the data transfer control device controls the transfer of data when the data to be transferred to an external device is read from the cache memory. Receiving a main memory address, which is an address of the main memory device in which data to be transferred is stored, from the external device, and based on the cache line size of the cache memory, the main memory address Conversion means for converting to a boundary address; request means for requesting the information processing device to transfer data of the cache line size from the cache line boundary address; and, in response to a request from the request means, The cap transferred from the information processing device A storage unit for storing data of a shrine size; and a main memory of the cache line size data stored in the storage unit corresponding to a difference between the main storage address and a cache line boundary address. An output unit for outputting the data from an address to the external device, the data transfer control device.