JPH09121234A - Data reception processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flexibly respond to plural protocols and to improve the processing efficiency. SOLUTION: An input buffer 11 where transmitted data D is held is provided, and the data volume of this data D is monitored by a designated volume data taking-out part 12, and data is collected to a designated volume and is supplied to a data type/frame constitution discrimination part 13. It is discriminated whether supplied data D meets a prescribed data type A or not, and further, it is discriminated whether the frame constitution is concluded or not if it is the data type A. Data A1 which meets the data type A and concludes the frame constitution is supplied to a frame taking-out part 14, and data A2 as contents of the frame is taken out. Data A1 ' which meets the data type A but doesn't conclude the frame constitution is returned to the buffer 11 and is held there. Data C which doesn't meet the data type A is supplied to a data abandonment part 15 and is abandoned.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reception processing device which is applied to a composite terminal device or the like having an image and voice processing function and which easily supports a plurality of data link protocols.

[0002]

2. Description of the Related Art Conventionally, BSC (Binary Synchronous)
Communication), HDLC (High-level Data Link C)
In a data reception processing device compatible with a data link control protocol such as ontrol), the hardware (reception circuit) performs a process of extracting data in frame units from the data received via the transmission path, and the frame extracted by this The process of analyzing the contents of is performed by software. Taking HDLC as an example, in the conventional method, the following processes are simultaneously executed while receiving data in the receiving circuit. That is, the HDL from the data received via the transmission line
If C flag is detected, discard it and continue HDLC
Start capturing data with a pattern other than flags as the start of a frame. While the frame is being received, the CRC error correction operation is performed while appropriately deleting the "0" for maintaining the transparency, which is inserted between consecutive "1" s. The data up to immediately before is used as a frame. Then, the extracted frame data is stored in the reception buffer (FIFO). The frame data stored in the reception buffer is passed to the processing of software that analyzes the contents of the frame. At this time, data is transferred in N (N is FI
FO depth) in bytes.

[0003]

In the above-mentioned conventional data reception control device, since the receivable data link control protocol depends on the hardware of the receiving side, it is possible to flexibly deal with a plurality of protocols and protocol changes. There is a problem that you cannot do it. The data of the extracted frame is held in the buffer in the receiving circuit, and is passed from the buffer to the subsequent software in units of N bytes determined by the depth of the FIFO. One frame must be divided into several pieces and passed. To avoid this,
Although it is sufficient to increase the value of N, since the FIFO is usually configured as a shift register inside the communication control IC, it cannot be increased so much in view of the circuit scale of the LSI.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a data reception control device capable of flexibly coping with a plurality of protocols and improving processing efficiency. To aim.

[0005]

[Means for Solving the Problems]

A first data reception processing device of the present invention is
A receiving circuit that receives the transmitted data without data manipulation, an input buffer that holds the data received by this receiving circuit, and the data held in this input buffer to a preset specified amount. Along with collectively extracting, it is determined whether the specified amount of data is data of a predetermined predetermined type and includes a completed frame configuration, and the specified amount of data is the predetermined type of data and a completed frame. If the configuration is included, take out the contents of the frame obtained by the above model from the specified amount,
When the specified amount of data is the predetermined type of data and forms part of a frame, the specified amount of data is returned to the input buffer, and when the specified amount of data is not the predetermined type of data Data reception control processing means for discarding this is provided.

A second data reception processing device according to the present invention is
A receiver circuit that physically connects the transmitted data to receive the data, an external memory that temporarily holds the data received by the receiver circuit, and a data receiver that supports multiple data link protocols The control processing means selects one protocol to be received in advance, collects the data held in the external memory into a preset designated amount, and extracts the designated amount of data from the selected protocol. It is determined whether the data complies with the above, and includes a completed frame structure, and if the specified amount of data is data according to the selected protocol and includes a completed frame structure, it is obtained from the specified amount by the protocol. The contents of the frame are extracted, and the specified amount of data is the data according to the selected protocol and the frame And a data reception control processing means for returning the specified amount of data to the external memory when the above-mentioned specified amount of data is not the data of the selected protocol. It is characterized by that.

According to the first data reception processing device of the present invention, the transmitted data is received by the reception circuit, stored in the input buffer as it is, and then collected into a designated amount to control data reception in the subsequent stage. It is sent to processing means (software), where the type of data is determined and the contents of the frame are extracted. The receiving circuit does not depend on the receiving circuit because the receiving circuit only makes a physical connection and does not perform data manipulation as well as data type determination. The type of received data depends on the data reception control processing means, but since the data reception control means can be configured by software, it is possible to deal flexibly.

According to the second data reception processing device of the present invention, the data reception control means can support a plurality of data link protocols, and one of the protocols to be received is selected. Since the receiving circuit only physically connects data, it does not depend on the protocol selected by the data reception control means. If data other than the receivable protocol arrives,
The data is discarded by the data reception control means.

Further, since the external memory for holding the data received by the receiving circuit only holds the data sequentially sent from the receiving circuit as it is, for example, a RAM.
(Random Access Memory) can be used, and the required capacity can be easily secured. Therefore, the designated amount read from the external memory can be set to an appropriate value, and a plurality of frames can be passed by one interrupt.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a data reception processing device according to an embodiment of the present invention. This device is applied to a modem or the like, and has a receiving circuit 1, a RAM 2, a DMA control unit 3, a CPU 4 and an R.
The OM 5 is connected via the system bus 6.

The receiving circuit 1 receives data arriving via a communication line in accordance with a physical connection protocol, and is compatible with a plurality of data link protocols. The RAM 2 is an external memory that constitutes an input buffer that temporarily holds the data received by the receiving circuit 1. The DMA control unit 3 executes DMA control for directly transferring the data received by the receiving circuit 1 to the RAM 2 via the system bus 6. CPU4 is RA
The data reception control processing means for collectively reading the data stored in the M2 into a specified amount according to the program stored in the ROM5, determining the type of the extracted data, and extracting the frame contents from the data is constructed. is there.

FIG. 2 is a functional block diagram of the device.
The data D supplied from the receiving circuit 1 is stored in the RAM 2.
The input buffer 11 is held as it is. Specified amount day
The data extraction unit 12 stores the data held in the input buffer 11.
Monitor the data amount of D and collect the data D to the specified amount.
Then, it is supplied to the data type / frame configuration determination unit 13.
The specified amount of data D supplied is the predetermined data type here.
Whether expression A is satisfied and whether data type expression A is satisfied
, It is determined whether the frame configuration is completed. De
Data frame type A is satisfied and the frame structure is completed
Data A 1 is supplied to the frame take-out section 14,
Data A of the contents of the frame_Two Is taken out. Day
If the type A is satisfied and the frame structure is complete
No data A₁ ′ Is returned to buffer 11 and stored here.
Be held. In addition, data C that does not satisfy data type A
Is supplied to the data discarding unit 15 and is discarded there.

Next, the format of data received by this device will be described. Here, description will be made taking HDLC as the data type A and BSC as the data type B as an example. FIG. 3 is a diagram for explaining a frame format in HDLC and BSC. HDLC is
As shown in (a) of the figure, a start flag 21 indicating the start of a frame, an address field 22 indicating the address of the partner node, a control field 23 including HDLC control information, and an information field that is a data body of an arbitrary length. 24
And the error detection field FCS (Fr
ame Check Sequence) 25 and an end flag 26 indicating the end of the frame. For example, the data represented by “03 03 FF FF” (hexadecimal notation) in the HDLC frame is as shown in FIG. 4 as the data on the transmission path.

The process for receiving this data is as follows. First, when the pattern of "0111 1110" (HDLC flag) is detected, this is discarded, and this is taken in as the start of the frame from the following data. When the pattern "111110" is detected during the reception of frame data, "0" is deleted (transparency is maintained). CR for error control while receiving frame
Continue to calculate C. When the next HDLC flag is detected, the processing up to that point is treated as the same frame.

Now, a case where the apparatus of this embodiment can receive data based on HDLC as the data type A will be described with reference to FIG. First, the data D is held in the input buffer 11 (S1), and when it reaches the designated amount (S2), the designated amount of data D is taken out (S3). Then, the data type / frame configuration determination unit 13 determines the type and frame configuration of the specified amount of data D (S4).
Specifically, the HDLC flag is searched from the beginning of the specified amount of data D, and if no HDLC flag is detected, all of the data C is deleted by the data discarding unit 15.
And discard (S5). If the HDLC flag is detected, the next HDLC flag is detected. Two HDLC
When the flag is detected from the specified amount of data D (S6),
The data A ₁ between both flags is supplied to the frame extracting unit 14, and the data A ₂ of the contents of the frame is processed by the processing described above.
Is taken out (S7) and passed to the subsequent process of analyzing this data A ₂ (S8). If the data type / frame structure determination unit 13 detects only the head flag,
All the subsequent data A ₁ ′ from the head flag is returned to the input buffer 11 (S9). As a result, the next designated amount of data D is started from the HDLC flag.

Next, the case where the receivable protocol is BSC will be described. As an example of BSC, ITU
-T Recommendation V. The model shown by 42 is shown in FIG.
This is a start flag sequence code (SYN + DLE + STX) 31 indicating the start of communication, a header code 32 and an information code 33 which are the main body of the data text,
Stop flag sequence code (DL
E + ETX) 34 and a BCC code 35 which is a CRC code as a frame check sequence. For example, in a BSC frame, "01 01 10
The data represented by 10 "(hexadecimal notation) is as shown in FIG. 6 as the data on the transmission path.
(A) Data in character units, (b) 'SYN + DLE + STX' at the beginning of the frame, (c) 'DLE' as data in the frame is represented by'DLE + DLE ', (d) "BCC"
(E) 'DLE + ET at the end of the frame
I'm happy to have X '.

When this data is received, it is processed as follows. "0101 1000 0000 1000000
The data until the reception of 0 0100 "(SYN + DLE + STX) is discarded, and when (SYN + DLE + STX) is received, the data starts to be taken in as the start of the frame. Following the pattern of" 0000 1000 "(DLE)," 11000000 "(ETX) If a pattern other than is received, DLE is deleted (transparency is maintained) .CR is used for error control while receiving a frame.
Continue to perform C calculations. "0000 1000 1100 0000" (DL
When E + ETX) is received, the data up to the next two characters is treated as a frame.

When the apparatus of this embodiment can receive BSC data as the data type B, the data type / frame structure determination unit 13 detects the above-mentioned characteristics of the BSC and the frame structure is completed. The data B ₁ , the incomplete data B ₁ ′, and the data C not satisfying the model B are distributed and supplied to the respective parts. Frame take-out section 14
Executes the above-mentioned processing to execute data B ₂ of the contents of the frame.
Just take out.

In the input buffer 11, the data A ₁ ′,
The process of returning B ₁ ′ may actually be the process of returning the address pointer to the original position. In addition, the input buffer 11 (RA
The predetermined amount fetched from M2) does not have to be a fixed amount, for example, when the frame length is long and the process of returning the data to the input buffer 11 without completing the frame structure continues. The amount of data to be extracted may be increased.

According to the above apparatus, since the data type determination and the frame extraction are all performed by the data reception control processing means, when the data type to be received is changed, only the contents of the ROM 5 are changed. It has the advantage of being able to deal flexibly with system changes. Further, the above-described data reception control processing means (particularly the ROM 5) is provided with a plurality of processes (programs) capable of coping with a plurality of different data types (data link protocols) in advance, so that it is possible to perform any setting operation beforehand It becomes possible to deal with the data type of.

For example, as shown in FIG. 7, the modem 41 of this embodiment corresponding to a plurality of protocols (a plurality of data types such as HDLC and BSC as data types) A and B.
And the protocol (eg HDLC as the data type)
Assuming that a modem 42 corresponding to A and a modem 43 corresponding to a protocol (for example, BSC as a data type) B are connected via a transmission line, if the modem 41 is set to the protocol A The communication with the modem 42 becomes possible, and if the modem 41 is set to the protocol B, the communication with the modem 43 becomes possible.

Even if data is transmitted from both the modems 42 and 43 in a state where the modem 41 is set to the protocol A, as shown in FIG. 8, a specified amount of data is taken out from the input buffer for judgment. Since the data of the type B is discarded at this point, it does not affect the communication of the type A.

[0024]

As described above, according to the present invention,
A receiver circuit (hardware) that does not depend on the data type,
Since it is provided with an input buffer or an external memory for holding the data received by this receiving circuit and a data reception control processing means (software) for judging the data type, it is possible to flexibly deal with a plurality of data types. There are advantages.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data reception processing device according to an embodiment of the present invention.

FIG. 2 is a functional block diagram of the device.

FIG. 3 is a diagram for explaining a frame format in HDLC and BSC.

FIG. 4 is a diagram showing an example of HDLC type data.

FIG. 5 is a flowchart for explaining a data extraction process in the same device.

FIG. 6 is a diagram showing an example of BSC type data.

FIG. 7 is a diagram showing an application example of the embodiment.

FIG. 8 is a diagram showing an example of a structure of data held in an input buffer of the embodiment.

[Explanation of symbols]

1 ... Receiving circuit, 2 ... RAM, 3 ... DMA controller, 4 ... C
PU, 5 ... ROM, 6 ... System bus, 11 ... Input buffer, 12 ... Specified amount data extraction unit, 13 ... Data type /
Frame configuration determination unit, 14 ... Frame extraction unit, 15 ... Data discarding unit, 21 ... Start flag, 22 ... Address field, 23 ... Control field, 24 ... Information field,
25 ... FSC, 26 ... end flag, 31 ... start flag sequence code (SYN + DLE + STX), 32
... header code, 33 ... information code, 34 ... stop flag sequence code (DLE + ETX), 35 ... BC
C code, 41-43 ... Modem.

Claims (2)

[Claims] 1. A receiving circuit for receiving transmitted data without data manipulation, an input buffer for holding data received by the receiving circuit, and preset data held in the input buffer. The specified amount of data is collectively extracted, and it is determined whether the specified amount of data is data of a predetermined predetermined type and includes a completed frame structure, and the specified amount of data is the data of the predetermined type. And including the completed frame structure, the contents of the frame obtained by the above model are extracted from the specified amount, and when the specified amount of data is the predetermined model data and constitutes a part of the frame, Data reception that returns a specified amount of data to the input buffer, and discards the specified amount of data if it is not the predetermined type of data Data reception processing apparatus characterized by comprising a control processing unit. 2. A receiving circuit for physically connecting the transmitted data to receive the data, an external memory for temporarily holding the data received by the receiving circuit, and a plurality of data link protocols. In the data reception control processing means corresponding to, one protocol to be received is selected in advance, the data held in the external memory is collectively extracted into a preset designated amount, and the designated amount of data is It is determined whether the data is in accordance with the selected protocol and includes a completed frame configuration, and if the specified amount of data is data in accordance with the selected protocol and includes a completed frame configuration, from the specified amount. The contents of the frame required by the above protocol are extracted, and the specified amount of data is transferred according to the selected protocol. Data reception control in which the specified amount of data is returned to the external memory when the data is a part of a frame and the specified amount of data is not the data of the selected protocol. A data reception processing device comprising: a processing unit.