JP3255120B2 - Trailer processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication control apparatus and, more particularly, to a system for performing high-speed protocol processing in an apparatus for performing OSI layer 2 processing of a protocol having a variable frame length and control information present in a trailer unit. .

[0002]

2. Description of the Related Art Conventionally, an OSI (Op
en Systems Interconnection) Layer 2 frame control is processed by hardware and firmware. In this method, the hardware recognizes the start / end of the frame at the time of reception, and the firmware processes the control information existing in the header part in the frame. Further, the processing performance of user information is improved by transparently (transparently) DMA (direct memory access) transfer to a memory handled by an upper layer.

Incidentally, for example, ITU-T Recommendation Q. 21
Service Specific Connection Oriented Protocol
col; SSCOP) is an ATM adaptation layer (AAL) CS (Convengence Sublayer) service dependent unit (SSCS; Service Specific ConvengenceSu).
and used to transfer variable length service data units (SDUs) between users. The frame length is variable (8-65532 octets), and the control information exists in the trailer unit.

[0004] SSCOP is an asynchronous transfer mode (ATM).
Is used to transfer information between Layer 3 entities of the AAL for signaling on the virtual channel (VC).

[0005] As described above, in the protocol in which the control information has a variable frame length and the control information exists in the trailer unit, the position of the control information in the frame cannot be identified at the start of the reception of the frame. For this reason, conventionally, in a communication apparatus that performs this type of protocol processing, a received frame is temporarily transferred to an upper-layer memory by a DMA method, and after the DMA transfer is completed, a trailer unit is included in the frames that have passed through the inside of the apparatus. Has to be transferred again from the memory of the host device by DMA transfer and read, and protocol processing has to be performed.

FIG. 5 shows a configuration of a conventional communication control device. The layer 2 protocol processing device 1 is a device that performs layer 2 frame control using hardware and firmware. Information to a lower layer is transferred via a line interface. Information to the upper layer is performed by sharing an upper layer RAM (random access memory) 8. The CPU 2 is a processor that performs layer 2 protocol processing, and its firmware is stored on the RAM 5. The reception control unit 6 is a hardware device that performs frame transmission / reception control, and detects a frame start / end flag, a start / end signal, etc.
It recognizes the start / end of frame reception and stores the received frame in the buffer.

The DMA controller 4 is a control unit when the CPU 2 makes a DMA access to the upper memory 8.
DMA transfer of the received data from the reception control unit 6 is performed according to an instruction from the CPU 2.

The operation of the conventional device shown in FIG. 5 will be described.

When the reception control unit 6 recognizes the start of frame reception by detecting a frame start flag, detecting a frame start signal from a lower layer, or the like, it generates a reception start interrupt to the CPU 2.

As a result, the CPU 2 sets a transfer destination address and starts a DMA write transfer to the upper layer RAM 8.

When the reception control unit 6 recognizes the completion of frame reception by detecting a frame end flag, detecting a frame end signal from a lower layer, or the like, it terminates the DMA transfer and generates a reception end interrupt to the CPU 6. Also, the number of transfer bytes is notified.

Thereafter, the address of the trailer position is calculated from the number of transfer bytes, and the DMA is started again to read the trailer contents from the upper memory 8 and perform the protocol processing.

[0013]

The above-mentioned conventional method has the following problems.

That is, in the protocol in which the variable frame length and the control information exist in the trailer unit, the position of the control information in the frame cannot be identified when the DMA transfer is started at the start of the frame reception. Therefore, after the transfer is completed, it is necessary to DMA-transfer and read the trailer portion of the frames that have passed through the inside of the apparatus.

In this case, since the number of times of DMA transfer is increased, the throughput of the entire apparatus is reduced, which is a factor that hinders the realization of high-speed data communication.

Therefore, the present invention has been made in view of the above-mentioned problems, and has as its object to provide an OS of a protocol having a variable frame length and control information existing in a trailer unit.
It is an object of the present invention to provide a system that improves the throughput of an apparatus that performs I layer 2 processing.

[0017]

In order to achieve the above object, the present invention provides a communication control device including a trailer buffer,
Data is sequentially stored in the trailer buffer at the time of DMA transfer, and when frame reception is completed, control information can be immediately read from the trailer buffer. This makes it unnecessary to transfer the control information of the trailer unit from the memory of the upper layer, and improves the throughput of the entire apparatus.

In the present invention, the trailer buffer comprises:
Since it is configured by a FIFO (First In First Out; first-in first-out buffer), the hardware configuration can be easily realized.

[0019]

Embodiments of the present invention will be described below. The present invention provides an apparatus for performing OSI layer 2 processing of a protocol in which a variable frame length and control information are present in a trailer unit. When a frame is received, the frame data is sequentially stored in a trailer buffer when the frame is DMA-transferred to an upper layer memory. The control information can be immediately read from the trailer buffer when the frame is received and the frame reception is completed.

According to the present invention, a reception control section (6) for detecting start / end of frame reception and notifying to a CPU and performing frame reception processing, and a reception control section (6) receiving instructions from the CPU (2). Transfer data to upper layer memory (8)
When the DMA controller (4) performing the MA transfer and the DMA controller (4) perform the DMA transfer of the received frame data to the upper layer memory (8), a first-in first-out trailer buffer ( 3), when the transfer of the received frame to the upper layer memory (8) is completed, the control information is stored in the trailer buffer (3). The protocol processing is performed by reading the control information from).

In the embodiment of the present invention, the redundant DMA transfer for reading the frame control information, which is required in the conventional device, is not required, and the bus right acquisition time and the memory access time can be reduced. In addition, the speed of the frame receiving process can be increased, and when a large number of control frames are received, the speed can be increased.

Further, according to the embodiment of the present invention, the processing interruption time of the upper layer processor due to the acquisition of the bus right of the layer 2 processor can be reduced, so that the protocol processing capability of the upper layer can be improved. Further, according to the embodiment of the present invention, the received data is DMA-transferred to the upper memory, so that the firmware processing of the layer 2 can be reduced and the load on the line is avoided.

As described above, according to the embodiment of the present invention, not only the layer 2 processing but also the throughput of the entire apparatus can be improved.

[0024]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of one embodiment of the present invention.

Referring to FIG. 1, a layer 2 protocol processing device 1 controls a layer 2 frame by hardware and firmware. Information to a lower layer is transferred via a line interface. Information to the upper layer is performed by sharing an upper layer RAM (random access memory) 8.

The CPU 2 is a processor that performs layer 2 protocol processing, and its firmware is stored in the RAM 5.
Stored above.

The reception control unit 6 is a hardware device for controlling transmission and reception of frames. The reception control unit 6 recognizes the start / end of frame reception by detecting a frame start / end flag and a start / end signal, and buffers the received frame. To be stored.

The DMA controller 4 is a control unit when the CPU 2 performs the DMA access to the upper memory 8. The DMA controller 4 performs the DMA transfer of the reception data from the reception control unit 6 in accordance with an instruction from the CPU 2.

The trailer buffer 3 is a FIFO (first-in first-out) buffer for storing trailers. FIG.
FIG. 3 is a diagram schematically showing a configuration of a trailer buffer 3.

Referring to FIG. 2, the received frame length is n octets, and the size of the FIFO buffer is m bytes. Since the control information can be variable in length depending on the protocol, the maximum length m octets of the required control information is set to FI
FO size.

When the DMA controller 4 DMA-transfers the received frame to the upper layer RAM 8, the contents of the transfer are simultaneously stored in the trailer buffer 3.

In the trailer buffer 3 composed of the FIFO type buffer as shown in FIG. 2, data exceeding the buffer length (m bytes) is sequentially discarded.

Therefore, the DM to the upper layer RAM 8 is
At the end of the A transfer, it can be seen that the last m bytes of the frame from the (n−m + 1) th to the nth octets are retained in the FIFO buffer constituting the trailer buffer 3.

By configuring this FIFO as an m-byte register, the CPU 2 can read an arbitrary position in the trailer buffer 3 by register access (register read).

FIG. 4 is a diagram for explaining the operation at the time of frame reception in one embodiment of the present invention.

When the reception control unit 6 recognizes the start of frame reception by detecting a frame start flag, detecting a frame start signal from a lower layer, or the like, it generates a reception start interrupt to the CPU 2.

As a result, the CPU 2 sets the transfer destination address in the DMA controller 4 and sets the upper layer RAM 8
Start a DMA write transfer to

When the reception control unit 6 recognizes the completion of frame reception by detecting a frame end flag, detecting a frame end signal from a lower layer, or the like, it terminates the DMA transfer and generates a reception end interrupt to the CPU 6. Also, the number of transfer bytes is notified.

When the frame reception is completed and the DMA transfer is completed, since the last m bytes of data of the frame remain in the trailer buffer 3, the CPU 2 performs the protocol processing by reading out the necessary number of bytes from the data. be able to.

FIG. 5 is a flowchart showing the processing flow of one embodiment of the present invention. When the reception control unit 6 recognizes the start of frame reception, a reception start interrupt is generated in the CPU 2 (step 101).

The CPU 2 sets a transfer destination address in the DMA controller 4 and starts a DMA write transfer to the upper layer RAM 8 (steps 102 and 103). DM
Repeat the A transfer until the reception is completed (step 104,
105).

When the reception control unit 6 recognizes the completion of frame reception by detecting a frame end flag, detecting a frame end signal from a lower layer, or the like, it terminates the DMA transfer (step 106) and issues a reception end interrupt to the CPU 2. appear. Also, the transfer byte number is notified (step 10).
7).

The CPU 2 reads the required number of bytes from the trailer buffer 3 (steps 108 and 109),
The PU2 performs protocol processing and reports to the upper layer (steps 110 and 111).

[0044]

As described above, according to the present invention,
Since redundant DMA transfer for reading the frame control information is not required, the bus right acquisition time and the memory access time can be reduced, and the speed of the frame reception processing can be increased. In particular, when receiving many control frames, the effect is very high.

According to the present invention, the processing interruption time of the upper layer processor due to the acquisition of the bus right by the layer 2 processor can be reduced, so that the protocol processing capability of the upper layer can be improved.

Further, according to the present invention, since the received data is DMA-transferred to the upper memory, the firmware processing of the layer 2 can be reduced, and the load on the line is avoided.

As described above, according to the present invention, it can be said that not only the layer 2 processing but also the throughput of the entire apparatus can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a trailer buffer according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining one embodiment of the present invention.

FIG. 4 is a flowchart showing a processing flow of an embodiment of the present invention.

FIG. 5 is a diagram for explaining a conventional device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Layer 2 protocol processing apparatus 2 CPU 3 Trailer buffer 4 DAM controller 5 RAM 6 Reception control unit 7 Upper layer CPU 8 Upper layer RAM

Claims (6)

(57) [Claims] An apparatus for processing data of a protocol in which a frame length is variable and whose control information is present in a trailer unit is provided with a trailer buffer, and when a received frame data is DMA-transferred to an upper layer memory. Transferring the transfer data sequentially to the trailer buffer, and performing protocol processing by reading control information retained in the trailer buffer when transfer of the received frame to the memory of the upper layer is completed. Features trailer processing system. 2. The trailer processing system according to claim 1, wherein said trailer buffer comprises a first-in first-out buffer. 3. A communication control device for processing data of a protocol in which a frame length is variable and control information is present in a trailer unit, comprising a trailer buffer, and transmitting received frame data to a memory of an upper layer by a DM.
A, when the transfer, the transfer data is also sequentially transferred to the trailer buffer, and when the transfer of the received frame to the upper layer memory is completed, the control information is stored in the trailer buffer. A communication control device characterized by the above-mentioned. 4. The communication control device according to claim 3, wherein said trailer buffer comprises a first-in first-out buffer. 5. A CPU which detects start / end of frame reception and detects
A reception controller that performs a frame reception process, a DMA controller that DMA-transfers received data from the reception controller to an upper-layer memory according to an instruction of the CPU, and the DMA controller converts received frame data into A first-in, first-out trailer buffer, in which transfer data is stored at the same time as the DMA transfer to the upper-layer memory, wherein when the transfer of the received frame to the upper-layer memory is completed, the control information A communication control device stored in the trailer buffer, wherein the CPU performs protocol processing by reading control information from the trailer buffer. 6. The variable length frame has a length of n octets, the trailer buffer size has a length of m octets, and at the end of the DMA transfer to the upper layer memory,
The last m bytes of the frame from n−m + 1 to the n-th octet are retained in the trailer buffer, and the trailer buffer is used as an m-byte register, and the CPU reads the trailer buffer by register read access. 6. The communication control device according to claim 5, wherein required protocol processing is performed by reading an arbitrary position.