JPH09121038A - Semiconductor device and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the joint area of a source/drain diffusion layer and realize a high-speed operation of a device by covering the side wall of a spacer with a conductive layer for the contact connecting electrically with the source/drain. SOLUTION: A spacer 24 is formed on the side part of a gate electrode 31 and a source/drain area is formed by using it as a mask. A conductive layer made of polysilicon, etc., is piled up through a CVD method, and a resist, etc., are formed on the conductive layer, then the resist is left in the recessed part of the surface of the flattened element. Further it is entirely etched through reactive ion etching, so that the polysilicon remains in a self-alignment contact hole and a conductive layer 32 for the contact is formed as a result. Thus, the layer 32 is also formed on the surface of the source/drain area as well as the side wall of the self-alignment contact hole, that is, the side wall of the spacer 24 and the side wall of a field oxide film 21. The contact formation area is enlarged from the conventional L' to L, so the area of the source/drain diffusion layer can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a gate array including a MOS transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, self-aligned contacts (hereinafter abbreviated as SAC) have been adopted in gate arrays and the like. A conventional SAC forming method will be described with reference to FIG.

FIG. 3A shows a state in which a field oxide film 21, a gate oxide film 22 and a gate electrode 31 are formed on the substrate 10. After that, as shown in FIG. 3B, the LDD region 11 is formed by ion implantation, and then the spacer (side wall) 24 is formed on the side portion of the gate electrode 31. Then, using the spacers 24 as a mask, the source / drain regions 12 having a high concentration are formed. At least ASIC (Application Specific Integrated Ci
In the case of rcuit), the interlayer insulating film 25 is grown and the contact hole 4 is formed by using a known photoresist technique.
When forming the contact hole 4, a certain distance Δ is set so as not to open on the end of the spacer 24 or on the spacer.
It is necessary to keep L. This distance ΔL is determined by several parameters.

Explaining these parameters, the spacer width variation amount (especially when the spacer width becomes wide) ΔL1 and the contact hole size variation amount ΔL2.
(Especially when the size becomes large), the misalignment amount ΔL3 of the stepper and the misalignment amount ΔL of the stepper in the photoresist process for contact formation.
It can be divided into four. The sum of these ΔL = (ΔL1
+ ΔL2 + ΔL3L + ΔL4) is the minimum dimension that must be taken from the spacer edge. Since this ΔL is required, the cell area of the gate array cannot be reduced.

The gate array will be described in more detail. The gate array is designed by introducing the concept of a grid. The smaller the grid, the smaller the cell size and higher integration, and also the smaller the load capacity and the lower power consumption.

If the grid size is sufficiently large, the contact hole 4 will not be formed on the spacer 24 and the contact resistance will not increase, as shown in FIG. However, when the grid size is small and the contact holes are present on the spacer as shown in FIG. 4B, not only the contact resistance increases but also the contact resistance varies. Further, even if the contact hole does not exist on the spacer from the beginning, the contact resistance also similarly varies when the contact hole exists on the spacer due to misalignment of the stepper, for example. .

For example, if the grid size is 0.25 μm, the gate length is 0.22 μm, the contact size is 0.3 μm, the spacer length is 0.14 μm, and the misalignment amount of the stepper is 0.08 μm. Figure 4
As shown in (A), the contact hole 4 can be configured not to exist on the spacer 23.

However, the grid size is 0.18 μm
In the same manner, when the gate length is 0.22 μm, the contact size is 0.3 μm, the spacer length is 0.14 μm, and the misalignment amount of the stepper is 0.08 μm, the misalignment of the stepper becomes maximum. Figure 4
As shown in (B), the contact hole 4 may exist on the spacer 24. This causes the contact resistance to vary.

As described above, when the grid size is reduced in order to improve the degree of integration, the contact holes are present on the spacer by design, or the contact holes are formed on the spacer depending on the misalignment amount of the stepper. To exist in. In order to prevent such contact holes from existing on the spacer, as described above, Δ
Although L is required, the presence of this ΔL increases the junction area of the diffusion layer, which is related to the increase in load capacitance. This has been a hindrance to high speed and low power consumption.

The present invention has been made in view of the above circumstances, and a semiconductor capable of further reducing the junction area of the source / drain diffusion layers in a semiconductor device such as a gate array and achieving higher speed and lower power consumption. An object is to provide an apparatus and a manufacturing method thereof.

[0011]

In order to achieve the above object, the present invention provides the following semiconductor device and its manufacturing method. (1) In a semiconductor device including a MOS transistor having a source / drain, a gate electrode, and a spacer existing on a side portion of the gate electrode, a contact conductive layer electrically connected to the source / drain has a sidewall of the spacer. A semiconductor device, characterized in that a part or the whole thereof is covered. (2) The semiconductor device according to the above (1), wherein the contact conductive layer covers the source / drain surface where the contact is to be formed and a part or all of the sidewall of the spacer. (3) a step of forming a gate electrode of a MOS transistor, a step of forming a spacer on a side portion of the gate electrode,
Forming a source / drain, forming a contact conductive layer electrically connected to the source / drain of the MOS transistor on the source / drain surface including the spacer sidewall, and forming an interlayer insulating film When,
And a step of forming a contact hole reaching the contact conductive layer in the interlayer insulating film.

In the semiconductor device of the present invention and the semiconductor device manufactured by the method of the present invention, the conductive layer for contact is formed so as to cover not only the source / drain surface of the MOS transistor but also the sidewall of the spacer existing on the side of the gate electrode. Has been done. With this contact conductive layer, the source / drain and the wiring layer can be electrically connected.

For this reason, conventionally, the region where the contact hole can be opened is limited to the surface of the source / drain, and if a part of the contact hole is applied to the spacer, the contact resistance varies, whereas in the present invention, the contact hole is the spacer. Even if the contact occurs, the contact resistance does not increase because the side wall of the spacer has the conductive layer.

Therefore, the width of the contact hole forming region is enlarged as compared with the conventional case, and the margin for misalignment of the stepper is increased. Therefore, the source / drain region can be designed narrower than the conventional case, and the area of the source / drain region is increased. Since the size can be reduced, the junction capacitance can be reduced, and high speed operation and low power consumption can be achieved.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below. FIG. 1 is a flow chart illustrating a manufacturing process of a semiconductor device of the present invention. FIG. 1 (A)
Is a field oxide film 21 and a gate oxide film 2 on the substrate 10.
2 shows a state in which the gate electrode 31 and the insulating film 23 on the gate electrode are formed. Then, as shown in FIG. 1B, an LDD region 11 is formed by ion implantation, and then a spacer (side wall) 24 is formed on a side portion of the gate electrode 31.
To form Then, using the spacers 24 as a mask, the source / drain regions 12 having a high concentration are formed.

Then, as shown in FIG. 1C, a contact conductive layer 32, which is a feature of the present invention, is formed. The contact conductive layer 32 is formed, for example, by depositing a conductive layer such as polysilicon by CVD or the like, forming a resist or the like on the conductive layer, and flattening the element surface by a known technique to form a recess on the element surface. After the resist is left to remain, the entire surface is etched by reactive ion etching, so that polysilicon can be formed in the self-aligned contact hole.

As a result, the contact conductive layer 32 is
Not only the surface of the source / drain, but also the sidewall of the self-aligned contact hole, that is, the sidewall of the spacer 24 and the sidewall of the field oxide film 21. The material of the conductive layer may be a metal such as titanium or tungsten, or a silicide of these metals, in addition to the above polysilicon.

Next, as shown in FIG. 1D, after forming an interlayer insulating film 25, contact holes 4 are formed on the source / drain surfaces by known photolithography. In this example, the contact hole 4 is opened on the contact conductive layer 32.

The conductive layer 32 for contact is the spacer 24.
Since the side wall and the side wall of the field oxide film 21 are also formed, as shown in FIG.
It is expanded from the conventional L'to L. Therefore, the position of formation of the contact hole 4 varies due to the above variation amount, and as shown in FIG. 2, even if the contact hole 4 overlaps with the spacer, the contact conductive layer 32 (in the figure) is formed on the sidewall of the spacer. , The hatched portion) is formed, so that the contact resistance does not increase.

Conventionally, the size of the source / drain in the gate length direction has been designed in consideration of the misalignment amount (margin), but the increase in the contact hole resistance can be prevented without taking this margin. Therefore, by designing the contact holes so that they overlap the spacers, or by adopting a grid size that allows the contact holes to overlap the spacers when misalignment of the stepper occurs,
The width of the source / drain diffusion layer can be narrowed, and as a result, the area of the source / drain diffusion layer can be reduced and the junction capacitance can be reduced. Junction capacitance is reduced by MOS
Contributes to higher transistor speeds.

The power consumption (P) is expressed by P∝CfV ² . Here, C is the load capacitance, f is the operating frequency, and V is the applied voltage. The fact that the junction capacitance can be reduced also means that the load capacitance C can be reduced.
The power consumption can be reduced.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the contact conductive layer is formed so as to cover the source / drain surface, the spacer side wall, and the field oxide film side wall. However, since the margin increases, the same effect can be obtained. Besides, various modifications can be made without departing from the scope of the present invention.

[0023]

As described above, the semiconductor device of the present invention can widen the width of the contact opening region and suppress the variation of the contact resistance value. Furthermore, since the bonding area can be reduced, it is possible to achieve high speed and low power consumption.

Further, according to the method of manufacturing a semiconductor device of the present invention, such a semiconductor device can be reliably manufactured.

[Brief description of the drawings]

FIG. 1 is a flowchart showing manufacturing steps of a semiconductor device of the present invention.

FIG. 2 is a plan view showing a cell of a semiconductor device of the present invention.

FIG. 3 is a flowchart showing manufacturing steps of a conventional semiconductor device.

FIG. 4 is a plan view showing a cell of a conventional semiconductor device.

[Explanation of symbols]

 4 Contact Hole 10 Substrate 12 Source / Drain 21 Field Oxide Film 22 Gate Oxide Film 24 Spacer (Sidewall) 25 Interlayer Insulation Film 31 Gate Electrode 32 Conductive Layer for Contact

Claims (3)

[Claims] 1. A semiconductor device including a MOS transistor having a source / drain, a gate electrode, and a spacer existing on a side of the gate electrode, wherein a contact conductive layer electrically connected to the source / drain is the spacer. A semiconductor device characterized in that part or all of a side wall is covered. 2. The semiconductor device according to claim 1, wherein the conductive layer for contact covers the source / drain surface where the contact is to be formed and a part or all of the side wall of the spacer. 3. A step of forming a gate electrode of a MOS transistor, a step of forming a spacer on a side portion of the gate electrode, a step of forming a source / drain, and an electrically connected source / drain of the MOS transistor. A step of forming a contact conductive layer to be connected on the source / drain surface including the spacer side wall; a step of forming an interlayer insulating film; and a step of forming a contact hole reaching the contact conductive layer in the interlayer insulating film. A method of manufacturing a semiconductor device, comprising: