JPH09116444A - Interleaving device, encoding device deinterleaving device, decoding device and transmission method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively use the capacity of an error correction code by using an M-system generator for the generation of a write/read address when a memory circuit is used and exchanging the order of data. SOLUTION: A write address circuit 2 sequentially stores data by a binary counter and the memory circuit 1 by an address signal 21. The values of respective registers constituting the M-system generator 3 are used for the read address signals 22 of stored data. The counter and the M-system generator are synchronized by a synchronizing signal through a control circuit 4. Thus, data is interleaved or de-interleaved at every prescribed interleaving periods. Since the order of data can be exchanged without synchronism, the errors of data can be distributed and the capacity of the error correction code can effectively be fulfilled without the continuity of the errors after de-interleaving.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleaving device, an encoding device, a deinterleaving device, a decoding device, and a transmission method suitable for use in a wireless communication system in which a signal level changes due to fading or the like. is there.

[0002]

2. Description of the Related Art As a transmission method, for example, in a wireless communication system, some countermeasures have been proposed for data errors occurring on a communication transmission path. One of the countermeasures is an error correction method. That is, FIG.
3 shows a block diagram of a communication system using error correction.

In FIG. 5, a block 101 is an information source in a communication system, a block 102 is an information source coding unit, a block 103 is a communication channel coding unit, and a block 10.
4 is a communication transmission line which is an error source, block 105 is a communication channel decoding unit, block 106 is an information source decoding unit, and block 1
Reference numeral 07 is a receiver in the communication system.

A block 112 is a channel coding unit 1.
A block 112 is an interleaver that constitutes the channel coding unit 103. Further, a block 121 is an error correction decoder constituting the channel decoding unit 105, and a block 122 is a channel decoding unit 1.
It is a deinterleaver that constitutes 05.

In this apparatus, the information source coding unit 102 compresses the information in order to reduce the redundancy of the information emitted from the information source 101. Next, in order to prepare for an error due to the communication channel 104, the channel encoder 103
In, encoding with error correction capability is performed.

Further, the channel coding unit 103 comprises an error correction coding unit 111 and an interleaver 112. Then, the error correction encoder 111 performs error correction coding using a convolutional code, a block code, or the like, and the interleaver 112 changes the order of the coded bits so that the error correction capability can be effectively corrected. Done.

That is, in the communication transmission path 104, a random error or a burst error occurs in the communication path coded signal due to random noise or fading. Therefore, for example, for burst errors that are partially erroneously continuous, the error bits are dispersed by performing interleaving that changes the order, and it is possible to effectively use the error correction capability.

Therefore, in the channel decoding unit 105, the deinterleaver 121 forming the channel decoding unit 105 first reverses the interleaver 112 of the channel encoding unit 103 with respect to various errors generated in the channel transmission unit 104. The order is restored by the operation of. By this operation, continuous errors such as burst errors are dispersed. Next, the error correction code is decoded by the error correction decoder 122 that constitutes the channel decoding unit 105.

Therefore, in this case, the deinterleaver 1
Since the error is dispersed by 21, the error correction decoder 12
It is possible to effectively use the error correction capability of 2.

Further, FIG. 6 shows a detailed block diagram of the interleaver 112 and the deinterleaver 121. In FIG. 6, a block 201 is a memory circuit for changing the order of data, a block 202 is a write address generating circuit that outputs an address when writing data to the memory, and a block 203 is an address when reading data from the memory. It is a read address generating circuit for outputting.

Further, a block 204 is an address generation control circuit for controlling the address generation of the write address generation circuit 202 and the calling address generation circuit 203 and the input / output of the memory circuit 201.

In the figure, reference numeral 211 is an input data signal to the memory, reference numeral 212 is an output data signal from the memory, reference numeral 221 is a write address signal indicating an address when writing to the memory, and reference numeral 222 is read from the memory. This is a read address signal that represents the address at time.

In this circuit, the memory circuit 20
The input data signal 211 input to 1 is the control circuit 204
Is temporarily recorded in the memory circuit 201. At that time, the address of the memory circuit 201 is the write address signal 22 output from the write address generation circuit 202.
1 and the write address generation circuit 202 is controlled by the address control circuit 204.

Next, the stored data is output as the output data signal 212 according to the control circuit 204 to the memory circuit 201.
Output from At that time, the address of the memory circuit 201 is controlled by the read address signal 222 output from the read address generation circuit 203, and the read address generation circuit 203 is controlled by the address control circuit 204.

By these operations, the control circuit 204 controls the timing of writing and reading, and the order of data flow is changed by the address generation algorithm of the write address generation circuit 202 and the address generation algorithm of the read address generation circuit 203. There is.

The interleaver and the deinterleaver have the same structure and are the same as those in the block diagram 6, but since the input address and the output address to the memory are different, the inside of the address generation circuit is different.

Therefore, the interleaver will be described first. Generally, the interleaver controls two address circuits for writing and reading to and from the memory as shown in FIG. 6 to write data and then read it, and change the order depending on the difference in the address. Therefore, several methods are conceivable depending on when the order is changed. Here, a method of changing the order at the time of reading will be described as an example.

That is, in the method in which the order is changed at the time of reading, the address at the time of writing is the output of a normal 4-bit binary counter, and the address at the time of reading is the upper bit and the lower bit of the 4-bit binary counter, for example. I shall. Note that the synchronization of these counters is
It is performed by an arbitrary synchronization signal.

Therefore, the write address circuit 202 of FIG.
For example, a 4-bit binary counter as shown in FIG. 7 is used. As a result, the order of write addresses is as follows. Write address: 0,1,2,3,4,5,6,7,8,9,10,11,12,1
3, 14, 15 As a result, the input data is stored in the memory circuit 201 of FIG. 6 in order.

On the other hand, the read circuit 203 shown in FIG.
For example, a counter in which the upper bits and the lower bits of a 4-bit binary counter as shown in FIG. 8 are replaced is used. Therefore, the order of read addresses is as follows. Read address: 0,8,4,12,2,10,6,14,1,9,5,13,3,1
1,7,15 Therefore, the data input to the memory circuit 201 of FIG. 6 is output after the order is changed according to the read address.

Further, a deinterleaver corresponding to the above interleaver will be described. That is, the deinterleaver plays a role of returning the data whose order has been changed by the interleaver to the original order. Therefore, like the interleaver, the deinterleaver also has a method of changing the order when writing to the memory and a method of changing the order when reading, but here the order is changed at the time of writing so that the correspondence with the interleaver described above can be easily understood. The method of exchanging is explained.

Therefore, in the method in which the order is changed at the time of the write address, an address obtained by inverting the upper bit and the lower bit of the output of the 4-bit binary counter is used as the address at the time of writing, and the address at the time of reading is set to the normal 4-bit binary. The output of the binary counter. The synchronization of these counters is performed by the synchronization signal in the transmission signal.

Therefore, the write address circuit 202 of FIG.
For example, a counter in which the upper bit and the lower bit of the 4-bit binary counter in FIG. 8 are replaced is used. As a result, the order of write addresses is as follows. Write address: 0,8,4,12,2,10,6,14,1,9,5,13,3,1
1,7,15

As a result, the memory circuit 201 shown in FIG.
The input data is recorded by changing the order. However, in this case, the order of the write addresses is the same as the order in which the write addresses are replaced by the interleaver described above, so that the order of the written data is eventually returned to the original order.

On the other hand, the read address circuit 20 shown in FIG.
For 3, for example, the normal 4-bit binary counter of FIG. 7 is used. Therefore, the order of read addresses is as follows. Read address: 0,1,2,3,4,5,6,7,8,9,10,11,12,1
3,14,15 As a result, the data input to the memory circuit 201 of FIG. 6 is output in order according to the read address.

Further, the effects of the interleaver and the deinterleaver by these operations will be described below.

That is, it is assumed that a burst-like error (*) occurs in the first 4 bits 0, 1, 2, 3 of the data string on the communication transmission line 104 of FIG. Error data sequence: *, *, *, *, 2,10,6,14,1,9,5,13,
3,11,7,15

However, in this case, in the deinterleaver, the first 4 bits 0, 1, 2, 3 are 0, 8, 4, 12
At the time of inputting to the error correction decoder 122 of FIG. 5, each bit of 0, 4, 8 and 12 is erroneous because it is stored in the address of and is output without changing the order in reading. Output data string: *, 1,2,3, *, 5,6,7, *, 9,10,11, *, 1
3,14,15

Therefore, in this apparatus, the errors generated in a burst are dispersed by the effect of the interleaver and the deinterleaver, and the error correction decoding in the error correction decoder 122 effectively functions.

[0030]

However, in such a communication system, a periodic error due to Rayleigh fading or the like occurs in the communication transmission line 104 of FIG.
For example, assume that an error occurs periodically in the data string every 4 bits. Error data sequence: *, 8,4,12, *, 10,6,14, *, 9,5,1
3, *, 11,7,15

In this case, in the deinterleaver, the four bits 0, 8, 4, 12 in which an error has occurred are converted into 0, 1, 2, 3
It is stored in the address of, and in reading, it is output without changing the order. Output data string: *, *, *, *, 4,5,6,7,8,9,10,11,12,
13,14,15

Therefore, in this case, the cyclically generated errors are concentrated on the continuous four leading bits, and the error correction decoding in the error correction decoder 122 cannot be effectively operated. .

As described above, in the interleave device and the deinterleave device described in the prior art, for example, the upper bit and the lower bit of the counter are exchanged for the address operation for exchanging the data order. Therefore,
Although data is distributed during communication, the distribution position has periodicity.

Therefore, when consecutive errors occur in the communication transmission line of the data interleaved in the transmission unit, the error positions of the data deinterleaved in the communication unit are distributed but have periodicity. Further, for an error having periodicity due to Rayleigh fading or the like, on the contrary, the error may not be dispersed and may be a continuous error.

Therefore, in the above-described conventional interleaving device, encoding device, deinterleaving device, decoding device, and transmission method, there is periodicity in the position of data error,
On the other hand, there is a problem in that, with respect to an error having a periodicity, the error becomes a continuous error, and the error correction capability of the error correction code used cannot be fully exerted.

[0036]

Therefore, in the present invention, when the order of data is changed using the memory circuit, the write address or read address is
The value of each register forming the M-sequence generator is used. According to this, the order of data can be exchanged without imparting periodicity, data errors can be dispersed, and It is possible to eliminate the periodicity at the error position, and even when the error position has the periodicity, the error does not continue after deinterleaving, and the ability of the error correction code can be effectively used.

[0037]

That is, in the present invention, storage means for temporarily saving data, write address generation means for generating a write address signal for writing data to a storage device, and data storage device. Read address generating means for generating a read address signal for reading from the memory, address generating control means for controlling the generation of the write address signal and the read address signal, and having M series generating means, a predetermined interleave. The data is interleaved or deinterleaved by the M sequence from the generation means for each cycle.

The present invention will be described below with reference to the drawings. First, FIG. 1 is a block diagram showing the configuration of an example of an interleave apparatus to which the present invention is applied.

That is, in general, the interleaver controls two address circuits for writing and reading to and from the memory as described above, so that data is written and then read, and the order is changed depending on the difference in the address. Therefore, several methods are conceivable depending on when the order is changed. Here, a method of changing the order at the time of reading will be described as an example.

Therefore, in FIG. 1, block 1 is a memory circuit for changing the order of data, and block 2 is a write address generating circuit for outputting an address when writing data to the memory. Block 3 is a read address generation circuit that outputs an address when data is read from the memory, and in this case, it is formed by an M series generator.

Further, block 4 is an address generation control circuit for controlling the address generation of the write address generation circuit 2 and the calling address generation circuit 3 and the input / output of the memory circuit 1.

In the figure, reference numeral 11 is an input data signal to the memory, reference numeral 12 is an output data signal from the memory, reference numeral 21 is a write address signal indicating an address when writing to the memory, and reference numeral 22 is read from the memory. This is a read address signal that represents the address at time.

In this circuit, in the method of changing the order at the time of reading, the output of a normal 4-bit binary counter is used as the address at the time of writing, and the address at the time of reading is M which is a feature of the present invention. The value of the shift register that constitutes the series generator is used. The synchronization of these counters and the M-sequence generator is performed by an arbitrary synchronization signal.

That is, the write address circuit 2 of FIG. 1 uses the 4-bit binary counter of FIG. 7 as in the conventional case.
As a result, the order of write addresses is as follows. Write address: 0,1,2,3,4,5,6,7,8,9,10,11,12,1
3,14,15 As a result, the input data is stored in order in the memory circuit 1 of FIG.

On the other hand, in the read address circuit 3 of FIG. 1, for example, an M series (PN (x) = x ⁴ as shown in FIG. 2 is used.
The address circuit using + x + 1) is used. Therefore, the values of the registers forming the M series irregularly change from 1 to 15 as shown in the explanatory diagram of the M series in FIG.

Therefore, if an address is obtained by adding 0 to somewhere in this sequence (here, 0 is inserted at the beginning), the order of read addresses is as follows. Read address: 0,8,3,6,12,11,5,10,7,14,15,13,
9,1,2,4 Therefore, the data input to the memory circuit 1 in FIG.
The output is changed according to the read address.

Further, a deinterleaver corresponding to the interleaver described here will be described with reference to FIG.

That is, the deinterleaver plays a role of returning the data whose order has been changed by the interleaver to the original order. Therefore, like the interleaver, the deinterleaver also has a method of changing the order when writing to the memory and a method of changing the order when reading, but here, in order to make it easier to understand the correspondence with the interleaver described above, A method of changing the order will be described.

Therefore, in FIG. 4, a block 31 is a memory circuit for changing the order of data, and a block 32.
Is a write address generation circuit that outputs an address when writing data to the memory. In this case, M
It is formed by a sequence generator. Further, the block 33 is a read address generating circuit which outputs an address when reading data from the memory.

The block 34 is an address generation control circuit for controlling the address generation of the write address generation circuit 32 and the calling address generation circuit 33 and the input / output of the memory circuit 31.

In the figure, reference numeral 41 is an input data signal to the memory, reference numeral 42 is an output data signal from the memory, reference numeral 51 is a write address signal representing an address when writing to the memory, and reference numeral 52 is read from the memory. This is a read address signal that represents the address at time.

In this circuit, in the method in which the order is changed at the write address, the value of the shift register constituting the M-series generator, which is a feature of the invention, is used as the write address, and the read address is the normal 4
The output of the bit binary counter. The synchronization of these counters and the M-sequence generator is performed by the synchronization signal in the transmission signal.

That is, the write address circuit 32 of FIG.
The address circuit using the M series (PN (x) = x ⁴ + x + 1) shown in FIG. 2 is used as the address circuit for reading the interleave. Therefore, the order of write addresses is as follows. Write address: 0,8,3,6,12,11,5,10,7,14,15,13,
9,1,2,4

As a result, the input data is recorded in the memory circuit 31 shown in FIG. However, in this case, since the order of the write addresses is the same as the order in which the interleaver of FIG. 1 replaces it, the order of the written data is eventually returned to the original order.

On the other hand, the read address circuit 33 shown in FIG.
For this, the normal 4-bit binary counter shown in FIG. 7 is used. Therefore, the order of read addresses is as follows. Read address: 0,1,2,3,4,5,6,7,8,9,10,11,12,1
3,14,15 As a result, the data input to the memory circuit 31 of FIG. 4 is output in order according to the read address.

Further, the effects of the interleaver and the deinterleaver by these operations will be described below.

That is, the communication transmission path 104 of FIG. 5 described above.
Then, it is assumed that a burst-like error (*) occurs in the first 4 bits 0, 1, 2, 3 of the data string. Error data sequence: *, *, *, *, 12,11,5,10,7,14,15,
13,3,1,2,4

In this case, however, the deinterleaver stores the first 4 bits 0, 1, 2, 3 at the addresses 0, 8, 3, 6 and outputs them without changing the order when reading. At the time of input to the error correction decoder 122 of FIG. 5, each bit of 0, 3, 6, and 8 is incorrect. Output data string: *, 1,2, *, 4,5, *, 7, *, 9,10,11,12,
13,14,15

Therefore, in this apparatus, errors generated in bursts are dispersed by the effect of the interleaver and the deinterleaver, and the error correction decoding in the error correction decoder 122 effectively functions. Also, in this case, it can be seen that the periodicity as in the conventional case is eliminated, which is more effective for the error correction technique.

Further, in this apparatus, it is assumed that a periodic error occurs due to Rayleigh fading or the like on the communication transmission line 104 in FIG. 5, and for example, an error periodically occurs in every 4 bits in the data string. Error data sequence: *, 8,3,6, *, 11,5,10, *, 14,15,1
3, *, 1,2,4

In this case, in the deinterleaver, the four bits 0, 4, 8, 12 in which an error has occurred are 0, 12, 7,
It is stored in the address 9 and is read out and output without changing the order. Output data string: *, 1,2,3,4,5,6, *, 8, *, 10,11, *, 1
3,14,15

Therefore, in this case, the periodically generated errors are also dispersed without being continuous, and as a result, the error correction decoding in the error correction decoder 122 can be effectively operated.

Therefore, in this device, when the order of data is changed using the memory circuit, the write address or the read address is given the periodicity by using the value of each register constituting the M-sequence generator. You can change the order of data without
It is possible to disperse data errors and eliminate the periodicity at the error location.

As a result, with respect to the error position of the deinterleaved data having the periodicity in the past, or the error having the periodicity due to Rayleigh fading or the like, on the contrary, the error is not dispersed but becomes a continuous error. According to the present invention, there is no possibility of continuous errors after deinterleaving what was possible, and the ability of the error correction code can be effectively used.

Further, according to the present invention, since the data is interleaved by the M sequence, the data to be transmitted does not have periodicity, and complicated data replacement is performed. It has a high effect.

Further, according to the present invention, the M-series address generator has an effect that the circuit scale is smaller than that of the conventional address generator using a counter.

Thus, according to the interleave device, the encoding device, the deinterleave device, the decoding device, and the transmission method described above, the storage means for temporarily saving the data and the write address for writing the data in the storage device. A write address generating means for generating a signal, a read address generating means for generating a read address signal for reading data from the storage device, and an address generation control means for controlling generation of the write address signal and the read address signal. It is provided with an M-sequence generating means, and by interleaving or deinterleaving data by the M-sequence from the generating means at every predetermined interleaving cycle, it is possible to change the order of data without imparting periodicity. Disperse data errors, and Rino can be eliminated periodicity in position, even for errors that periodicity, prevents an error continuously after deinterleaving, in which it is possible to effectively utilize the capability of the error correcting code.

In the above-described embodiment, a method has been described in which the interleaver changes the order when reading, and the deinterleaver changes the order when writing. However, in contrast, the interleaver changes the order when writing and deinterleaves. The same method can be applied to the method in which the reaver is used to switch the order when reading.

In the above embodiment, the counter and M
The number of bits of the sequence generator is 4 and the number of addresses is 16, but this is simplified for explanation.
Actually, it is implemented with a larger number of bits.
Also, various types of circuits can be applied to the type of the M-sequence generator used.

By using the interleaving device and the deinterleaving device of the above-described embodiments, a good coding device and decoding device can be formed, and by using these coding device and decoding device, A good transmission method (wireless communication system) can be configured.

[0071]

As described above, according to the present invention, when the order of data is exchanged by using the memory circuit, the value of each register constituting the M-sequence generator is used for the write address or the read address, so that the cycle It has become possible to change the order of the data without imparting the property, to disperse the data error and to eliminate the periodicity at the error position.

As a result, with respect to the error position of the deinterleaved data having the periodicity in the past or the periodical error due to the Rayleigh fading or the like, on the contrary, the error is not dispersed but becomes a continuous error. According to the present invention, there is no possibility that errors will continue after deinterleaving, and it is possible to effectively use the capability of the error correction code.

Further, according to the present invention, since the data is interleaved by the M sequence, the transmitted data does not have periodicity, and complicated data replacement is performed. It has a high effect.

Further, according to the present invention, the M-series address generator has an effect that the circuit scale is smaller than that of the conventional address generator using a counter.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of an interleave device to which the present invention is applied.

FIG. 2 is a block diagram showing a configuration of an example of an M-sequence generator.

FIG. 3 is a diagram for explaining the operation.

FIG. 4 is a block diagram showing an example of a deinterleave device to which the present invention has been applied.

FIG. 5 is a block diagram of a communication system using error correction.

FIG. 6 is a block diagram of a conventional interleaver and deinterleaver.

FIG. 7 is a circuit diagram of a 4-bit binary counter.

FIG. 8 is a circuit diagram of a 4-bit binary counter in which upper and lower bits of output bits are exchanged.

[Explanation of symbols]

 1 Memory Circuit 2 Write Address Generation Circuit 3 Read Address Generation Circuit (M Series Generator) 4 Address Generation Control Circuit 11 Input Data Signal 12 Output Data Signal 21 Write Address Signal 22 Read Address Signal

Claims (9)

[Claims] 1. Storage means for temporarily saving data, write address generation means for generating a write address signal for writing the data to the storage device, and reading the data from the storage device. A read address generating means for generating a read address signal, an address generation control means for controlling the generation of the write address signal and the read address signal, and an M series generating means are provided for each predetermined interleaving cycle. To M from the above generating means
An interleaving device, which interleaves the above data according to a sequence. 2. The interleave device according to claim 1, further comprising write address generating means for generating a write address signal for writing the data in the storage device using the M series from the generating means. Characteristic interleave device. 3. The interleave device according to claim 1, further comprising read address generating means for generating a read address signal for reading the data from the storage device using the M series from the generating means. Characteristic interleave device. 4. Storage means for temporarily saving data, write address generation means for generating a write address signal for writing the data to the storage device, and reading the data from the storage device. A read address generating means for generating a read address signal, an address generation control means for controlling the generation of the write address signal and the read address signal, and an M series generating means are provided for each predetermined interleaving cycle. To M from the above generating means
An encoding device comprising an interleaving device that interleaves the above-mentioned data by a sequence. 5. Storage means for temporarily saving data, write address generation means for generating a write address signal for writing the data to the storage device, and reading the data from the storage device. A read address generating means for generating a read address signal, an address generation control means for controlling the generation of the write address signal and the read address signal, and an M series generating means are provided for each predetermined interleaving cycle. To M from the above generating means
A deinterleaving device that deinterleaves the above-mentioned data according to a sequence. 6. The deinterleave device according to claim 5, further comprising write address generating means for generating a write address signal for writing the data in the storage device using the M series from the generating means. Deinterleaving device. 7. The deinterleave device according to claim 5, further comprising read address generating means for generating a read address signal for reading the data from the storage device, using the M series from the generating means. Deinterleaving device. 8. Storage means for temporarily saving data, write address generation means for generating a write address signal for writing the data to the storage device, and reading the data from the storage device. A read address generating means for generating a read address signal, an address generation control means for controlling the generation of the write address signal and the read address signal, and an M series generating means are provided for each predetermined interleaving cycle. To M from the above generating means
A decoding device comprising a deinterleaving device that deinterleaves the above-mentioned data according to a sequence. 9. Storage means for temporarily saving data, write address generation means for generating a write address signal for writing the data to the storage device, and reading the data from the storage device. A read address generating means for generating a read address signal, an address generation control means for controlling the generation of the write address signal and the read address signal, and an M series generating means are provided for each predetermined interleaving cycle. To M from the above generating means
Encoding device equipped with an interleaving device for interleaving the data by a series, storage means for temporarily saving the data, and write address generation for generating a write address signal for writing the data in the storage device. Means, read address generating means for generating a read address signal for reading the data from the storage device, and address generation control means for controlling generation of the write address signal and the read address signal, M Sequence generating means, and M from the generating means for each predetermined interleaving cycle
And a decoding device having a deinterleaving device that deinterleaves the above-mentioned data according to a sequence.