JPH09116042A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09116042A JPH09116042A JP7275817A JP27581795A JPH09116042A JP H09116042 A JPH09116042 A JP H09116042A JP 7275817 A JP7275817 A JP 7275817A JP 27581795 A JP27581795 A JP 27581795A JP H09116042 A JPH09116042 A JP H09116042A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- semiconductor device
- semiconductor
- metal wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の構造
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a semiconductor device.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
特開平１−１９１４５３号公報、特開平４−８４４５２
号公報、特開平６−２０９０５５号公報に開示されるも
のがあり、以下図４を参考にして説明する。図４はかか
る従来の半導体装置の断面図である。2. Description of the Related Art Conventionally, techniques in such a field include:
JP-A-1-191453 and JP-A-4-84452
JP-A-6-209055 and JP-A-6-209055, which will be described below with reference to FIG. FIG. 4 is a sectional view of such a conventional semiconductor device.
【０００３】この図において、半導体素子２１の電極２
２に接続用のＡｕ等のバンプ２３が形成され、ポリイミ
ドテープ２４上に形成された導体パターン２５に接続さ
れていた。さらに、半導体素子２１のまわりを封止用枠
２６で囲い、その内部を樹脂２７で封止し、必要な部分
に外部導出用電極として、金や、半田等のボール２８を
リフロー等で形成していた。In this figure, the electrode 2 of the semiconductor element 21 is shown.
Bumps 23 made of Au or the like for connection were formed on No. 2 and were connected to the conductor pattern 25 formed on the polyimide tape 24. Further, the semiconductor element 21 is surrounded by a sealing frame 26, the inside thereof is sealed with a resin 27, and a ball 28 of gold or solder is formed by reflow or the like as an external lead electrode at a necessary portion. Was there.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、上記し
たような従来の半導体装置の構造では、 （１）半導体素子２１上の電極２２と導体パターン２５
の接続部に応力がかかり、断線が発生する。 （２）ポリイミドテープ２４の吸湿量が多いため、基板
実装時のリフロー熱ストレスで、クラックが発生する。However, in the structure of the conventional semiconductor device as described above, (1) the electrode 22 on the semiconductor element 21 and the conductor pattern 25 are formed.
A stress is applied to the connection part of and the disconnection occurs. (2) Since the polyimide tape 24 has a large moisture absorption amount, a crack occurs due to the reflow heat stress during mounting on the substrate.
【０００５】（３）外部導出用ボール２８を形成する
際、リフロー等の熱ストレスが加わるため、耐湿性等の
信頼性が低下する。 （４）半導体素子２１上にバンプ２３を形成するため、
専用設計が必要であり、汎用性に乏しい。 という問題があった。(3) Since thermal stress such as reflow is applied when the external lead-out ball 28 is formed, reliability such as moisture resistance is deteriorated. (4) Since the bumps 23 are formed on the semiconductor element 21,
It needs a special design and lacks versatility. There was a problem.
【０００６】本発明は、上記問題点を除去し、半導体素
子の発熱や外部の環境による熱的ストレスに対して強い
半導体装置を提供することを目的とする。It is an object of the present invention to eliminate the above-mentioned problems and to provide a semiconductor device which is resistant to heat generation of a semiconductor element and thermal stress due to the external environment.
【０００７】[0007]
【課題を解決するための手段】本発明は、上記目的を達
成するために、 〔１〕半導体装置において、半導体素子（１）上に予め
半田ボール（４）を形成した基板（３）を、接着層
（２）を介して接着し、前記半導体素子（１）と基板
（３）とを金属線（８）で接続後、封止用枠（５）を設
けて、内部を樹脂（９）で封止するようにしたものであ
る。In order to achieve the above object, the present invention provides: [1] In a semiconductor device, a substrate (3) having a solder ball (4) preliminarily formed on a semiconductor element (1), The semiconductor element (1) and the substrate (3) are bonded together via an adhesive layer (2) and connected to each other by a metal wire (8), then a sealing frame (5) is provided, and the inside is made of a resin (9). It is designed to be sealed with.
【０００８】このように、半導体素子（１）上に接着層
（２）を介し基板（３）を接着し、半導体素子（１）の
電極（６）と基板（３）の導体（７）を金属線（８）で
接続するようにしたので、半導体素子（１）の発熱や外
部の環境による熱的ストレスに対して半導体装置を非常
に強くすることができ、例えば、温度サイクル試験にお
いては１０００サイクル以上を達成できる。In this way, the substrate (3) is adhered to the semiconductor element (1) via the adhesive layer (2), and the electrode (6) of the semiconductor element (1) and the conductor (7) of the substrate (3) are attached. Since the connection is made with the metal wire (8), the semiconductor device can be made extremely strong against the heat generation of the semiconductor element (1) and the thermal stress due to the external environment. Can achieve more than cycles.
【０００９】また、半導体素子（１）には特別な処理が
必要でないため、標準素子を利用でき、新たな設計や改
良、あるいはバンプ付け等が不要であり、汎用性が大き
い。更に、予め基板（３）上に半田ボール（４）を形成
しているため、半田ボール（４）形成時の熱ストレスを
なくすことができ、信頼性が向上する。また、基板
（３）にセラミックや低吸湿プラスチックを使用するこ
とにより、耐リフロー性を向上させることができる。Further, since the semiconductor element (1) does not require any special treatment, standard elements can be used, and new design, improvement, bumping, etc. are unnecessary, and the versatility is great. Further, since the solder balls (4) are formed on the substrate (3) in advance, thermal stress at the time of forming the solder balls (4) can be eliminated and reliability is improved. Further, by using a ceramic or a low hygroscopic plastic for the substrate (3), reflow resistance can be improved.
【００１０】〔２〕半導体装置において、半導体素子
（１）上に予め半田ボール（４）を形成した基板（３）
を接着層（２）を介して接着し、前記半導体素子（１）
と基板（３）とを金属線（８）で接続後、封止用枠
（５）を設けて、キャップ（１０）を前記封止用枠
（５）と基板（３）に接合し、内部を中空にするように
したものである。[2] In a semiconductor device, a substrate (3) in which solder balls (4) are previously formed on a semiconductor element (1)
Are bonded via an adhesive layer (2), and the semiconductor element (1)
After connecting the substrate and the substrate (3) with a metal wire (8), a sealing frame (5) is provided, and the cap (10) is joined to the sealing frame (5) and the substrate (3). Is made hollow.
【００１１】このように、内部を中空構造としたので内
部接続の信頼性を格段に向上させることができる。 〔３〕半導体装置において、半導体素子（１）上に予め
半田ボール（２）を形成した基板（３）を接着層（２）
を介して接着し、前記半導体素子（１）と基板（３）と
を金属線（８）で接続後、封止用枠（５）を設けて、内
部に熱伝導性のエポキシ樹脂（１１）を充填し、さらに
キャップ（１０）に半田ボール（１２）を形成するよう
にしたものである。As described above, since the inside has a hollow structure, the reliability of the internal connection can be remarkably improved. [3] In a semiconductor device, a substrate (3) having solder balls (2) formed on a semiconductor element (1) in advance is attached to an adhesive layer (2).
The semiconductor element (1) and the substrate (3) are bonded to each other with a metal wire (8), then a sealing frame (5) is provided, and a thermally conductive epoxy resin (11) is provided inside. And solder balls (12) are formed on the cap (10).
【００１２】このように、上記〔２〕に加えて、内部に
熱伝導性のエポキシ樹脂（１１）を充填し、かつキャッ
プ（１０）上へ半田ボール（１２）を設けるようにした
ので、マザーボードへ実装後、放熱性が向上し、したが
って、熱的歪みが減少し、内部接続の信頼性が向上す
る。かつ、半導体装置とマザーボードとの接続の信頼性
の向上が期待できる。As described above, in addition to the above [2], the thermally conductive epoxy resin (11) is filled inside and the solder balls (12) are provided on the cap (10). After mounting, heat dissipation is improved, and therefore thermal distortion is reduced, and reliability of internal connection is improved. In addition, the reliability of the connection between the semiconductor device and the motherboard can be expected to improve.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら説明する。図１は本発明の実施例
を示す半導体装置の断面図である。この図に示すよう
に、半導体素子１上に熱硬化あるいは熱可塑性の接着層
２を介し予め必要なパターンを形成し、かつ一方の面に
半田ボール４を形成した半導体素子１より、０．５〜
２．０ｍｍ程度小さいガラスエポキシ等のプラスチッ
ク、あるいはセラミックからなる基板３が固着されてい
る。半導体素子１の周囲には、搬送あるいは封止用枠５
が取り付けられ、半導体素子１上の電極６と基板３上の
導体７を金属線８で結線している。さらに金属線８を覆
うように樹脂９にて封止されている。Embodiments of the present invention will be described below with reference to the drawings. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention. As shown in this figure, the semiconductor element 1 in which a necessary pattern is formed in advance on the semiconductor element 1 via the thermosetting or thermoplastic adhesive layer 2 and the solder balls 4 are formed on one surface is ~
A substrate 3 made of plastic such as glass epoxy or ceramics, which is small by about 2.0 mm, or ceramic is fixed. A frame 5 for transportation or sealing is provided around the semiconductor element 1.
Are attached, and the electrodes 6 on the semiconductor element 1 and the conductors 7 on the substrate 3 are connected by metal wires 8. Further, it is sealed with a resin 9 so as to cover the metal wire 8.
【００１４】このように構成したので、マザーボードに
リフロー（ＩＲ、ＶＰＳ、エアー等）で半田接続後、動
作させると、半田ボール４、基板３、金属線８を介して
半導体素子１に入出力が行われる。この時、半導体素子
１は発熱し、熱的な歪みが発生する。あるいは外部の環
境により、熱的、機械的歪みが発生するが、基板３、接
着層２が緩衝剤となり、また、基板３と半導体素子１の
接続を金属線８で行っているので、半導体素子１と金属
線８の接続部へのストレスが最小限で済むようになる。With this structure, when soldering is performed on the mother board by reflow (IR, VPS, air, etc.) and then it is operated, input / output to / from the semiconductor element 1 via the solder balls 4, the substrate 3, and the metal wires 8 is performed. Done. At this time, the semiconductor element 1 generates heat and thermal distortion occurs. Alternatively, although thermal and mechanical strains occur due to the external environment, the substrate 3 and the adhesive layer 2 serve as a buffering agent, and since the substrate 3 and the semiconductor element 1 are connected by the metal wire 8, the semiconductor element is The stress on the connection between the metal wire 1 and the metal wire 8 can be minimized.
【００１５】また、基板３を多層構成にすることによ
り、電源電圧の変動等に対して強くすることができる。
次に、本発明の第２実施例について説明する。図２は本
発明の第２実施例を示す半導体装置の断面図である。こ
の図に示すように、半導体素子１上に接着層２を介して
基板３を接着し、封止用枠５を設け、半導体素子１上の
電極６と基板３上の導体７を金属線８で接続する。ここ
までは第１実施例と同様である。Further, by forming the substrate 3 in a multi-layered structure, it is possible to make it resistant to fluctuations in the power supply voltage and the like.
Next, a second embodiment of the present invention will be described. FIG. 2 is a sectional view of a semiconductor device showing a second embodiment of the present invention. As shown in this figure, the substrate 3 is bonded onto the semiconductor element 1 via the adhesive layer 2, the sealing frame 5 is provided, and the electrode 6 on the semiconductor element 1 and the conductor 7 on the substrate 3 are connected to the metal wire 8. Connect with. The operation up to this point is the same as in the first embodiment.
【００１６】その後、予め所定の形状に加工した、プラ
スチックあるいは金属製のキャップ１０が封止用枠５と
基板３に接合層を介し接合されている。このように構成
したので、第１実施例と同様に、マザーボードに実装
後、電源をＯＮすると熱的歪みが発生するが、半導体装
置内部は中空構造となっているため、半導体素子１上の
電極６と金属線８との接続部、および基板３上の導体７
と金属線８の接続部にはストレスが加わらず、接続信頼
性が良くなる。Thereafter, a plastic or metal cap 10 which has been processed into a predetermined shape in advance is bonded to the sealing frame 5 and the substrate 3 via a bonding layer. With this configuration, as in the first embodiment, thermal distortion occurs when the power is turned on after mounting on the mother board, but since the semiconductor device has a hollow structure, the electrodes on the semiconductor element 1 are formed. 6 and the metal wire 8 and the conductor 7 on the substrate 3
No stress is applied to the connection portion between the metal wire 8 and the metal wire 8 and the connection reliability is improved.
【００１７】次に、本発明の第３実施例について説明す
る。図３は本発明の第３実施例を示す半導体装置の断面
図である。ここで、第１と第２実施例と同じ部分には、
同じ番号を付してその説明は省略する。この実施例は、
図３に示すように、上記第２実施例に加えて、内部に熱
伝導性のエポキシ樹脂１１を充填し、かつ金属性あるい
はプラスチック性のキャップ１０の上に半田ボール１２
が設けられている。Next, a third embodiment of the present invention will be described. FIG. 3 is a sectional view of a semiconductor device showing a third embodiment of the present invention. Here, the same parts as in the first and second embodiments include
The same numbers are assigned and the description is omitted. This example is
As shown in FIG. 3, in addition to the second embodiment, a thermally conductive epoxy resin 11 is filled inside and a solder ball 12 is placed on a metallic or plastic cap 10.
Is provided.
【００１８】このように構成したので、第１及び第２実
施例と同様に、マザーボードに搭載後、電源をＯＮする
と、半導体素子１が発熱し、熱的な歪みが発生するが、
内部を熱伝導性のエポキシ樹脂１１で充填し、かつキャ
ップ１０の上に半田ボール１２を形成しているので、熱
が、熱伝導性のエポキシ樹脂１１、キャップ１０から半
田ボール１２を通してマザーボードへ放熱されるため、
熱的歪みを小さくすることができる。With this structure, as in the first and second embodiments, when the power is turned on after mounting on the mother board, the semiconductor element 1 generates heat and thermal distortion occurs.
Since the inside is filled with the thermally conductive epoxy resin 11 and the solder balls 12 are formed on the cap 10, heat is radiated from the thermally conductive epoxy resin 11 and the cap 10 to the motherboard through the solder balls 12. Because
Thermal distortion can be reduced.
【００１９】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。It should be noted that the present invention is not limited to the above embodiment, but various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
【００２０】[0020]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、以下のような効果を奏することができる。 （１）請求項１記載の発明によれば、半導体素子上に接
着層を介し基板を接着し、半導体素子上の電極と基板の
導体を、金属線で接続するようにしたので、半導体素子
の発熱や外部の環境による熱的ストレスに対して半導体
装置を非常に強くすることができ、例えば、温度サイク
ル試験においては、１０００サイクル以上を達成でき
る。As described above, according to the present invention, the following effects can be obtained. (1) According to the first aspect of the invention, the substrate is adhered on the semiconductor element via the adhesive layer, and the electrode on the semiconductor element and the conductor of the substrate are connected by a metal wire. The semiconductor device can be made very strong against heat generation and thermal stress due to the external environment, and for example, 1000 cycles or more can be achieved in a temperature cycle test.
【００２１】また、半導体素子には特別な処理が必要で
ないため、標準素子を利用でき、新たな設計や改良、あ
るいはバンプ付け等が不要であり、汎用性が大きい。更
に、予め基板上に半田ボールを形成しているため、ボー
ル形成時の熱ストレスをなくすことができ、信頼性が向
上する。更に、基板にセラミックや低吸湿プラスチック
を使用することにより、耐リフロー性を向上させること
ができる。 （２）請求項２記載の発明によれば、内部を中空構造と
したので、内部接続の信頼性を格段に向上させることが
できる。Further, since the semiconductor element does not require any special treatment, the standard element can be used, and new design, improvement, bumping, etc. are not required, and the versatility is great. Further, since solder balls are formed on the substrate in advance, thermal stress at the time of ball formation can be eliminated, and reliability is improved. Furthermore, the reflow resistance can be improved by using ceramic or low moisture absorption plastic for the substrate. (2) According to the second aspect of the invention, since the inside has a hollow structure, the reliability of the internal connection can be significantly improved.
【００２２】（３）請求項３記載の発明によれば、上記
（２）に加えて、内部に熱伝導性のエポキシ樹脂を充填
し、かつキャップ上へ半田ボールを設けるようにしたの
で、マザーボードへ実装後、放熱性が向上する。したが
って、熱的歪みが減少し、内部接続の信頼性が向上す
る。かつ半導体装置とマザーボードとの接続の信頼性の
向上が期待できる。(3) According to the third aspect of the present invention, in addition to the above (2), the interior is filled with a thermally conductive epoxy resin, and solder balls are provided on the cap. After mounting, heat dissipation is improved. Therefore, thermal distortion is reduced and reliability of the internal connection is improved. In addition, the reliability of the connection between the semiconductor device and the motherboard can be expected to improve.
【図１】本発明の実施例を示す半導体装置の断面図であ
る。FIG. 1 is a sectional view of a semiconductor device showing an embodiment of the present invention.
【図２】本発明の第２実施例を示す半導体装置の断面図
である。FIG. 2 is a sectional view of a semiconductor device showing a second embodiment of the present invention.
【図３】本発明の第３実施例を示す半導体装置の断面図
である。FIG. 3 is a sectional view of a semiconductor device showing a third embodiment of the present invention.
【図４】従来の半導体装置の断面図である。FIG. 4 is a cross-sectional view of a conventional semiconductor device.
１ 半導体素子 ２ 接着層 ３ 基板 ４，１２ 半田ボール ５ 封止用枠 ６ 半導体素子の電極 ７ 基板の導体 ８ 金属線 ９ 樹脂 １０ キャップ １１ 熱伝導性のエポキシ樹脂 1 Semiconductor Element 2 Adhesive Layer 3 Substrate 4,12 Solder Ball 5 Sealing Frame 6 Semiconductor Element Electrode 7 Substrate Conductor 8 Metal Wire 9 Resin 10 Cap 11 Heat Conductive Epoxy Resin
Claims (3)
め半田ボールを形成した基板を接着層を介して接着し、
前記半導体素子と基板とを金属線で接続後、封止用枠を
設けて、内部を樹脂で封止することを特徴とする半導体
装置。1. In a semiconductor device, a substrate having solder balls formed in advance on a semiconductor element is bonded via an adhesive layer,
After connecting the semiconductor element and the substrate with a metal wire, a sealing frame is provided and the inside is sealed with a resin.
め半田ボールを形成した基板を接着層を介して接着し、
前記半導体素子と基板とを金属線で接続後、封止用枠を
設けて、キャップを前記封止用枠と基板に接合し、内部
を中空としたことを特徴とする半導体装置。2. In a semiconductor device, a substrate having solder balls formed in advance on a semiconductor element is bonded via an adhesive layer,
After connecting the semiconductor element and the substrate with a metal wire, a sealing frame is provided, a cap is joined to the sealing frame and the substrate, and the inside is made hollow.
め半田ボールを形成した基板を接着層を介して接着し、
前記半導体素子と基板とを金属線で接続後、封止用枠を
設けて、内部に熱伝導性のエポキシ樹脂を充填し、さら
にキャップに半田ボールを形成したことを特徴とする半
導体装置。3. In a semiconductor device, a substrate having solder balls formed in advance on a semiconductor element is bonded via an adhesive layer,
After connecting the semiconductor element and the substrate with a metal wire, a sealing frame is provided, a thermally conductive epoxy resin is filled inside, and a solder ball is formed on the cap.
Priority Applications (13)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7275817A JPH09116042A (en) | 1995-10-24 | 1995-10-24 | Semiconductor device |
| KR1019960047703A KR100386061B1 (en) | 1995-10-24 | 1996-10-23 | Semiconductor device and lead frame with improved construction to prevent cracking |
| EP00110728A EP1039540A1 (en) | 1995-10-24 | 1996-10-24 | Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same |
| EP96117092A EP0771029A3 (en) | 1995-10-24 | 1996-10-24 | Semiconductor device having an improved structure for preventing cracks, and method of manufacturing the same |
| EP01122146A EP1168440A1 (en) | 1995-10-24 | 1996-10-24 | Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same |
| EP00110729A EP1039541A1 (en) | 1995-10-24 | 1996-10-24 | Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same |
| US08/736,610 US5864174A (en) | 1995-10-24 | 1996-10-24 | Semiconductor device having a die pad structure for preventing cracks in a molding resin |
| EP00110727A EP1039538A1 (en) | 1995-10-24 | 1996-10-24 | Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same |
| TW085113467A TW350106B (en) | 1995-10-24 | 1996-11-04 | Semiconductor elements and the manufacturing method |
| TW087102088A TW411533B (en) | 1995-10-24 | 1996-11-04 | Semiconductor device and its manufacturing method |
| US09/165,295 US6177725B1 (en) | 1995-10-24 | 1998-10-02 | Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same |
| US09/695,403 US6459145B1 (en) | 1995-10-24 | 2000-10-25 | Semiconductor device having an improved structure for preventing cracks, and improved small-sized semiconductor |
| US10/223,484 US6569755B2 (en) | 1995-10-24 | 2002-08-20 | Semiconductor device having an improved structure for preventing cracks, improved small sized semiconductor and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7275817A JPH09116042A (en) | 1995-10-24 | 1995-10-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09116042A true JPH09116042A (en) | 1997-05-02 |
Family
ID=17560845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7275817A Withdrawn JPH09116042A (en) | 1995-10-24 | 1995-10-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09116042A (en) |
-
1995
- 1995-10-24 JP JP7275817A patent/JPH09116042A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20030107 |