JPH09107086A - Non-voltatile semiconductor memory and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a thick intergate-interlayer film by forming an upper layer silicon oxide film of the intergate-interlayer film and a gate insulating film of an MISFET for a peripheral circuit in the same process in different thickness utilizing the difference of growth of a silicon oxide film depending on the foundation. SOLUTION: The thickness of a silicon oxide film 6c formed on a silicon nitride film 6b through thermal oxidation in a dry or a wet atmosphere scarcely changes. Thus, an insulating film (ONO film), consisting of a silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c formed in this order from the bottom, can be formed as an intergate-interlayer 6 of a memory cell MC in a state wherein the silicon oxide film 6c is made sufficiently thin, and at the same time, a gate insulating film of s MOSFETQr for use in a read-out circuit can be formed in the same process with the thickness thereof being made different from that of the silicon oxide film 6c. As a result, respective thickness with optimum values can be achieved without increasing the processes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to an inter-gate interlayer film between a floating gate electrode and a control gate electrode of a non-volatile semiconductor memory device and a gate insulating film of a peripheral transistor section. The present invention relates to a technique effective when applied to formation.

[0002]

2. Description of the Related Art A semiconductor memory device has a volatile semiconductor memory device that retains recorded information only while power is supplied, and a semiconductor memory device that retains recorded information even when power is disconnected. There is a nonvolatile semiconductor memory device that can be used.

As a nonvolatile semiconductor memory device, an EEPROM (Electr
There is a wise Erasable Programable Read Only Memory).

A memory cell, which is a memory element of such a nonvolatile semiconductor memory device, has a floating gate electrode provided on a channel region of a semiconductor substrate via a gate insulating film, and an inter-gate interlayer film provided on the floating gate electrode. Therefore, a control gate electrode is provided. In such a configuration, depending on the presence / absence of electrons in the floating gate electrode, that is, whether or not electrons are stored in the floating gate electrode, the control gate electrode is provided with the channel region interposed therebetween when a voltage is applied. The threshold voltage at which conduction between the source region and the drain region occurs changes. Using this change, information is stored by injecting electrons into the floating gate electrode. For example, the state where electrons are present in the floating gate electrode is set to "0", and the state where electrons are not present in the floating gate electrode is set. The presence or absence of information is determined as 1 ".

In the nonvolatile memory element having such a floating gate electrode, in order to prevent the information on the floating gate electrode from being lost due to the leakage of electrons from the floating gate electrode to the control gate electrode, It is desirable that the inter-gate interlayer film between the control gate electrode and the control gate electrode be a laminated film (ONO film) in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated. In order to prevent scraping due to cleaning in the intermediate step, a 4-layer laminated film (ONON film) in which a silicon nitride film is further laminated on an upper silicon oxide film is used.

[0006]

In the information writing operation of the non-volatile memory element, for example, 12 V (writing voltage) is applied to the control gate electrode, 6 V is applied to the drain region, and 0 V is applied to the source region, and hot electrons are applied to the floating gate electrode. Is done by injecting. In such injection, when the write voltage is applied to the control gate electrode, the higher the potential of the floating gate electrode is, the easier the injection of electrons into the floating gate electrode occurs, and the information writing characteristic is improved. In this information writing operation, the potential Vfg of the floating gate electrode is expressed by the following equation.

[0007]

(Equation 1)

Generally, Cd (capacitance between floating gate and drain) is sufficiently smaller than C1 (capacitance between floating gate and control gate), and the charge Q = 0 of the floating gate electrode at the initial stage of writing.
It has become. Therefore, the above equation is approximately represented by the following equation.

[0009]

(Equation 2)

From this equation, in order to improve the writing characteristics by injecting more electrons, Vfg may be increased, and in order to increase Vfg, the capacitance C between the floating gate electrode and the control gate electrode may be increased.
It can be seen that it is sufficient to increase 1 or the write voltage Vg. However, the write voltage Vg is determined by the standard and cannot be increased in the present situation where it is required to be lowered according to the voltage of the entire circuit. Therefore, in order to raise the potential Vfg of the floating gate electrode, the floating voltage is required. It is necessary to increase the capacitance C1 between the gate electrode and the control gate electrode. The capacitance C1 between the floating gate electrode and the control gate electrode is expressed by the following equation.

[0011]

(Equation 3)

In order to increase C1 from this equation, the relative dielectric constant of the inter-gate interlayer film between the floating gate electrode and the control gate electrode is increased by increasing the area S of the overlapping portion of the floating gate electrode and the control gate electrode. It is necessary to increase the ratio ε _OX or reduce the film thickness T _OX of the gate sensitive interlayer film between the floating gate electrode and the control gate electrode. However, increasing the area S becomes an obstacle to miniaturization because the cell size increases, and in order to increase the relative dielectric constant ε _OX of the inter-gate interlayer film between the floating gate electrode and the control gate electrode, the inter-gate The structure of the interlayer film has to be changed, and at present, a structure having the same function as that of the inter-gate interlayer film and having a high relative dielectric constant has not been put into practical use. Therefore, in order to increase the capacitance C1, it is necessary to reduce the thickness T _OX of the interlayer film between the floating gate electrode and the control gate electrode.

In the erasing operation of information, for example, 0 V is applied to the control gate electrode and 12 V (erase voltage) is applied to the source region, and the electrons of the floating gate electrode are applied to the source region by tunneling the electrons through the gate insulating film. It is done by pulling out. In such an erase operation, the potential Vf of the floating gate electrode is
The lower g is, the larger the potential difference between the floating gate electrode and the source region is, the more easily electrons are extracted from the floating gate electrode, and the information erasing characteristics are improved. In the information erased state, the potential Vfg of the floating gate electrode is expressed by the following equation.

[0014]

(Equation 4)

In order to improve the erase characteristic from this equation,
It can be seen that in order to lower the potential Vfg of the floating gate electrode, it is effective to reduce the ratio of the capacitance Cs between the floating gate and the source. When the capacitance C1 between the floating gate electrode and the control gate electrode is increased, the ratio of the capacitance Cs between the floating gate electrode and the source region becomes relatively small. Therefore, by reducing the film thickness T _{ox of the} inter-gate interlayer film between the floating gate electrode and the control gate electrode, the capacitance C1 between the floating gate electrode and the control gate electrode is increased, and the erase characteristic is also improved. It will be.

Although the case where the information is written by hot electron injection and the information is erased by the electron tunneling has been described above, even when the information is written and erased by the electron tunneling, the inter-gate interlayer film is formed. Writing / erasing characteristics are improved by reducing the thickness T _OX .

Under these circumstances, various attempts have been made to reduce the thickness of the inter-gate interlayer film. For example,
As disclosed in Japanese Unexamined Patent Publication No. 4-858825, a method of using an ONO film as the inter-gate interlayer film has been considered. However, in this method, the gate oxide film in the peripheral transistor portion and the upper layer of the inter-gate interlayer film are formed. Since the silicon oxide film has the same film thickness, the film thickness of the gate oxide film in the peripheral transistor portion determines the film thickness of the silicon oxide film as the upper layer of the inter-gate interlayer film. The thickness of the upper silicon oxide film cannot be made sufficiently thin.

Further, as disclosed in Japanese Patent Laid-Open No. 6-232415, an inter-gate interlayer film is an ONO film,
A method of forming the upper silicon oxide film to have a large film thickness in advance in consideration of the decrease in the upper silicon oxide film is considered, but in consideration of the decrease in the film thickness due to an error in the etching rate,
Since the upper silicon oxide film must be thick, the upper silicon oxide film becomes thicker than necessary, and the inter-gate interlayer film cannot be sufficiently thinned.

In a semiconductor memory device having a floating gate electrode, a MISFET (Metal Insu) for a read circuit of a memory cell and a peripheral circuit (peripheral transistor portion).
The floating gate electrode of the memory cell and the gate electrode of the write circuit MISFET of the peripheral circuit are formed in the same process due to the difference in voltage applied when the lator semiconductor field effect transistor) and the write circuit MISFET are formed. , The control gate electrode of the memory cell and the gate electrode of the read circuit MISFET of the peripheral circuit are formed in the same step, and the read circuit M is formed.
The gate insulating film of the ISFET is formed by the step of forming the inter-gate interlayer film.

However, the MISF for the read circuit is
Since the required thickness is different between the ET gate insulating film and the inter-gate interlayer film, it is difficult to obtain the optimum thickness by the same process.

An object of the present invention is to solve such a problem, and by thinning the inter-gate interlayer film between the floating gate electrode and the control gate electrode, the characteristics of the element of the semiconductor memory device having the floating gate electrode. It is to provide a technology capable of improving.

Another object of the present invention is to provide a technique capable of forming the inter-gate interlayer film and the gate insulating film of the MISFET for the peripheral circuit to have optimum thicknesses.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0024]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the present invention, the inter-gate interlayer film between the floating gate electrode and the control gate electrode of the memory cell is an ONO film having a three-layer structure, and the difference in growth of the silicon oxide film due to the underlying layer is utilized. Since the upper silicon oxide film of the inter-gate interlayer film and the gate insulating film of the MISFET for the peripheral circuit are formed in the same process with different film thicknesses, it is possible to reduce the film thickness of the inter-gate interlayer film. Each film thickness can be formed to an optimum value without increasing the number of steps.

According to the above-mentioned means, since the film thickness of the inter-gate interlayer film is thin, the characteristics of writing and erasing information are improved, and even if the size of the memory cell is reduced, it is the same as the conventional one. It is possible to obtain the characteristics of.

The embodiments of the present invention will be described below.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0029]

FIG. 1 shows a nonvolatile semiconductor memory device N as an embodiment to which the present invention is applied.
FIG. 3 is a plan view showing a memory cell portion of an OR-type flash memory, and a portion surrounded by a broken line in the drawing is one memory cell unit. 2 is a vertical sectional view taken along line aa (row direction) in FIG. 1, and FIG. 3 is taken along line bb (column direction) in FIG. FIG.

In the figure, 1 is a semiconductor substrate made of p-type single crystal silicon, 2 is a field insulating film separating each element forming region, and 3 is an n-type semiconductor region (high concentration region 3a and high concentration region 3a). And a floating gate electrode 4 provided on the semiconductor substrate 1 via a gate insulating film (first gate insulating film) 5 and a gate on the floating gate electrode 4. A control gate electrode 7 is provided via an interlayer film (second gate insulating film) 6. The inter-gate interlayer film 6 is a laminated film (ONO film) in which a lower silicon oxide film 6a, a silicon nitride film 6b, and an upper silicon oxide film 6c are sequentially laminated. As shown in the figure, M which is a memory cell MC
ISFET (Metal Insulator Semiconductor Field Ef
The effect transistor is composed of a gate insulating film 5, a floating gate electrode 4, an inter-gate interlayer film 6, a control gate electrode 7, and an n-type semiconductor region 3.

A plurality of memory cells MC are provided in the row direction and the column direction, and the control gate electrodes 7 of the cells MC adjacent in the column direction integrally extend to form a word line WL and the column. The source regions 3 of the memory cells MC adjacent to each other in the direction are integrally extended to form a common source line SL, and the drain regions 3 of two memory cells MC adjacent to each other in the row direction are common. Each drain region 3 is connected to the data line DL extending in the row direction.

FIG. 4A is a diagram showing the configuration of a one-chip microcomputer in which the semiconductor memory device is mounted. CPU (Central Processor Un)
It is a non-volatile semiconductor memory device having a relatively large capacity for storing a program, such as an EPROM (Electric).
ally Programable Read Only Memory), an interrupt controller INTC (Interrupt Controller) that allows other programs to be executed in the middle of program execution, and connection with external peripheral devices to read data and transmit calculation results to the outside. I / O port I / O for performing, etc., a timer T for generating a timing signal for synchronizing each operation or measuring the passage of time, an A / D converter for converting an analog signal and a digital signal Various peripheral control functions such as A / D are integrated on one chip.

The flash memory according to the present embodiment is
By mounting the EPROM shown in FIG. 4A instead of the EPROM, a one-chip microcomputer equipped with the semiconductor memory device of the present invention shown in FIG. 4B is obtained. The computer can easily rewrite the data and programs stored in the ROM in the state where the board is mounted. Therefore, it is effective for evaluation before shifting to full-scale mass production, for trial production and for mass production start-up, and also for products for which specifications are frequently changed and products for small-quantity, high-mix production. .

Further, after the equipment is assembled, it is possible to perform tuning, specification change, software version upgrade and maintenance for each equipment.

A method of manufacturing the above-mentioned nonvolatile semiconductor memory device will be described step by step with reference to FIGS. 5 to 15 and 20 to 24.

The semiconductor memory device includes a memory cell MC that stores information and a peripheral circuit that writes or reads information. The MISFET Qw for the write circuit of the memory cell MC and the peripheral circuit and the MIS for the read circuit.
Since the applied voltage is different from that of the FET Qr, the floating gate electrode of the memory cell MC and the gate electrode of the write circuit MISFET Qw of the peripheral circuit are formed in the same step, and the control gate electrode of the memory cell MC and the read of the peripheral circuit are formed. The gate electrode of the circuit MISFET Qr is formed in the same step. Note that CP
U, controller INTC, I / O port I / O, A /
The MISFET forming the D converter A / D and the like has the same structure as the read circuit MISFET Qr.

In the following description, in each drawing, the memory cell M
C, the cross-sectional view in the column direction (word line direction) is shown in the upper stage, and the cross-sectional view in the row direction (data line direction) is shown in the lower stage for each of the MISFET Qr for the read circuit and the MISFET Qw for the write circuit.

First, each element forming region 2a is formed on the semiconductor substrate 1.
20 is provided (FIG. 20), a silicon oxide film to be the gate insulating film 5 of the memory cell MC and the gate insulating film 9 of the MISFET for the write circuit is formed on the main surface of the semiconductor substrate 1, and then the memory is formed. A polycrystalline silicon film 10 which will be the floating gate electrode 4 of the cell MC and the gate electrode of the write circuit MISFET is formed on the entire surface of the semiconductor substrate 1 (FIG. 5). The gate insulating film 5 is, for example, 10
It is formed of a silicon oxide film having a thickness of nm or less. The gate insulating film 9 is made thicker than the gate insulating film 5.
The gate insulating films 5 and 9 are formed of a thermal oxide film obtained by thermally oxidizing the semiconductor substrate 1. The polycrystalline silicon film 10 is formed by, for example, a CVD (Chemical Vapor Deposition) method.

Next, patterning of the floating gate electrode 4 in the data line direction and patterning of the gate electrode 11 of the write circuit MISFET Qw in the gate length direction are performed on the polycrystalline silicon film 10 by photolithography and etching. A polycrystalline silicon film 4a is formed on the formation region, and a polycrystalline silicon film 11a is formed on the read circuit MISFET formation region (FIG. 6). By this patterning, polycrystalline silicon film 4a extending in the row direction shown in FIG. 21 is formed. Further, this patterning defines the width of the floating gate electrode 4a in the column direction.

Next, the film thickness of 5 to 20 nm is formed on the surfaces of the polycrystalline silicon film 4a and the polycrystalline silicon film 11a by thermal oxidation in a dry atmosphere at 850 ° C. to 1000 ° C. or by a CVD method at 700 ° C. to 800 ° C. Silicon oxide film 6a
Is formed, and then a silicon nitride film 6b having a film thickness of 10 to 20 nm is deposited by a CVD method at 700 ° C. to 800 ° C., and a nitrogen atmosphere at 900 ° C. to 1000 ° C. is formed in order to fill the pinholes of the silicon nitride film 6b. And anneal (FIG. 7). Instead of this annealing, a silicon oxide film (not shown) may be formed by thermal oxidation in a wet or steam atmosphere at 900 ° C. to 1000 ° C. by thermal oxidation.

The silicon oxide film 6a preferably has a film thickness of 10 nm or more, that is, 10 nm to 20 nm, in order to prevent electrons from leaking from the floating gate electrode 4 to the control gate electrode 7. Since the silicon nitride film 6b has a higher dielectric constant than the silicon oxide film 6a, the dielectric constant of the inter-gate interlayer film 6 can be increased.

Next, a resist mask 1 exposing the read MISFET formation region by photolithography.
2 is formed, and the silicon nitride film 6b in the read MISFET formation region is removed by dry etching (FIG. 8).

Next, after the resist mask 12 is removed, cleaning with hydrofluoric acid is performed to read MISFET.
The silicon oxide film 6a and the gate insulating film 9 in the formation region are removed to expose the main surface of the semiconductor substrate 1 in the read MISFET formation region. When a silicon oxide film (not shown) is formed by thermal oxidation on the silicon nitride film 6b of the inter-gate interlayer film 6, this silicon oxide film is also removed by this hydrofluoric acid cleaning. Subsequently, the main surface of the semiconductor substrate in the MISFET formation region for the readout circuit is thermally oxidized in a wet or dry atmosphere at 800 ° C. to 900 ° C. to have a film thickness of 10 nm.
After the sacrificial oxide film 13 having a thickness of 20 nm is formed, channel ions are implanted into the read MISFET formation region (FIG. 9).

Next, the sacrificial oxide film 13 is washed with hydrofluoric acid.
After removing the silicon oxide film 6 on the inter-gate interlayer film
c and the silicon oxide film 14a to be the gate insulating film 14 of the read circuit MISFET Qr is formed to a thickness of 3 by the CVD method.
nm to 5 nm over the entire surface (FIG. 10).

Then, thermal oxidization is performed in a dry or wet atmosphere at 800 ° C. to 900 ° C. to perform MIS for the read circuit.
A silicon oxide film 14 to be the gate insulating film 14 of the read circuit MISFET Qr is formed in the FET formation region with a thickness of 10 to 2
Grow 0 nm. That is, the thermal oxidation increases the thickness of the silicon oxide film 14a formed on the semiconductor substrate 1 to form the silicon oxide film 14 having a thickness of 10 to 20 nm. Further, in this thermal oxidation, since the silicon oxide film hardly grows on the silicon nitride film 6b which is the oxidation resistant film, the film thickness of the silicon oxide film 6c as the upper layer of the inter-gate interlayer film hardly changes. That is, the film thickness of the silicon oxide film 6c formed on the silicon nitride film 6b by this thermal oxidation hardly changes.
Thus, as the inter-gate interlayer film 6 of the memory cell MC, the insulating film (ONO film) in which the silicon oxide film 6a, the silicon nitride film 6b, and the silicon oxide film 6c are stacked in this order from the bottom is a sufficiently thin silicon oxide film 6c. When the gate insulating film 14 of the read circuit MISFET Qr is formed in the same step, the thickness of the gate insulating film 14 is changed from that of the silicon oxide film 6c (thicker than the silicon oxide film 6c).
It can be formed (FIG. 11).

Further, the silicon oxide film 6c and the silicon oxide film 14 formed by the CVD method by this thermal oxidation are baked to become a dense film with a small defect density, and the silicon oxide film 6 is formed.
The film quality of c and 14 can be improved.

On the other hand, if this thermal oxidation is performed at 900 ° C. or higher, the defect density of the silicon oxide films 6c and 14 will increase. In order to reduce the defect density, it is preferable to use a wet atmosphere and thermal oxidation at 800 ° C. to 900 ° C. The silicon oxide film 6c needs to have a thickness of 3 nm or more in order to prevent holes from leaking from the control gate electrode 7 to the floating gate electrode 4. On the other hand, in consideration of reducing the film thickness of the inter-gate interlayer film 6, the above-mentioned 3 nm to 5 nm is preferable.

That is, the silicon oxide film 6c is formed on the silicon nitride film 6b in a thickness of 3 nm or more as compared with the case where the inter-gate interlayer film is formed of a two-layer film of the silicon oxide film 6a and the silicon nitride film 6b. By doing so, the leak current due to holes can be reduced more when the inter-gate interlayer film is formed.

After this thermal oxidation, annealing is performed in an inert gas atmosphere such as N ₂ O. By this annealing, the silicon oxide film 6c and the gate insulating film 14 are baked and the film quality is improved.

Then, a two-layer film (polycide film) 15 of a polycrystalline silicon film and a silicide film on the polycrystalline silicon film, which will be the control gate electrode 7 of the memory cell MC and the gate electrode of the read circuit MISFET Qr, is formed on the entire surface. Deposit. (FIG. 12). Note that 15 is not limited to a two-layer film, and may be composed of a polycrystalline silicon film single layer or a silicide film single layer.

Next, a resist mask 16 is formed by photolithography, the two-layer film 15 is patterned into word lines WL (control gate electrodes 7) by etching using the resist mask 16, and the inter-gate interlayer film 6 and The floating gate electrode 4 is patterned (FIG. 22).

Next, ion implantation of n-type impurity phosphorus (P) or arsenic (As) is performed to form the high-concentration region 3a forming the source region and the drain region 3 of the memory cell MC (FIG. 13). .

Next, a resist mask 17 that covers the memory cell MC region is formed by photolithography, and the gate electrode 18 of the read circuit MISFET Qr is patterned by etching using this resist mask 17 to form the write circuit MISFET region. The two-layer film 15 is removed. After that, the resist mask 17 is removed, and the source and drain regions 19 of the read circuit MISFET Qr are formed by using the gate electrodes 11 and 18 as masks.
Also, ion implantation of n-type impurity phosphorus (P) or arsenic (As) is performed to form the low concentration regions 19a and 20a forming the source region and the drain region 20 of the MISFET for the write circuit (FIG. 14).

Next, the side wall spacers 21, 22, 23 of each gate are formed, and ion implantation of n-type impurities is performed using the side wall spacers 21, 22, 23 as a mask to form the source region and the drain region 3. , 19 and 20 of high concentration regions 3b, 19b and 20b are formed (FIG. 15).

Thereafter, an interlayer insulating film 8 covering each element is deposited, and after forming a contact hole, each drain region 3 is connected by a metal wiring which becomes a data line DL, and the memory shown in FIGS. 1, 2 and 3. A cell MC is formed.

As described above, the read circuit MISFET Qr forming the peripheral circuit has the gate insulating film 14 having a thickness larger than that of the upper silicon oxide film 6c, the gate electrode 18 (the same layer as the control gate electrode 7), n. Type semiconductor region 19
(Source / drain region).

[0057] In the above description, the silicon oxide film 6c by thermal oxidation, after forming the gate insulating film 14, but is annealed in N ₂ O atmosphere is not limited thereto, subjected to annealing by N ₂ O atmosphere After that, thermal oxidation may be performed to form the silicon oxide film 6c and the gate insulating film 14. By this annealing, the silicon oxide film 6c and the gate insulating film 14 are baked and the film quality is improved.

In the above description, the CVD method is used.
After the silicon oxide films 14a and 6c having a thickness of 5 nm to 5 nm are formed, thermal oxidation is performed to perform the silicon oxide film 6c and the gate insulating film 1.
However, the present invention is not limited to this, and the thermal oxidation step and the step of forming an oxide film by the CVD method may be reversed as described below. That is, after removing the sacrificial oxide film 13 by hydrofluoric acid cleaning in the step shown in FIG.
Thermal oxidation is performed in a wet atmosphere of 800 ° C. to 900 ° C. to form a silicon oxide film 14a to be the gate insulating film 14 of the read circuit MISFET Qr in a read circuit MISFET formation region to a thickness of about 7 nm. At this time, no silicon oxide film is formed on the silicon nitride film 6b (FIG. 23).

Next, a silicon oxide film 6c which is an upper layer of the inter-gate interlayer film and a silicon oxide film 14c which becomes the gate insulating film 14 of the read circuit MISFET Qr are deposited on the entire surface to a thickness of about 3 nm by the CVD method. As a result, a thin upper silicon oxide film 14c is formed, and the silicon oxide film 1 is formed.
A thick gate insulating film 14 is formed from 4b and 14c (FIG. 24).

After that, annealing is performed in an inert gas atmosphere such as N ₂ O to bake the upper silicon oxide film 6c and the gate insulating film 14 to improve the film quality. After this, the subsequent steps shown in FIG. 12 are performed. As described above, also in the steps shown in FIGS. 23 and 24, the same effect as that of the above-described embodiment can be obtained.

As a reference example, a method performed by the inventors prior to the present invention will be described step by step with reference to FIGS. 16 to 19.

In the following description, in each drawing, the memory cell M
C, the MISFET for the read circuit and the MISFET for the write circuit respectively, the cross-sectional view in the column direction (word line direction) is shown in the upper stage, and the row direction (data line direction)
A cross-sectional view of is shown in the lower stage.

First, the steps up to the steps shown in FIGS. 5 to 6 are the same as those of the above-described embodiment, but thereafter, the surface of the floating gate electrode 4 and the gate electrode 11 of the write circuit MISFET is dried at 850 ° C. to 1000 ° C. Silicon oxide film 6 having a film thickness of 5 to 20 nm by thermal oxidation in an atmosphere
a is formed, then a silicon nitride film 6b having a film thickness of 10 to 20 nm is deposited at 700 ° C. to 800 ° C. by a CVD method, and thermal oxidation is performed in a wet steam atmosphere at 900 ° C. to 1000 ° C. An upper silicon oxide film 6c having a thickness of 10 nm is formed, and a silicon nitride film 6 having a thickness of 5 to 15 nm is formed in order to prevent the oxide film from being scraped in the cleaning process of the silicon oxide film 6c.
d is deposited by a CVD method at 700 ° C. to 800 ° C., and an insulating film (ONO) is formed by laminating a silicon oxide film 6a, a silicon nitride film 6b, a silicon oxide film 6c, and a silicon nitride film 6d in this order from the bottom.
An N film) is formed (FIG. 16).

Next, the resist mask 1 exposing the read MISFET formation region by photolithography.
2 is formed, and the silicon nitride film 6d, the silicon oxide film 6c and the silicon nitride film 6b in the read MISFET formation region are removed by dry etching (FIG. 17).

Next, after removing the resist mask 12, cleaning with hydrofluoric acid is carried out to read MISFET.
The silicon oxide film 6a and the gate insulating film 9 in the formation region are removed to expose the main surface of the semiconductor substrate 1 in the read MISFET formation region. When there is no silicon oxide film 6d on the silicon oxide film 6c of the inter-gate interlayer film 6, the silicon oxide film 6c is removed by this hydrofluoric acid cleaning. Subsequently, the main surface of the semiconductor substrate in the read circuit MISFET formation region is subjected to thermal oxidation in a wet or dry atmosphere at 800 ° C. to 900 ° C. to form a sacrificial oxide film 13 having a film thickness of 10 nm to 20 nm, and then formed in the read MISFET formation region. Channel ion implantation is performed (FIG. 18).

Next, the sacrificial oxide film 13 is washed with hydrofluoric acid.
After removing the MIS, thermal oxidation is performed in a dry or wet atmosphere at 800 ° C. to 900 ° C. to perform MIS for read circuit.
In the FET formation region, a silicon oxide film to be the gate insulating film 14 of the read circuit MISFET is formed with a film thickness of 10 to 20 nm (FIG. 19).

Subsequent steps are the same as in the normal manufacturing method, and the nonvolatile semiconductor memory device of the reference example is formed through the steps corresponding to FIGS. 12 to 15 of the above-mentioned steps.

In the semiconductor memory device of the reference example thus formed, since the inter-gate interlayer film is the ONON film, it is difficult to thin the inter-gate interlayer film, and the inter-gate interlayer film is formed. Separate from the process, M for reading circuit
A step of forming a gate insulating film of ISFET has been required. On the other hand, in the present invention, the inter-gate interlayer film can be an ONO film by the method described above, and the film thickness of the inter-gate interlayer film can be reduced.

Further, by utilizing the difference in the growth of the silicon oxide film depending on the underlying layer, the upper silicon oxide film of the inter-gate interlayer film and the gate insulating film of the read circuit MISFET are changed in film thickness in the same step. Since they are formed, the respective film thicknesses can be formed to the optimum values without increasing the number of steps.

Therefore, since the thickness of the inter-gate interlayer film is reduced, the characteristics of writing and erasing information are improved, and even if the size of the memory cell MC is reduced, the same characteristics as before can be obtained. Is possible.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

For example, in the above-described embodiments, the flash memory used as the ROM mounted in the microcomputer has been described as an example, but the present invention is also applicable to the flash memory used as a single storage device. It is also applicable to an EPROM or an EEPROM having a floating gate electrode.

Furthermore, the present invention can be applied to other processes in which the interlayer film and the gate insulating film are formed in the same step because the present invention has a plurality of polycrystalline silicon layers.

[0074]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, there is an effect that the inter-gate insulating film can be composed of an ONO film.

(2) According to the present invention, there is an effect that the upper silicon oxide film of the ONO film and the gate insulating film of the MISFET for the peripheral circuit can be formed in different thicknesses in the same step.

(3) According to the present invention, there is an effect that the upper silicon oxide film of the ONO film can be thinned.

(4) According to the present invention, the above effect (1)
The effect of (3) is that the gate insulating film can be thinned.

(5) According to the present invention, the above effect (4) has the effect of improving the characteristics of the nonvolatile semiconductor memory device.

(6) According to the present invention, due to the above effect (5), it is possible to reduce the element formation area of the nonvolatile semiconductor memory device.

[Brief description of the drawings]

FIG. 1 is a plan view showing a main part of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 shows a main part of the nonvolatile semiconductor memory device shown in FIG.
FIG. 6 is a vertical cross-sectional view taken along line bb of FIG.

FIG. 3 is a main part of the nonvolatile semiconductor memory device shown in FIG.
It is a longitudinal cross-sectional view shown along the line -b.

FIG. 4 is a diagram showing a configuration of a conventional one-chip microcomputer in which a nonvolatile semiconductor memory device and a nonvolatile semiconductor memory device according to an embodiment of the present invention are mounted.

FIG. 5 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 6 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 7 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 8 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 9 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 10 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 11 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 12 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 13 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 14 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 15 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 16 is a vertical cross-sectional view showing, for each step, a main part of a nonvolatile semiconductor memory device that is a reference example of the present invention.

FIG. 17 is a vertical cross-sectional view showing, for each step, a main part of a nonvolatile semiconductor memory device that is a reference example of the present invention.

FIG. 18 is a vertical cross-sectional view showing, for each step, a main part of a nonvolatile semiconductor memory device that is a reference example of the present invention.

FIG. 19 is a vertical cross-sectional view showing, for each step, a main part of a nonvolatile semiconductor memory device that is a reference example of the present invention.

FIG. 20 is a plan view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 21 is a plan view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 22 is a plan view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 23 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 24 is a vertical cross-sectional view showing, for each step, a main part of the nonvolatile semiconductor memory device according to the embodiment of the present invention.

[Explanation of symbols]

1 ... Semiconductor memory device, 2 ... Field insulating film, 3, 1
9, 20 ... Source region, drain region, 19a, 20a
... low-concentration region, 3a, 3b, 19b, 20b ... high-concentration region, 4 ... floating gate electrode, 5, 9, 14 ... gate insulating film, 6 ... inter-gate interlayer film, 6a, 6c ... silicon oxide film, 6b, 6d ... Silicon nitride film, 7 ... Control gate electrode, 8 ... Interlayer insulating film, 10, 15 ... Polycrystalline silicon film, 11, 18 ... Gate electrode, 12, 16, 17 ... Resist mask, 13 ... Sacrificial oxide film, 21 , 22, 23 ... Sidewall spacers.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 29/792

Claims (7)

[Claims] 1. A nonvolatile semiconductor memory device having a memory cell for storing information by holding electrons in a floating gate electrode and a MISFET for a peripheral circuit, wherein a floating gate electrode and a control gate electrode of the memory cell are provided between the floating gate electrode and the control gate electrode. The inter-gate interlayer film is a laminated film in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are sequentially laminated, and the upper silicon oxide film is a silicon oxide film formed substantially by CVD, and the gate insulation of the peripheral circuit MISFET is performed. A non-volatile semiconductor memory device characterized in that a film is formed by CVD and thermal oxidation or thermal oxidation and CVD to be a silicon oxide film having a film thickness different from that of the upper silicon oxide film. 2. The non-volatile semiconductor memory device according to claim 1, wherein the inter-gate interlayer film covers an upper surface and a side surface of the floating gate electrode. 3. A method for manufacturing a nonvolatile semiconductor memory device having a memory cell for storing information by holding electrons in a floating gate electrode and a MISFET for a peripheral circuit, wherein a conductor to be a floating gate electrode of the memory cell is formed. A step of depositing, a step of depositing a silicon oxide film forming an inter-gate interlayer film between the floating gate electrode and the control gate electrode of the memory cell, and a step of depositing a silicon nitride film forming the inter-gate interlayer film And a silicon oxide film to be an inter-gate interlayer film and a gate insulating film of a MISFET for a peripheral circuit is formed by CVD and thermal oxidation or thermal oxidation and CVD while changing the film thickness between the inter-gate interlayer film and the gate insulating film. And the control gate electrode of the memory cell and M for the peripheral circuit
And a step of depositing a conductor to be a gate electrode of the ISFET. 4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein thermal oxidation is performed after the silicon oxide film is formed by the CVD, and annealing is performed after the thermal oxidation by N ₂ O or the like. 5. After the silicon oxide film is formed by the CVD,
4. The method for manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein annealing is performed with N ₂ O or the like, and thermal oxidation is performed after the annealing. 6. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein a silicon oxide film is formed by CVD after the thermal oxidation, annealing is performed, and thermal oxidation is performed after the annealing. 7. The conductor as the gate electrode of the peripheral circuit MISFET is deposited by the step of depositing the conductor as the floating gate electrode of the memory cell. The method for manufacturing a nonvolatile semiconductor memory device according to any one of claims.