JPH09107073A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent damage or malfunction in transistor fed with a substrate potential other than one for an input protective circuit and eliminate an unstable state of the potential even at electrostatic discharge or at application of an input (VIL) of negative potential. SOLUTION: A well region 17 on a semiconductor substrate 11 includes a first semiconductor region 12 connected to an input pad 18, second semiconductor regions 13 and 14, to which a ground potential VSS is applied, and third semiconductor regions 15a and 15b, to which a first back gate bias potential VBB1 is applied. A second back gate bias potential VBB2 is applied to a semiconductor substrate 11. In this way, parasitic transistor and diode are generated among an input pad 18, the ground potential VSS, and the back gate bias potential VBB1 . Then, damage to a transistor or a malfunction in transistor can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device such as a large scale integrated circuit (LSI), and more particularly to an element structure of an input protection circuit section.

[0002]

2. Description of the Related Art In general, a semiconductor device such as an LSI has an electrostatic discharge (El discharge) in which a high voltage is accidentally applied to its external terminal or static electricity charged on a human body is discharged to the external terminal.
When ectroStatic Discharge (ESD) occurs, the elements inside the chip are destroyed. As a countermeasure, usually,
An input protection circuit is provided to protect the elements inside the LSI.

FIG. 1 shows a conventional LSI, for example, a 1 Mbit dynamic random access memory (DRA).
3 shows an example of the element structure of the input protection circuit section in M). Here, 21 is a P-type semiconductor substrate, 22 is a part of the surface region of the P-type substrate 21, and is an n + -type first semiconductor region connected to an input pad 25 for inputting an external signal. (N + diffusion layer), 23 and 24 are n + type second semiconductor regions (n + diffusion layer) formed in a part of the surface region of the P type substrate 21 and to which the ground potential Vss is applied. . An input circuit section (not shown) of the LSI is connected to the input pad 25.

FIG. 2 shows an equivalent circuit of the input protection circuit section shown in FIG. 26 is an input pad 25 and an n + diffusion layer
Reference numeral 27 denotes a resistance component between the n + diffusion layer 22, the P-type substrate 21, and the n + diffusion layers 23 and 24, and a parasitic bipolar transistor (NPN transistor). The base potential of the parasitic bipolar transistor 27 is the potential of the substrate 21, and is normally given the back gate bias potential VBB.

The input protection circuit section having the above-described structure is composed of an input pad.
When a large voltage is accidentally applied to an external terminal (not shown) connected to 25 or electrostatic discharge occurs, this input pad
N + diffused layer 22 connected to the n + diffused layer in the vicinity
Excessive current flows to 23,24 to prevent the destruction of circuit elements inside the LSI.

[0006]

However, the base potential of the parasitic bipolar transistor 27 is the back gate bias potential VBB. The back gate bias potential VBB is used by the transistors in the memory cell array section and cell peripheral circuit section (not shown) provided in the semiconductor substrate 21. Therefore, when an excessive current flows from the external terminal (not shown) to the input pad 25 due to electrostatic discharge, a large amount of current flows to the semiconductor substrate 21 and the substrate potential becomes unstable. The transistor in the circuit may be destroyed.

When testing the integrated circuit, a predetermined negative potential (VIL) is applied to an external terminal (not shown) connected to the input pad 25. Then, the minority carriers generated from the n + diffusion layer 22 connected to the input pad 25 flow out to the semiconductor substrate 21 and destabilize the back gate bias potential VBB. For this reason, the transistor using the back gate bias potential VBB may malfunction even outside the input protection circuit section.

The present invention has been made in order to solve the above problems, and an object of the present invention is to provide an input pad to which a signal is externally supplied when an excessive current flows due to electrostatic discharge. In addition, it is possible to stably hold the substrate potential and prevent destruction of the transistor using the substrate potential in circuits other than the input protection circuit unit. It is the one we are trying to provide.

Another object of the present invention is to keep the substrate potential stable even when a test negative input potential (VIL) is applied to the input pad, and in a circuit other than the input protection circuit section, It is an object of the present invention to provide a semiconductor device including a highly reliable input protection circuit section that can prevent a malfunction of a transistor using a substrate potential.

[0010]

In order to solve the above problems, the present invention provides a first conductivity type semiconductor substrate and a second conductivity type well region formed in a part of the surface region of the semiconductor substrate. , Formed in a part of the surface area of this well area,
First connected to an input pad for inputting an external signal
A first semiconductor region of a conductivity type, a second semiconductor region of a first conductivity type formed in a surface region of the well region, and a first semiconductor region of the second semiconductor region in a surface region of the well region. A third semiconductor region of the second conductivity type formed on the side opposite to the semiconductor region side, and the well region does not include a semiconductor region other than the first, second, and third semiconductor regions,
It is independent of other semiconductor circuits provided in the semiconductor substrate, a ground potential is applied to the second semiconductor region, and a first back voltage lower than the ground potential is applied to the third semiconductor region. A gate bias potential is applied, a second back gate bias potential different from the first back gate bias potential is applied to the other semiconductor circuit of the semiconductor substrate, and the first semiconductor region, the well region, and Second
The semiconductor region of forms a parasitic bipolar transistor,
The first semiconductor region, the well region and the third semiconductor region form a parasitic diode connected in parallel with the parasitic bipolar transistor.

That is, the present invention relates to the first conductivity type first
A second conductivity type well region independent of other semiconductor circuits provided in the semiconductor substrate is formed in a part of the surface region of the semiconductor region, and an external signal is applied to a part of the surface region of the well region. A first semiconductor region of a first conductivity type connected to an input pad for input, and a first semiconductor region to which a ground potential is applied.
A second semiconductor region of conductivity type and a first semiconductor region lower than ground potential
By providing the third semiconductor region of the second conductivity type to which the back gate bias potential is applied, the parasitic bipolar transistor and the parasitic diode are formed in parallel with the input pad. Therefore, when an excessive current flows through the input pad due to electrostatic discharge, the parasitic bipolar transistor becomes conductive, and the excessive current can flow from the first semiconductor region to the second semiconductor region. Moreover, the input protection circuit is formed in a dedicated well region, the input protection circuit and other circuits are separated, and the base potential of the parasitic bipolar transistor, that is, the well region potential is the first back gate bias potential. Since it is different from the second back gate bias potential applied to the other semiconductor circuits on the semiconductor substrate, the internal circuit can be prevented from being destroyed even when an excessive current flows through the bipolar transistor.

The ground potential is supplied to the second semiconductor region, the first back gate bias potential is supplied to the third semiconductor region, and the first back gate bias potential is supplied to the other semiconductor circuits on the semiconductor substrate. And a second back gate bias potential different from the above. Therefore, the potential of the third semiconductor region can be set lower than the ground potential, which makes it more difficult to turn on the parasitic diode with respect to the negative test potential.

Further, even when a negative potential for testing (VIL minus) is applied to the input pad and the first semiconductor region and the well region are forward biased, minority carriers are generated from the first semiconductor region. Since the well region is independent of other circuits and the back gate bias potentials of the well region and other circuits are separated, the generated carriers do not change the back gate bias of the other circuits, and the internal circuit does not change. It is possible to prevent the destruction of data. Moreover, since the parasitic diode has a clamping action, the input undershoot resistance can be improved.

Further, by disposing the input protection circuit in a dedicated well, it is possible to apply an optimum bias to the second and third semiconductor regions, the well region and the semiconductor substrate. There is.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. 3 and 4 show an embodiment of the present invention, which is an LSI, for example, 16
1 shows an example of an element structure of an input protection circuit section in an M-bit DRAM.

In the input protection circuit section IPC shown in FIGS. 3 and 4, a P type well region (P well) 17 is formed in a part of the surface region of the N type semiconductor substrate 11. An n + type first semiconductor region (n + diffusion layer) 12 is formed in a part of the surface region of the P well 17, and the first semiconductor region is formed.
An input pad 18 to which an external signal is input is connected to 12. The input pad 18 is provided in the vicinity of the first semiconductor region 12, and the input pad 18 is connected to an input circuit IN of an integrated circuit composed of, for example, an inverter circuit and a signal is applied from the outside. Connected to the external terminal 16.

A part of the surface area of the P well 17 is the first
On both sides of the semiconductor region 12, the n + type second semiconductor regions (n + diffusion layers) 13 and 14 are formed. A constant potential, such as the ground potential Vss, is applied to these second semiconductor regions 13 and 14, respectively. A p + type third semiconductor region (p + diffusion layer) 15 is formed around the second semiconductor regions 13 and 14 in a part of the surface region of the P well 17.
The third semiconductor region 15 has a portion 15a along the second semiconductor region 13 and a portion 15b along the second semiconductor region 14. In the third semiconductor region 15,
A constant potential, for example, the first back gate bias potential VBB1
Is applied. Therefore, the potential of the well region 17 is set to the first back gate bias potential VBB1 via the third semiconductor region 15. The first back gate bias potential VBB1 is, for example, -2 to -3V, which is lower than the potential Vss = 0V of the n + diffusion layers 13 and 14.

The well region 17 does not include semiconductor regions other than the first, second, and third semiconductor regions 12, 13, 14, and 15. That is, as shown in FIG. 3, the input protection circuit section is provided in one independent well region 17.

A second back gate bias potential VBB2 is supplied to the semiconductor substrate 11. That is, as shown in FIG. 5, in the semiconductor substrate 11, the input protection circuit unit IP
C is provided, and a peripheral circuit 60 and a memory cell array unit 61 are provided. Further, the semiconductor substrate 11 has
First to generate a first back gate bias potential VBB1
2 is provided, and a second potential generating circuit 63 for generating the second back gate bias potential VBB2 is provided. In the input protection circuit section IPC,
The first back gate bias potential VBB1 is supplied from the first potential generation circuit 62, and the second back gate bias potential VBB2 is supplied from the second potential generation circuit 63 to the peripheral circuit 60 and the memory cell array section 61. ing. The first and second back gate bias potentials VBB1 and VBB2 may be the same potential or different potentials.

FIG. 6 is a circuit diagram of the input protection circuit shown in FIGS.
The equivalent circuit of IPC is shown. Reference numeral 19 is a parasitic transistor (NPN transistor) formed by the n + diffusion layer 12, the P well 17, and the n + diffusion layers 13 and 14.
Reference numeral 10 is a parasitic diode formed by the n + diffusion layer 12, the P well 17, and the p + diffusion layer 15.

According to the above-described embodiment, when the external terminal 16 connected to the input pad 18 is accidentally applied with a large voltage or the external terminal 16 is electrostatically discharged, the external terminal 16 is connected to the input pad 18. An excessive current flows through the parasitic transistor 19 and does not flow inside the memory cell array section or the cell peripheral circuit section. Therefore, it is possible to prevent the destruction of the circuit elements inside the integrated circuit. In this case, even if a considerable amount of current flows into the P well region 17 when an excessive current flows, the substrate potential does not become unstable, and the transistors in the memory cell array section and cell peripheral circuit section are destroyed. Never.

Further, the peripheral circuit 60 and the memory cell array section 61
The back gate bias potential supplied to the input protection circuit block and the back gate bias potential supplied to the input protection circuit section IPC are separated. Therefore, in the test of the integrated circuit, a negative potential (VIL minus) is input to the input pad 18 to forward bias the first semiconductor region and the well region, and
Even when minority carriers are generated from the semiconductor region of, since the well region is independent of other circuits and the back gate bias potentials of the well region and other circuits are separated, other carriers are generated by the generated carriers. The back gate bias of the circuit does not fluctuate, and the destruction of data in the internal circuit can be prevented. Moreover, since the parasitic diode has a clamping action, the input undershoot resistance can be improved.

Further, a large current flows through the parasitic diode 10,
Even when the output potential of the first potential generating circuit 62 fluctuates through the p + diffusion layers 15a and 15b, the input protection circuit section IPC
Is isolated from other circuits by the well region 17, and
The output potential of the first potential generation circuit 62 is the input protection circuit section IPC.
Since the noise is generated by the large current, circuits other than the input protection circuit section IPC do not malfunction because they are not supplied to circuits other than the above.

In the above embodiment, the p + diffusion layer
15 is not necessarily formed on the outer peripheral edge of the P well 17. The first back gate bias potential may be supplied via a resistor. Besides, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the spirit of the invention.

[0025]

As described above in detail, according to the present invention, it is possible to prevent the substrate potential from becoming unstable during electrostatic discharge or application of a negative potential (VIL) for testing, and the input protection circuit section can be prevented. It is possible to provide a semiconductor device provided with a highly reliable input protection circuit section capable of preventing breakdown or malfunction of a transistor using a substrate potential other than the above.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an input protection circuit section of a conventional semiconductor device.

FIG. 2 is an equivalent circuit diagram of the input protection circuit unit shown in FIG.

FIG. 3 is a sectional view showing an embodiment of the present invention.

FIG. 4 is a plan view showing a pattern of the input protection circuit section shown in FIG.

5 is a circuit configuration diagram of a semiconductor device using the circuits shown in FIGS. 3 and 4. FIG.

6 is an equivalent circuit diagram of the input protection circuit unit shown in FIG.

[Explanation of symbols]

10 ... Parasitic diode, 11 ... N-type semiconductor substrate, 12 ... N + type first semiconductor region (n + diffusion layer), 13, 14 ... N + type second semiconductor region (n + diffusion layer), 15, 15a, 15b ... P + type third semiconductor region (p + diffusion layer), 16 ... External terminal, 17 ... P type well region (P well), 18 ... Input pad, 19 ... Parasitic transistor (NPN) Transistor), IPC ... Input protection circuit section, IN ... Input circuit, VBB1, VBB2 ... First and second back gate bias potentials, Vss ... Ground potential.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenji Numata, 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Research Institute Co., Ltd. No. 1 Incorporated company Toshiba Research Institute

Claims (4)

[Claims] 1. A semiconductor substrate of a first conductivity type, a well region of a second conductivity type formed in a portion of a surface region of the semiconductor substrate, and a well region of a surface region of the well region, A first conductive type first semiconductor region connected to an input pad for inputting a signal; a first conductive type second semiconductor region formed in a surface region of the well region; A third semiconductor region of a second conductivity type formed on a surface region of the second semiconductor region opposite to the first semiconductor region side, and the well region includes the first and the first semiconductor regions. 2, the semiconductor region other than the third semiconductor region is not included, is independent of other semiconductor circuits provided in the semiconductor substrate, and a ground potential is applied to the second semiconductor region, In the semiconductor region, a first back ground voltage lower than the ground potential is provided. A second back gate bias potential different from the first back gate bias potential is applied to the other semiconductor circuit of the semiconductor substrate, and the first semiconductor region, the well region, and the first back gate bias potential are applied. The second semiconductor region forms a parasitic bipolar transistor, and the first semiconductor region, the well region, and the third semiconductor region form a parasitic diode connected in parallel to the parasitic bipolar transistor. 2. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is provided with first and second potential generation circuits for generating the first and second back gate bias potentials. apparatus. 3. The semiconductor device according to claim 2, wherein the first and second back gate bias potentials are different from each other. 4. The semiconductor device according to claim 2, wherein the first and second back gate bias potentials are the same potential.