JPH09102731A - Switched capacitor arithmetic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of capacitors by performing the ON/OFF control of the 1st to 7th switches and also controlling the voltage applied to the 1st and 2nd capacitors at each proper level. SOLUTION: The 1st to 7th switch elements 30, 33, 35, 37, 38, 40 and 42 consist of n-channel MOS transistors respectively and are turned on when the timing signals ϕ1 and -ϕ1 applied to every gate of transistors are set at high levels. At the same time, an input terminal 43 is connected to the positive phase + input of an operational amplifier 36 and an output terminal 44 is connected to the output of the amplifier 36 respectively. In such a constitution, the necessary circuit operations are secured even with the capacitors in a number smaller than the ordinary number by one, i.e., the 1st and 2nd capacitors 32 and 39. In addition, the troubles of both occupied area and conversion accuracy can be simultaneously eliminated since it is easier to equalize the capacitance of two capacitors than of three.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switched capacitor arithmetic circuit, and more particularly, a circuit for digital-to-analog conversion (hereinafter "D / A conversion") of a ternary internal code corresponding to each digit of a digital input signal. The present invention relates to a switched capacitor arithmetic circuit suitable for use in a type D / A converter.

[0002]

BACKGROUND ART FIG. 9 is a schematic block diagram of a cyclic D / A converter. The conversion control circuit 1 uses n + 1 of D _{0 to} D _n.
Internal code corresponding to each digit of bit digital input signal CT _{0 to} CT _m ... Each bit takes a value of “+1”, “0” or “−1”. ........., the cyclic D / A conversion circuit 2 generates internal codes CT _{0 to} C
The sample / hold circuit 3 executes predetermined arithmetic processing according to T _m , the reference voltage V _ref, etc., and samples the result of the same arithmetic processing for a predetermined time, and holds the sampled value after the completion of the arithmetic processing to hold an analog value. and outputs as a voltage V _{ou t.} Note that C
K is a system clock signal, STC is an external control signal that specifies the start of the conversion operation, and φ ₀ is a signal that determines the sunring period and the hold timing.

FIG. 10 is a conceptual configuration diagram including a circulation type D / A conversion circuit 2 and a sample hold circuit 3. The circulation type D / A conversion circuit 2 has the contact state shown when the signal STC is at H level. It has a switch element 2a and a two block section (switched capacitor arithmetic circuit) 2b, 2c of the same configuration, which connects the input and output in a crossed manner. Analog output voltage V _out A of the blocks 2b and 2c
/ B (V _out A or V _{ou t} B) can be expressed by the following equation.

V _out A / B = 1/2 (V _in A / B + Ai × V _ref ) ... Here, Ai is a ternary signal of +1, 0, −1. FIG.
1 is a 4-bit digital input signal (that is, D _{0 to} D
₃ ) is the timing of the signals STC, CK and φ ₀ . In FIG. 11, BLOCK_A (S /
H) and BLOCK_B (S / H) represent operating states of the upper block 2b and the lower block 2c, respectively. The L level is the sampling period and the H level is the hold period. Sampling period A1, A2, A3
Represents the value of Ai in the above equation at that time.

Now, set the signal STC to H level (1 CK)
Data (D₀, D₁, D_Two, D _Three) = (0,1,
0, 0) is input, this data is converted into the conversion control circuit 1
The ternary signal (A1, A2, A
3) = (+ 1, -1,0), and CT₀~ CT_m
Is sent serially to the two blocks 2b and 2c as
You.

The switch element 2a operates so that the state shown in the figure is obtained at the STC = H level and the opposite state is obtained at the STC = L level. As a result, V _in A = 0V (ground potential) is obtained at the first CK after the conversion operation is started, and thereafter, V _out
Input / output circulates between the two block units 2b and 2c, such as A → V _in B and V _out B → V _in A. In the case of n = 3, φ ₀ is L level up to 4 cycles of CK, during which the sample and hold circuit 3 continues to sample V _out A, and when φ ₀ becomes H level, that value Is held and output as an analog voltage V _out shown in the following equation.

[0007]

(Equation 1)

Here, substituting the actual values (+1, 0, -1) into the coefficients A1, A2, A3,

[0009]

(Equation 2)

Finally, V _out becomes 2/8 V _ref .

[0011]

2. Description of the Related Art FIG. 12 is a block diagram of a block section (switched capacitor arithmetic circuit) 2b, 2c. In this figure, 10 to 16 are first to seventh switch elements using n-channel MOS transistors, 17 to 19 are first to third capacitors, and 20 is an operational amplifier such as an operational amplifier. C _{1 to} C ₃ are the first to third capacitors 17 to
The respective capacitance values of 19, φ ₁ , φ ₁ bar, φ ₂ and φ ₂ bar are ON / OFF control signals (ON at H level) of the first to seventh switch elements 10 to 16.

Now, the voltage applied to the first to third capacitors 17 to 19 when φ ₁ = H level is V ₁ (-1 / -1)
2), V ₂ (-1/2), V ₃ (-1/2), φ ₁
The same voltage when the bar is at H level is V ₁ (1/2), V
Considering the timing chart shown in FIG. 13 with ₂ (1/2) and V ₃ (1/2), from the H level period of φ ₁ to φ
_In the transient operation of ₁ bar to the H level period, the following charge conservation law is established.

C ₁ × V ₁ (−1/2) + C ₂ × V ₂ (−
1/2) + C ₃ × V ₃ (−1/2) = C ₁ × V ₁ (1 /
2) + C ₂ × V ₂ (1/2) + C ₃ × V ₃ (1/2) Here, in FIG. 12, V ₂ (−1/2) = 0 V ₃ (−1/2) = V _in A / B V ₂ (1/2) = V ₃ (1/2) = V _out A / B,

[0014]

(Equation 3)

When C ₁ = C ₂ = C ₃ , V _out A / B = 1/2 {V _in A / B + V ₁ (−1/2)
-V ₁ (1/2)}, and the time of phi ₂ = H level, V ₁ = V _ref, when phi ₂ bar = H level, since the V ₁ = 0, the timing T ₁ V at the end _out A / B is 1/2 (V _in A / B + V _ref ) V _out at the end of timing T ₂ A / B is 1/2 (V _in A / B) V _out at the end of timing T ₃ A / B becomes 1/2 (V _in A / B-V _ref ).

[0016]

SUMMARY OF THE INVENTION
Three in the conventional switched capacitor arithmetic circuit
The capacitors 17 to 19 are required.
Occupied area by the service ........ 1 capacitance value is set to 16PF
And about 30,000 μm^Two× 3, and this
Needs 2 blocks, but the question is ...
There is a point. To obtain the intended circuit operation,
Accurately match all capacitance values (C₁= C_Two= C _Three) Do not let
However, it is difficult to make a perfect match if manufacturing errors are taken into consideration.
It is difficult to improve the conversion accuracy sufficiently.
There was a title.

Therefore, an object of the present invention is to provide a useful technique capable of reducing the number of capacitors and solving the problems of the occupied area and the conversion accuracy all at once.

[0018]

According to the first aspect of the present invention,
A first switch element for turning on / off between the first input terminal and one end of the first capacitor, and a second switch element for turning on / off between the second input terminal and the other end of the first capacitor. A third switch element for turning on and off between the negative phase input of the operational amplifier and the other end of the first capacitor, and a third switch element for turning on and off between the output of the operational amplifier and one end of the first capacitor. Switch element 4, a fifth switch element for turning on and off between the other end of the second capacitor, one end of which is connected to the negative phase input of the operational amplifier, and the output of the operational amplifier, and a third input terminal. A sixth switch element for turning on and off between the other end of the second capacitor and a seventh switch element for turning on and off between a negative phase input and an output of the operational amplifier; To do.

In such a configuration, ON / OFF of the first to seventh switch elements is appropriately controlled, and the first switch element, the second switch element, the sixth switch element and the seventh switch element are turned ON. when the the voltage applied to the first and second capacitors, V ₁ (-1 /
2), V ₂ (−1/2), and when the remaining switch elements (third switch element, fourth switch element and fifth switch element) are on, the first capacitor and the second capacitor The voltage applied to the capacitor is V ₁ (1/2), V ₂ (1
/ 2), the same operation as in the conventional example can be obtained even with a capacitor (first and second capacitors) that is one less than in the conventional example (see FIG. 12), and the problem of the occupied area and the problem of conversion accuracy are solved. Can be solved all at once.

Alternatively, the invention according to claim 2 is characterized in that a first switch element for turning on and off between the first input terminal and one end of the first capacitor, a second input terminal and the first capacitor. A second switch element for turning on and off between the other end, a third switch element for turning on and off between a negative phase input of the operational amplifier and the other end of the first capacitor, an output of the operational amplifier and the above A fourth switch element that turns on and off between one end of the first capacitor, a second capacitor connected between a negative phase input and an output of the operational amplifier, and a negative phase input and output of the operational amplifier. And a seventh switch element for turning on and off between and.

This configuration can be applied when the voltage of the third input terminal in the invention of claim 1 is used in common with the voltage of the fourth input terminal. The fifth switch element, the sixth switch element and the third input terminal in the invention according to claim 1 are unnecessary, and the configuration is simplified.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a first embodiment of a switched capacitor arithmetic circuit according to the present invention. 30 is the first
A first switch element connected between the input terminal 31 and one end 32a of the first capacitor 32, and 33 connected between the second input terminal 34 and the other end 32b of the first capacitor 32. The second switch element 35 is an operational amplifier 3
The third switch element connected between the negative phase input (-input) of 6 and the other end 32b of the first capacitor 32, 37 is the output of the operational amplifier 36 and one end 3 of the first capacitor 32.
A fourth switch element 38 connected between 2a and 2a is connected between the other end 39b of the second capacitor 39 whose one end 39a is connected to the negative phase input of the operational amplifier 36 and the output of the operational amplifier 36. A fifth switch element, 40 a sixth switch element connected between the third input terminal 41 and the other end 39b of the second capacitor 39, and 42 an operational amplifier 3
6 is a seventh switch element connected between the negative phase input and output of 6. All these switch elements (first to seventh
Switch elements 30, 33, 35, 37, 38, 40 and 42) of the above are constituted by n-channel MOS transistors, and the timing signal φ ₁ (and its inverted signal φ ₁ bar) applied to each gate is H level. It is designed to turn on at the level. Incidentally, 43 is a fourth input terminal connected to the positive phase input (+ input) of the operational amplifier 36, and 44 is an output terminal connected to the output of the operational amplifier 36.

In such a configuration, the signals φ ₁ , φ ₁
Set the bar timing as shown in Fig. 2 and set φ ₁
= H level, the voltage applied to the first capacitor 32 and the second capacitor 39 is V ₁ (−1/2), V ₂
(-1/2), and when φ ₁ bar = H level, the first
If the voltages applied to the second capacitor 39 and the second capacitor 39 are V ₁ (1/2) and V ₂ (1/2), the following charge conservation law is established.

C ₁ × V ₁ (−1/2) + C ₂ × V ₁ (−
1/2) = C ₁ × V ₁ (1/2) + C ₂ × V ₂ (1 /
2) _{Here, V 1 (-1/2) = V} B -V A V 2 (-1/2) = V D -V C V 1 (1/2) = V 2 (1/2) = V _out −V _C , and the output voltage V _out can be expressed by the following equation.

[0025]

(Equation 4)

[0026] Thus, when _{C 1 = C 2 = C,} V out = 1/2 (-V A + V B + V C + V D) , however, V _A: the voltage of the second input terminal 34 V _B: first Input terminal 31 voltage V _C : fourth input terminal 43 voltage V _D : third input terminal 41 voltage, for example, (V _A , V _B , V _C , V _D ) = (0 , V _ref , 0,
V _in) However, V _ref: reference voltage V _in: When the input _{voltage, V out = 1/2 (} V in + V ref) _{also, (V A, V B,} V C, V D) = (0,0 , 0, V _in ), V _out = 1 / 2V _in , and (V _A , V _B , V _C , V _D ) = (V _ref , 0, 0,
If V _in ), then V _out = ½ (V _in −V _ref ). Therefore, the circuit of this embodiment operates according to the input / output conditions shown in Table 1 below. Since this operation is similar to that of the conventional example, the required circuit operation can be obtained even with one less capacitor (first and second capacitors 32 and 39). As a result, it is possible to reduce the area equivalent to one capacitor, and it is easier to make the capacities of two capacitors equal to three capacitors. Can be solved all at once.

When constructing a multi-input arithmetic circuit, a required number of units A and B are used in combination. The section A is connected in parallel using terminals A ₁ and A ₂ shown for convenience, and the section B is terminals B _1U , B _2U , B _1D and B _2D shown for convenience.
To connect in series. For example, A part x m pieces, B part x
In the case of n pieces, m pieces of A parts are lined up in the front and back direction of the drawing with the terminals A ₁ and A ₂ being common, and under the A part (below the drawing)
The n B parts are lined up. The first terminals B _1U and B _2U of the B section are connected to the terminals A ₁ and A ₂ of the A section, and the first terminals B _1D and B _2D of the B section are connected to the second B section. Terminal B _1U , B _2U
, And the terminals B _1D and B _2D of the n-th part B are connected to the negative phase input and output of the operational amplifier 36. In the case of this example, V _A and V _B are m (V _{A1 to} V _Am , V _{B1 to} V _Bm ),
V _D becomes n (V _{D1 to} V _Dn ), and as shown in the following equation,
An output voltage V _out corresponding to multiple inputs can be obtained. However, i is 1 to m and j is 1 to n.

V_out= (-ΣC_1i× V_Ai+ ΣC_1i× V_Bi
+ ΣC_1i× V_C+ ΣC_2j× V_Dj) / (ΣC_1i+ ΣC_2j) FIG. 3 shows a switched capacitor arithmetic circuit according to the present invention.
It is a figure which shows 2 Example. 50 is the first input terminal 51
Connected between the one end 52a of the first capacitor 52 and
The first switch element 53 is connected to the second input terminal 54 and the first
The second end connected between the other end 52b of the condenser 52 of
, 55 is a negative phase input of the operational amplifier 56 (-
Input) and the other end 52b of the first capacitor 52.
The connected third switch element 57 is an operational amplifier 56.
Connected between the output and one end 52a of the first capacitor 52
The fourth switch element, 58 is the negative of the operational amplifier 56.
A second capacitor connected between the phase input and the output, 5
9 is connected between the negative phase input and the output of the operational amplifier 56
It is the seventh switch element. All these switches
Elements (first switch element 50, second switch element 5
3, third switch element 55, fourth switch element 57
And the seventh switch element 59) is an n-channel MOS transistor.
It consists of a transistor, and the tag added to each gate.
Imming signal φ ₁(And its inverted signal φ₁H)
It turns on when the bell is turned on. In addition, 60 is
The fourth connected to the positive phase input (+ input) of the operational amplifier 56
Input terminal, 61 is an output connected to the output of the operational amplifier 56
Terminal.

In such a configuration, the signals φ ₁ , φ ₁
Set the bar timing as shown in Fig. 2 and set φ ₁
= H level, the voltage applied to the first capacitor 52 and the second capacitor 58 is V ₁ (−1/2), V ₂
(-1/2), and when φ ₁ bar = H level, the first
When the voltage applied to the capacitor 52 and the second capacitor 58 is V ₁ (1/2) and V ₂ (1/2), the following charge conservation law is established.

C ₁ × V ₁ (−1/2) + C ₂ × V ₁ (−
1/2) = C ₁ × V ₁ (1/2) + C ₂ × V ₂ (1 /
2) _{Here, V 1 (-1/2) = V} B -V A V 2 (-1/2) = 0 V 1 (1/2) = V 2 (1/2) = V out -V C Therefore, C ₁ × (V _B −V _A ) = (C ₁ + C ₂ ) × (V _out −V
_C ) V _out = {C ₁ / (C ₁ + C ₂ )} × (V _B −V _A ) +
V _{C and} assuming C ₁ = C ₂ = C, V _out = (1/2) × (V _B −V _A ) + V _C = (1/2) × (−V _A + V _B + 2V _C ) V _ref Is a reference voltage, V _in is an input voltage from the outside, and (V _A , V _B , V _C ) = (V _ref , V _in , V _ref ), V _out = 1/2 (V _in + V _ref ). And (V _A , V _B , V _C ) = (0, V _in , 0), V _out = 1/2 (V _in ), and (V _A , V _B , V _C ) = (V _ref , V _in , 0), V _out = 1/2 (V _in −V _ref ), and eventually the input / output conditions as shown in the following Table 2 are obtained. Below margin

[0031] In the case of constructing a multi-input arithmetic circuit, as in the first embodiment, a required number of units A and B are used in combination. When the A part × m number and the B part × n number are set, the output voltage V _out of the present embodiment is given by the following equation. However, i is 1 to
m and j are 1 to n.

V _out = {-ΣC _1i × V _Ai + ΣC _1i × V _Bi
+ (ΣC _1i × ΣC _2j ) × V _C } / (ΣC _1i + ΣC _2j ) FIG. 4 is a diagram showing a third embodiment of the switched capacitor arithmetic circuit according to the present invention, which is a specific example of the second embodiment. .
70 is a first switch element connected between the first input terminal 71 and one end 72a of the first capacitor 72, 73
Is the second input terminal 74 and the other end 7 of the first capacitor 72.
2b is a second switch element connected between the second switch element and 2b, 75 is a third switch element connected between the negative phase input (-input) of the operational amplifier 76 and the other end 72b of the first capacitor 72, 77 is the output of the operational amplifier 76 and the first capacitor 7
4 is a fourth switch element connected to the one end 72a of the second amplifier, 78 is a second capacitor connected between the negative phase input and the output of the operational amplifier 76, and 79 is a negative phase input of the operational amplifier 76. It is a seventh switch element connected between the output and the output. Reference numeral 80 is an output terminal connected to the output of the operational amplifier 76.

The difference from the second embodiment is that the first capacitor
Connect the switch element 81 between the other end 72b of 72 and the ground.
Continuation point, positive phase input of operational amplifier 76 and second input terminal
A switch element 82 is connected between the switch 74 and
Switch element 8 between the positive phase input of the operational amplifier 76 and ground
It is the point where 3 is connected. In such a configuration, each
Signal φ that controls on / off of the switch element₁, Φ ₁bar,
φ_Two, Φ_Three, Φ_Four, Φ_FiveSet the timing as shown in Fig. 5.
As well as φ₁= 1st cond when H level
The voltage applied to the sensor 72 and the second capacitor 78 is V₁
(-1/2), V_Two(-1/2), φ₁Bar = H
The first condenser 72 and the second condenser at the time of bell
The voltage applied to the₁(1/2), V_Two(1 /
Then, the following charge conservation law holds.

C ₁ × V ₁ (−1/2) + C ₂ × V ₂ (−
1/2) = C ₁ × V ₁ (1/2) + C ₂ × V ₂ (1 /
2) Here, if V ₂ (−1/2) = 0 and C ₁ = C ₂ = C, then V ₁ (−1/2) = V ₁ (1/2) + V ₂ (1/2 ).

Table 3 below shows φ ₂ = φ ₂ when φ ₁ = H level
a correlation table of V ₁ (-1/2) and the corresponding respective states of phi _5. Table 4 below shows each state of φ ₂ to φ ₅ when φ ₁ bar = H level and the corresponding V ₁ (1/2) and V ₂ (1 /
It is a correlation table of 2).

[0036] From Table 3 and Table 4, the output voltage V _out at the end of timing T ₁₁ is V _out = 1/2 (V _in −V _ref ) The output voltage V _out at the end of timing T ₁₂ is V _out = 1/2 (V _in ) The output voltage V _out at the end of the timing T ₁₃ becomes V _out = 1/2 (V _in + V _ref ), and the conventional example is achieved by using one less capacitor (first and second capacitors 72, 78). The same circuit operation as can be obtained.

FIG. 6 is a diagram showing a fourth embodiment of the switched capacitor arithmetic circuit according to the present invention, which is a concrete example of the first embodiment. 90 is a first switch element connected between the first input terminal 91 and one end 92a of the first capacitor 92, and 93 is a first input terminal 91 (which also serves as a second input terminal) and a first switch element. Second switch element connected between the other end 92b of the capacitor 92 of
Negative-phase input (-input) and the other end 9 of the first capacitor 92
3b is a third switch element connected between 2b and 2b, and 97 is the output of the operational amplifier 96 and one end 92 of the first capacitor 92.
The fourth switch element 98 connected to the a is connected between the other end 99b of the second capacitor 99 whose one end 99a is connected to the negative phase input of the operational amplifier 96 and the output of the operational amplifier 96. A fifth switch element, 100 is a sixth switch element connected between the third input terminal 101 and the other end 99b of the second capacitor 99, and 102 is a negative phase input and output of the operational amplifier 96. Is a seventh switch element connected between. Reference numeral 103 is an output terminal connected to the output of the operational amplifier 96.

The difference from the first embodiment is that the first capacitor
A switch element between both ends 92a and 92b of 92 and the ground
Point where 104 and 105 are connected, positive phase input of operational amplifier 96
It is at the point where the force is connected between ground. In such a configuration
Signal that controls on / off of each switch element
φ₁, Φ ₁Bar, φ_Two, Φ_Three, Φ_Four, Φ_FiveTiming
Is set as shown in Fig. 7, and φ₁= When H level
Of the first and second capacitors 72 and 78.
The voltage₁(-1/2), V_Two(-1/2) and
, Φ₁First capacitor 7 when bar = H level
2 and the voltage applied to the second capacitor 78,₁(1 /
2), V_Two(1/2), the following law of conservation of charge holds
I do.

C ₁ × V ₁ (−1/2) + C ₂ × V ₂ (−
1/2) = C ₁ × V ₁ (1/2) + C ₂ × V ₂ (1 /
2) Here, if V ₂ (−1/2) = V _in V ₁ (1/2) = V ₂ (1/2) = V _out , and C ₁ = C ₂ = C, then V _out = 1/2 {V _in + V ₁ (−1/2)}.

The following Table 5 shows φ ₂ ~ when φ ₁ = H level
a correlation table of V ₁ (-1/2) and the corresponding respective states of phi _5. Below margin From Table 5, the output voltage V at the end of timing T _21
out is V _out = 1/2 (V _in −V _ref ) The output voltage V _out at the end of timing T ₂₂ is V _out = _½ (V _in ) The output voltage V _out at the end of timing T ₂₃ is Since V _out = 1/2 (V _in + V _ref ), a circuit operation similar to that of the conventional example can be obtained with one less capacitor (first and second capacitors 72 and 78).

The configuration of the fourth embodiment may be modified as shown in FIG. That is, the first input terminal 200 and the second
Input terminal 201 is provided, and V is connected to the first input terminal 200.
_{In addition} to applying _in , V _{ref is applied} to the second input terminal 201b, and the switch element 202 is connected between the other end 99b of the second capacitor 99 and the ground, and the on / off timing of each switch element is controlled according to FIG. You may.

[0042]

According to the present invention, the number of capacitors can be reduced to two (one less than that in the conventional example). Therefore, it is possible to reduce the area for one capacitor and to match the capacitance values of the two capacitors more easily than with the three capacitors, so that the capacitance values can be matched exactly and the conversion accuracy can be improved.
That is, an advantageous effect that cannot be obtained by the conventional example is obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment.

FIG. 2 is a timing chart of the first embodiment.

FIG. 3 is a configuration diagram of a second embodiment.

FIG. 4 is a configuration diagram of a third embodiment.

FIG. 5 is a timing chart of the third embodiment.

FIG. 6 is a configuration diagram of a fourth embodiment.

FIG. 7 is a timing chart of the fourth embodiment.

FIG. 8 is another configuration diagram of the fourth embodiment.

FIG. 9 is a schematic block diagram of a cyclic digital-analog converter.

FIG. 10 is a conceptual configuration diagram including a cyclic D / A conversion circuit and a sample and hold circuit.

11 is a timing diagram of FIG.

FIG. 12 is a configuration diagram of a conventional example.

FIG. 13 is a timing chart of a conventional example.

[Description of Reference Signs] 30: First Switch Element 31: First Input Terminal 32: First Capacitor 33: Second Switch Element 34: Second Input Terminal 35: Third Switch Element 36: Operational Amplifier 37: 4th switch element 38: 5th switch element 39: 2nd capacitor 40: 6th switch element 41: 3rd input terminal 42: 7th switch element 50: 1st switch element 51: 1st input terminal 52: 1st capacitor 53: 2nd switch element 54: 2nd input terminal 55: 3rd switch element 56: Operational amplifier 57: 4th switch element 58: 2nd capacitor 59 : 7th switch element 70: 1st switch element 71: 1st input terminal 72: 1st capacitor 73: 2nd switch element 74: 2nd input terminal 75: 3rd switch Switch element 76: operational amplifier 77: fourth switch element 78: second capacitor 79: seventh switch element 90: first switch element 91: first input terminal (also second input terminal) 92 : First Capacitor 93: Second Switch Element 95: Third Switch Element 96: Operational Amplifier 97: Fourth Switch Element 98: Fifth Switch Element 99: Second Capacitor 100: Sixth Switch Element 102: 7th switch element 200: 1st input terminal 201: 2nd input terminal

Claims (2)

[Claims] 1. A first switch element for turning on / off between a first input terminal and one end of a first capacitor, and turning on / off between a second input terminal and the other end of the first capacitor. A second switch element, a third switch element for turning on and off between a negative phase input of the operational amplifier and the other end of the first capacitor, an output of the operational amplifier and one end of the first capacitor A fourth switch element for turning on and off the switch, a fifth switch element for turning on and off between the other end of the second capacitor, one end of which is connected to the negative phase input of the operational amplifier, and the output of the operational amplifier, A sixth switch element for turning on and off between the third input terminal and the other end of the second capacitor, and a seventh switch element for turning on and off between the negative phase input and output of the operational amplifier. Characterized by Switched capacitor arithmetic circuit. 2. A first switch element for turning on / off between a first input terminal and one end of the first capacitor, and a on / off for turning between a second input terminal and the other end of the first capacitor. A second switch element, a third switch element for turning on and off between a negative phase input of the operational amplifier and the other end of the first capacitor, an output of the operational amplifier and one end of the first capacitor A fourth switch element for turning on and off the switch, a second capacitor connected between the negative phase input and the output of the operational amplifier, and a seventh switch for turning on and off the negative phase input and the output of the operational amplifier A switched capacitor arithmetic circuit, comprising: