JPH09102614A - Active matrix display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the OFF current of a switching circuit in an active matrix display. SOLUTION: Five thin film transistors 121-125, 126-130 are connected in series in picture element cells 132, 133. The thin film transistors 121-123 and 125-127 are connected with gate signal lines 134, 135 which are diffenet every rows. The thin film transistors 124, 125, 129, 130 are connected with a common capacitance line 136. When data are written on the picture elements 132, 133, a selection signal is inputted from the gate signal lines 134, 135, and makes the thin film transistors 121-123 and 125-127 function as switching elements. Further a suitable potential is applied from the capacitance line 136, and makes the thin film transistors 124, 125, 129, 130 function as capacitors. Thereby the discharge amount from the picture element cells 132, 133 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device such as a liquid crystal display device, a plasma display device and an EL display device.

[0002]

2. Description of the Related Art FIG. 13A is a schematic view of a conventional active matrix display device, and a region shown by a broken line is a display region 104 in which thin film transistors 101 are arranged in a matrix. Thin film transistor 10
The source electrode of No. 1 is connected to the image (data) signal line 106, and the gate electrode of the thin film transistor 101 is connected to the gate (selection) signal line 105. Gate signal line 10
5. A plurality of image signal lines 106 are arranged so as to be substantially perpendicular to each other, and are connected to peripheral circuits 107 and 108, which are shift registers and the like, respectively.

The auxiliary capacitance 102 is a capacitor for reinforcing the capacitance of the pixel cell 103 and is used for holding image data. The thin film transistor 101 is used to switch the image data of the voltage applied to the pixel cell 103.

It is generally known that when a reverse bias voltage is applied to the gate of the thin film transistor 101, a leak current (referred to as an OFF current) flows instead of a state in which no current flows between the source and drain (OFF state). However, there is a problem that the potential of the pixel cell 103 changes due to the leakage current.

When the thin film transistor 101 is an N channel type, it is formed between the P type layer induced on the surface of the semiconductor thin film when the gate is negatively biased and the N type layers of the source region and the drain region. Although a PN junction occurs, many traps exist in the semiconductor thin film,
This PN junction is incomplete and junction leak current easily flows. The OFF current increases as the gate electrode is biased more negatively because the carrier concentration of the P-type layer formed on the surface of the semiconductor thin film increases and the width of the energy barrier of the PN junction narrows. This is because the concentration occurs and the junction leak current increases.

The OFF current thus generated largely depends on the source / drain voltage, and it is known that the OFF current dramatically increases as the voltage applied between the source / drain of the thin film transistor increases. Has been. For example, in the case of applying a voltage of 5 V between the source and the drain and the case of applying a voltage of 10 V, the latter O
The FF current may be 10 times or 100 times that of the former, not twice. Further, the non-linear fluctuation of the OFF current also depends on the gate voltage, and in general, when the reverse bias value of the gate voltage is large (in the N-channel type, a large negative voltage), the difference between the two is remarkable.

In order to solve this problem, for example, a method of connecting thin film transistors in series (multigate method) has been proposed, as described in JP-B-5-44195 and JP-B-5-44196. . This is intended to reduce the OFF current of each thin film transistor by reducing the voltage applied to the source / drain of each thin film transistor. For example, two thin film transistors 11 as shown in FIG.
When 1 and 112 are connected in series to the pixel cell 103, the voltage applied to the source / drain of each thin film transistor 111 and 112 becomes half. If the voltage applied to the source / drain is halved, it turns off from the above discussion.
The current can be 1/10 or 1/100. Note that FIG.
13B, the same reference numerals as those in FIG. 13A indicate the same members.

[0008]

However, if the characteristics required for displaying an image on a liquid crystal display become strict, it becomes difficult to reduce the OFF current as much as necessary even in the above multigate method. That is, even if the number of gate electrodes (number of thin film transistors) is increased to 3, 4, and 5, the voltage applied to the source / drain of the thin film transistor is 1/3, 1/4, 1/5. This is because it only decreases little by little. In addition, since the number of thin film transistors is increased, the circuit becomes complicated and the occupied area increases,
There is also a problem of lowering the aperture ratio.

The present invention has been made in view of the above problems, and has a simple structure, the voltage applied to the source / drain of a thin film transistor connected to a pixel electrode is 1/10 of that in a normal case. Below, preferably 1/100
The following is to provide an active matrix display device capable of reducing the OFF current of a thin film transistor.

[0010]

In order to solve the above-mentioned problems, one of the configurations of the active matrix display device according to the present invention is to provide image signal lines and gate signal lines arranged in a matrix, and the above-mentioned image. A pixel electrode arranged in a region surrounded by a signal line and a gate signal line, and n thin-film transistors of the same conductivity type are arranged in series adjacent to the pixel electrode. A source or drain region of the n = 1st thin film transistor of the plurality of thin film transistors is connected to the image signal line, and a drain or source region of the nth thin film transistor of the plurality of thin film transistors is connected to the pixel electrode. The gate electrodes of the m (n> m) thin film transistors are commonly connected to the gate signal line.
In the m thin film transistors other than the m thin film transistors, the gate electrodes of the thin film transistors connected to the pixel electrodes in the odd rows and the gate electrodes of the thin film transistors connected to the pixel electrodes in the even rows are connected to the same capacitance line, The potential of the gate electrode connected to the capacitance line is fixed by the capacitance line to a potential at which the channel formation region has the same conductivity type as the source and drain regions.

In the above structure, n and m are natural numbers except 0. N = 5 to obtain the desired effect
It is preferable that it is above.

FIG. 1 shows a specific configuration example of the above configuration.
In the configuration shown in FIG. 1, n = 5 and m = 2, and
The n = 5 thin film transistors denoted by 21 to 125 and 126 to 130 are connected in series to the pixel cells 132 and 133, respectively.

N = 1th thin film transistor 121, 1
The source region of 26 is connected to the image signal line 129, and the drain regions of the n-th (fifth) thin film transistors 125 and 128 are connected to one electrode (pixel electrode) of the pixel cells 132 and 133, respectively.

Further, in the active matrix display device of the present invention, among the n thin film transistors connected to different pixel electrodes, (n−m) thin film transistors are connected to the gate signal line, and the other m thin film transistors are It is connected to the capacitance line, but the gate signal line is different for each row,
The capacitance line is shared by the odd and even rows.

Specifically, as shown in FIG. 1, the gate electrodes of the three ((n−m)) thin film transistors 121 to 123 are connected to the gate signal line 134, and the gate electrodes of the thin film transistors 126 to 128 are. Gate signal line 1
35 is connected. On the other hand, the gate electrodes of the two (m) thin film transistors 124 and 125 and the gate electrodes of the thin film transistors 129 and 130 are connected to a common capacitance line 136 so that the gate potential is held at an appropriate potential. ing.

In the above structure, the pixel cells 132, 1
By holding the capacitance line 136 at an appropriate potential while 33 holds the potential, the thin film transistors 1 in the adjacent rows are
Capacitors are formed between the channels of 24, 125 and 129, 130 and the gate electrodes to suppress the voltage drop of the pixel cells 132, 133.

In the present invention, particularly, when the thin film transistor connected to the gate signal line has the LDD structure and further the offset structure, the OFF current is reduced, which is effective.

According to another structure of the present invention, a pair of adjacent pixel electrodes, a pair of gate signal lines arranged between the pair of pixel electrodes, and a pair of gate signal lines are arranged. A capacitor line and a pair of island-shaped semiconductor regions connected to the pair of pixel electrodes, respectively, and one end of the island-shaped semiconductor region is connected to the pixel electrode. Each of the gate signal lines crosses each of the island-shaped semiconductor regions at three or more regions, and the capacitance line crosses each of the island-shaped semiconductor regions at two or more regions. An active matrix display device characterized by:

FIG. 8 shows a specific configuration example of the above configuration.
FIG. 8 shows a pair of adjacent pixel electrodes 216 and 217.
A pair of gate signal lines 205 and 206 arranged between a pair of adjacent electrodes 216 and 217, a capacitance line 209 arranged between the pair of gate signal lines, and a pair of pixel electrodes 216. 217, each of which has a pair of island-shaped semiconductor regions 201 and 202 (which form an active layer of a thin film transistor), and one end of each of the island-shaped semiconductor regions 201 and 202 has the pixel electrode 216.
And 217 and is connected to the pair of gate signal lines 2
05 and 206 respectively cross the respective island-shaped semiconductor regions 201 and 202 in three regions, and the capacitance line 209 crosses the respective island-shaped semiconductor regions 201 and 202 in two regions. It has a structure.

When the above configuration is adopted, one capacitance line is commonly used for the pair of pixel electrodes, so that the aperture ratio of the pixel can be increased. In FIG.
Although only the minimum configuration is shown, an actual liquid crystal display employs a configuration in which the configuration shown in FIG. 8 is repeatedly combined in a number of several hundreds × several hundreds.

The basic idea of the invention disclosed in this specification is that, as shown in FIG.
5 are connected in series, of which the thin film transistor 121
The gates of 123 to 123 are connected to the gate signal line 134, and the gates of the other thin film transistors 124 and 125 are connected to the capacitance line 13.
6 to connect. Further, the capacitance lines are shared by the odd-numbered rows and the even-numbered rows, and the number of the capacitance lines is ½ of the number of rows to improve the aperture ratio of the pixels.

When the potential of the pixel is held, by holding the capacitance line 136 at an appropriate potential, a capacitance is formed between the channels of the thin film transistors 124 and 125 and the gate electrodes, so that the thin film transistors 122 and 123 are formed.
The voltage appearing between the source and drain of the
The OFF current of these thin film transistors can be reduced. The auxiliary capacity is not always necessary.
Rather, since it increases the load at the time of writing, the capacitance of the pixel cell 132 and the thin film transistor 124,
In some cases, it may not be preferable if the ratio of the capacity generated in 125 is optimum.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIG. When the selection signal is sent to the gate signal line 134, all the thin film transistors 121 to 123 are turned on. Further, at this time, a signal needs to be applied to the capacitor line 136 so that the thin film transistors 124 and 125 are also turned on. As a result, the image signal line 131
In response to the signal, the pixel cell 132 is charged, and at the same time, the thin film transistors 124 and 125 are also charged.
At the fully charged (balanced) stage, the source / drain voltages of the thin film transistors 124 and 125 are substantially equal.

When the selection signal is turned off in this state, all the thin film transistors 121 to 123 are turned off.
The thin film transistors 124 and 125 are still in the ON state. After that, a signal of another pixel is applied to the image signal line 131 and the thin film transistor 121 has a finite OFF current, so that the charge charged in the thin film transistor 124 is discharged and the voltage is lowered. But,
This speed progresses at the same speed as the voltage drop of the capacitor 102 of the normal active matrix circuit shown in FIG.

On the other hand, regarding the thin film transistor 122, since the source / drain voltage was almost 0 at the beginning, the OFF current was extremely small, but thereafter, the voltage of the thin film transistor 124 dropped, so that the source / drain was gradually increased. OFF as the voltage between drains increases
The current will also gradually increase. Regarding the thin film transistor 123 as well, since the voltage of the thin film transistor 124 drops, the OFF current also gradually increases, but needless to say, the speed thereof is smaller than that of the thin film transistor 122. From the above, it goes without saying that the voltage drop of the pixel cell 127 due to the increase of the OFF currents of the thin film transistors 121 to 123 is sufficiently slower than that in the normal active matrix circuit shown in FIG.

Generally, the deterioration of the thin film transistor is caused by source /
Although it depends on the voltage between the drains, in the present invention, since the voltage between the source / drain of the thin film transistors 122 and 123 and the thin film transistors 126 and 127 of FIG. Can be suppressed.

In the circuit shown in FIG. 1, a gate signal line 134 and a capacitance line 136 are provided in a substantially M-shaped semiconductor region 100 shown in FIG. 3A, as shown in FIGS. By arranging the layers overlapping with each other, a high degree of integration can be achieved. 3B to 3D show an M-shaped semiconductor region 10.
The possible arrangement relationship of the gate signal line 134 and the capacitance line 136 with respect to 0 is shown. Whichever is adopted, the effect of the present invention can be obtained similarly.

FIG. 3B shows the most orthodox arrangement, in which the semiconductor region 100 and the gate signal line 134 and the capacitance line 136 intersect each other, so that the thin film transistor 12 is formed.
1-125 are the intersections (three intersections with the gate signal line,
It is formed at two intersections with the capacitance line, five in total). In the semiconductor region 100, the gate signal line 134 and the capacitance line 13
N-type or P-type impurities are introduced into the regions (there are four in FIG. 3B) separated (sandwiched) by 6 and the thin film transistors 121 to 125. Source / drain. The image signal line 131 and the pixel electrode of the pixel cell 132 may be formed so as to be connected to either end of the semiconductor region 100.

On the other hand, as shown in FIG. 3C, it is possible that the points a and b are not covered with the capacitance line 136. This is because it is sufficient for the thin film transistors 124 and 125 to function only as capacitors. Further, as shown in FIG. 3D, it is possible to form six switching points with the semiconductor region 100 and form a switching element in which six thin film transistors 301 to 306 are connected in series. In this case, an equivalent circuit diagram of the matrix circuit is shown in FIG.

In FIG. 2, the same reference numerals as those in FIG. 1 indicate the same members. Further, FIG. 2 also shows six thin film transistors 307 to 312 connected in series to the pixel cell 133. The circuit configuration diagram shown in FIG. 2 corresponds to the one in which the thin film transistor 122 (127) in FIG. 1 is replaced by two thin film transistors 302, 302 (308, 309) in series. For this reason, it is better than the circuit of FIG.
The FF current can be further reduced.

[0031]

【Example】

Example 1 This example relates to a manufacturing process of a switching circuit of a pixel cell, and the manufacturing process will be described to deepen the understanding of the present invention. This embodiment describes a manufacturing process of a switching circuit including thin film transistors 121 to 125 in the switching circuit shown in FIG. 1. FIGS. 3A and 3B are portions showing the manufacturing process of the switching circuit. FIG. 4A to 4C are cross-sectional views in each manufacturing process. In FIG. 4, a left side shows a cross section of a portion indicated by a dotted line XY in FIG. A cross section of a portion indicated by Y ′ is shown. It should be noted that XY and X'-Y 'are not collinear, although they are drawn adjacent in FIG.

This embodiment is characterized in that an offset gate is formed by anodizing the gate electrode to further reduce the OFF current. A technique for anodizing the gate electrode is disclosed in Japanese Patent Laid-Open No. 5-267667. Of course, a gate electrode having a structure that is normally used can also be used in the present invention.

As shown in FIG. 4A, a silicon oxide film 152 as a base film is formed on a substrate 151 (Corning 7059, 100 mm × 100 mm) by 1000 to 5000 Å.
For example, the film was formed at 3000Å. To form the silicon oxide film 152, TEOS is decomposed by a plasma CVD method.
It was deposited and formed into a film. Further, this step may be performed by a sputtering method.

After that, an amorphous silicon film of 300 to 1500 is formed by a plasma CVD method or an LPCVD method.
Å, for example, 500 Å is deposited and this is 550-600 ℃
It was left to stand for 8 to 24 hours to crystallize. At that time, a small amount of nickel may be added to promote crystallization. Japanese Patent Application Laid-Open No. 6-244104 discloses a technique for promoting crystallization by adding nickel or the like to lower or shorten the crystallization temperature / crystallization time. This step may be performed by optical annealing such as laser irradiation. Also, thermal annealing and optical annealing may be combined.

The crystallized silicon film is etched to form an approximately M-shaped island-shaped region 100 shown in FIG. 3A, on which a gate insulating film 153, plasma C, is formed.
The thickness is 700 to 1500Å, for example, 12 by the VD method.
A 00Å silicon oxide film was formed. This step may be performed by a sputtering method.

Thereafter, an aluminum (containing 1 wt% Si or 0.1 to 0.3 wt% Sc) film having a thickness of 1000 Å to 3 μm, for example 5000 Å, is formed by the sputtering method, and then, as shown in FIG. As shown in FIG. 4B, this was etched to form a gate signal line 134 and a capacitance line 136. All of these become gate electrodes of thin film transistors.

At this stage, as shown in FIG.
Etching is performed so that all the other gate signal lines 134 and the capacitor lines 136 (corresponding to the aluminum wiring 602 in FIG. 5) on 1 are connected to the aluminum film region 604 formed around the active matrix region 603. However, at this time, it is preferable to design the aluminum wiring such as the gate electrode of the thin film transistor forming the peripheral circuits such as the gate driver 605 and the source driver 606 so as to be insulated from the aluminum film region 604. This is to prevent the electrodes and wirings of the thin film transistors of the peripheral circuit from being anodized to improve the degree of integration.

Then, as shown in FIG. 4C, a current is applied to the gate electrode (gate signal line 134, capacitance line 136) in an electrolytic solution to cause anodization, and the thickness is 500 to 2500.
Å, for example, 2000 Å anodized oxide 154, 155 was formed. The electrolytic solution used was prepared by diluting L-tartaric acid with ethylene glycol to a concentration of 5% and adding p with ammonia.
H is adjusted to 7.0 ± 0.2. The substrate is immersed in the solution, the + side of the constant current source is connected to the gate electrode on the substrate, the platinum electrode is connected to the-side, and voltage is applied at a constant current of 20 mA until 150V is reached. Oxidation was continued. Furthermore, in a constant voltage state of 150 V, the current is 0.
Oxidation was continued until it became 1 mA or less. As a result, a thickness of 2000 Å is formed on the gate signal line 134 and the capacitance line 136.
Anodic oxides 154, 155 are formed.

Then, as shown in FIG. 4D, the gate electrode portion (that is, the gate signal line 134, the capacitance line 136, and the anodic oxides 153 and 155 around them) is formed in the island region 100 by the ion doping method. ) Is used as a mask to implant impurities (here, phosphorus) in a self-aligned manner to form N-type impurity regions 156 to 159. Here, phosphine (PH ₃ ) was used as the doping gas. In this case, the dose amount may be 1 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage may be 60 to 90 kV. For example,
Dose amount is 1 × 10 ¹⁵ atoms / cm ² , acceleration voltage is 80 k
V. As a result, N-type impurity regions 156 to 159 were formed.

Further, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec) was irradiated to activate the doped impurity regions 156 to 159. Laser energy density is 200-400m
J / cm ² , preferably 250 to 300 mJ / cm ^2, was suitable. This step may be performed by thermal annealing. In particular, it contains a catalytic element (nickel),
It can be activated by thermal annealing at a lower temperature than in the usual case (JP-A-6-267989).

In this way, the N-type impurity regions 156-1 are formed.
59 is formed, and the thin film transistors 121, 123,
It can be seen that 124 and 125 are formed. Further, a thin film transistor 122 (not shown) having the gate signal line 134 as a gate electrode is also formed. These thin film transistors 121 to 125 have anodic oxides 154 and 1
The impurity regions 156 to 159 are distant from the gate electrode by the thickness of 55, forming a so-called offset gate structure.

As shown in FIG. 4E, the interlayer insulating film 16 is formed.
0 was used to form a silicon oxide film with a thickness of 5000 Å by the plasma CVD method. At this time, TEOS is used as the source gas.
And oxygen was used. Then, the interlayer insulating film 160 and the gate insulating film 153 are etched, and the N-type impurity region 1 is formed.
A contact hole was formed at 56, that is, at the source of the thin film transistor 121. After that, an aluminum film was formed by a sputtering method and etched to form a source electrode / wiring 161. This is the image signal line 13 shown in FIG.
1 corresponds to the extension.

As shown in FIG. 4F, a passivation film 162 was formed. Here, NH ₃ / SiH ₄ /
A silicon nitride film having a film thickness of 2000 to 8000 Å, for example, 4000 Å was formed by a plasma CVD method using H ₂ mixed gas to form a passivation film. And
The passivation film 162, the interlayer insulating film 160, and the gate insulating film 153 are etched to form an N-type impurity region 159.
A contact hole with the pixel electrode 163 was formed in the drain of the thin film transistor 125.

And indium tin oxide (ITO)
A film was formed by a sputtering method and this was etched to form the pixel electrode 163. The pixel electrode 163 is one of the electrodes of the pixel cell 132. Through the above steps, the N-channel thin film transistors 121 to 125 connected in series shown in FIG.
An active matrix circuit element composed of (126 to 130) is formed.

[Embodiment 2] FIGS. 6 to 8 are top views for explaining a manufacturing process of a switching element of this embodiment. For the specific process, a known technique or Example 1 is used.
Since the technique shown in 1 may be used, it will not be described in detail here. An equivalent circuit of the switching circuit of this embodiment is shown in FIG.

As shown in FIG. 6, by patterning the crystalline silicon film, semiconductor regions (active layers) 201 to 204 each having a substantially M shape as described in Example 1 or FIG.
Is formed at a predetermined position. After that, a gate insulating film (not shown) is formed. The gate signal lines 205 to 208 arranged in parallel, the capacitance line 209 arranged in parallel between the gate signal lines 205 and 206, and the gate signal line 207.
And 208, the capacitance lines 210 arranged in parallel are formed respectively.

Here, the positional relationship between the gate signal lines 205 to 208 and the capacitance lines 209 and 210 and the active layers 201 to 204 is the same as that of the first embodiment.
204 intersects with gate signal lines 205 to 208 at three places, active layers 201 and 202 intersect with common capacitance line 209 at two places, and active layers 203 and 204 respectively share common capacitance line 210 with two places. Cross.

As shown in FIG. 7, active layers 201-204
After doping an impurity imparting an N-type or P-type conductivity to form an interlayer insulator (not shown), the active layer 2
Contact holes 211 are provided at one end of each of 01 to 204.
To 214 are formed, and the image signal line 215 is formed.

Next, as shown in FIG. 8, active layers 201 to 2
A contact hole is formed at the other end of the gate electrode 04, and pixel electrodes 216 to 219 are formed in a region surrounded by the gate signal lines 205 to 208 and the image signal line 215 so as to be connected to the other ends of the active layers 201 to 204.

Through the above steps, the switching element of the active matrix circuit is formed. In this embodiment, a pair of pixel electrodes 216 and 217 (218 and 219)
On the other hand, since one capacitance line 209 (210) is commonly used, the number of capacitance lines can be reduced to half the number of gate signal lines, so that the aperture ratio of the pixel can be increased. Although only the minimum configuration is shown in FIG. 8, in an actual liquid crystal display, a configuration in which the configuration shown in FIG. 8 is repeatedly combined in the number of several hundreds × several hundreds is adopted. .

The equivalent circuit of the active matrix circuit of FIG. 8 corresponds to that of FIG.
5 corresponds to the gate signal lines 134 and 135, and the capacitance line 20
9 corresponds to the capacitance line 136. Further, the active layer 201, the gate signal line 205, and the capacitor line 209 form thin film transistors 121 to 125. The active layer 202, the gate signal line 206, and the capacitor line 209 form the thin film transistor 126.
~ 130 are configured. In addition, the pixel electrodes 216 and 217
Corresponds to one of the electrodes of the pixel cells 132 and 133, respectively.

In order to further improve the aperture ratio, FIG.
FIG. 9A shows a schematic M-shaped active layer 221 shown in FIG.
As shown in (B), the bent portion of the active layer 221 is entirely covered with the capacitance line 222 and the gate signal line 223,
Further, it is also effective to overlap a part of the thin film transistor formed in the active layer 221 with the image signal line 224 as shown in FIG.

Furthermore, by increasing the bending of the active layer and increasing the number of intersections of the active layer with the gate signal lines and the capacitance lines, more transistors can be formed. As a result, it becomes possible to further reduce the OFF current. For example, as shown in FIG. 10A, FIG.
By patterning the active layer 301 with one more bent portion than the island-shaped active layer shown in FIG.
By overlapping the gate signal line 302 and the capacitance line 303 as described above, six thin film transistors functioning as switching elements can be formed, and three thin film transistors functioning as capacitors can be formed.

[Third Embodiment] FIG. 11 is a top view of an active matrix circuit of the present embodiment, which is a modification of the switching circuit of the second embodiment. 11, the same reference numerals as those in FIG. 8 indicate the same members. The equivalent circuit of the present embodiment has the circuit configuration shown in FIG. 1 as in the second embodiment.

The structure shown in FIG. 11 is characterized in the way of using a common capacitance line in two pixels. In the second embodiment shown in FIG. 8, the active layers 201 and 202, the active layer 20
3 and 204 are arranged point-symmetrically with respect to the capacitance lines 209 and 210, respectively, and the capacitance lines 209 and 210 and the active layer 201 are arranged.
Areas intersecting with .about.204 are arranged in parallel in the longitudinal direction of the capacitance lines 209 and 210.

On the other hand, in this embodiment, as shown in FIG. 11, the active layers 201 and 202 or the active layers 203 and 204 are arranged in line symmetry with respect to the capacitance lines 209 and 210, and the capacitance line 20
Areas where 9 and 210 intersect the active layers 201 to 204 are arranged in the width direction of the capacitance lines 209 and 210. As a result, the degree of integration of the matrix circuit can be increased. Further, since one capacitance line 209 is commonly used for the pair of pixel electrodes 216 and 217,
Since the number of capacitance lines can be half the number of gate signal lines, the aperture ratio of pixels can be increased.

[Fourth Embodiment] FIG. 12 is a top view of an active matrix circuit of the present embodiment, which is another modification of the switching circuit of the second embodiment. In FIG. 12, FIG.
The same reference numerals as in FIG. The equivalent circuit of the present embodiment has the circuit configuration shown in FIG. 1 as in the second embodiment.

As shown in FIG. 12, as in the second embodiment,
The active layers 201 and 202 and the active layers 203 and 204 are arranged point-symmetrically with respect to the capacitance lines 209 and 210, and the regions where the capacitance lines 209 and 210 intersect the active layers 201 to 204 are the capacitance lines 209 and 210. Although arranged in the longitudinal direction, in the present embodiment, the active layers 201 and 202 and the active layer 20 are arranged.
3 and 204 are arranged to enter each other's area. Thereby, the aperture ratio of the pixel can be increased.
Furthermore, since one capacitance line 209 is commonly used for the pair of pixel electrodes 216 and 217, the number of capacitance lines can be halved to the number of gate signal lines. Can be increased.

In the first to fourth embodiments, the structure of the thin film transistor has been described centering on the top gate type, but the bottom gate type and other structures also have the same OFF current. Can be reduced.

Particularly in the top gate type thin film transistor, the thin semiconductor region (active layer) has a complicated shape, while the gate electrode and the like have an extremely simple shape, so that disconnection of the upper layer wiring can be prevented. It has the advantage. On the contrary, if the gate electrode has a complicated shape, it will be a cause of lowering the aperture ratio.

[0061]

As described above, in the active matrix display device according to the present invention, the voltage drop of the liquid crystal cell can be suppressed by connecting the gates of a plurality of thin film transistors connected in series to the gate signal line or the capacitance line. . Furthermore, since one capacitance line is commonly used for a pair of pixel electrodes, the number of capacitance lines can be halved to the number of gate signal lines, thus increasing the aperture ratio of the pixel. it can.

Generally, the deterioration of the thin film transistor is caused by source /
Although it depends on the voltage between the drains, in the present invention, since the voltage between the source / drain of the thin film transistor connected to the gate signal line can be kept low during all driving processes, deterioration of the thin film transistor is prevented. be able to.

The present invention is effective in applications in which higher image display is required. That is, in the case of expressing extremely delicate shades of 256 gradations or more, it is necessary to suppress the discharge of the liquid crystal cell to 1% or less during one frame. None of the conventional methods shown in FIGS. 13A and 13B are suitable for this purpose.

The present invention is also suitable for an active matrix display device using a thin film transistor of a crystalline silicon semiconductor, which is particularly suitable for the purpose of displaying a matrix having a large number of rows. Generally, in a matrix having a large number of rows, the selection time per row is short, and therefore an amorphous silicon semiconductor thin film transistor is not suitable for use. However, there is a problem that a thin film transistor using a crystalline silicon semiconductor has a large OFF current.

Therefore, the present invention capable of reducing the OFF current can make a great contribution also in this field. Needless to say, the thin film transistor using an amorphous silicon semiconductor is also effective.

As described above, the present invention can be implemented by changing the manufacturing process of the conventional active matrix circuit to the minimum, and a great effect can be obtained. Thus, the present invention is an industrially useful invention.

[Brief description of the drawings]

FIG. 1 is a switching circuit diagram of an active matrix display device of the present invention.

FIG. 2 is a switching circuit diagram of the active matrix display device of the present invention.

FIG. 3 shows an arrangement example of a semiconductor region, a gate signal line, and a capacitance line of the present invention.

FIG. 4 shows a manufacturing process (cross section) of the switching element in the first embodiment.

FIG. 5 shows an arrangement example of a gate signal line, a capacitance line and the like and a peripheral circuit of the first embodiment.

FIG. 6 shows a manufacturing process (upper surface) of a switching element according to a second embodiment.

FIG. 7 shows a manufacturing process (upper surface) of a switching element in Example 2.

FIG. 8 shows a manufacturing process (upper surface) of a switching element according to a second embodiment.

FIG. 9 is a modification of the second embodiment and shows an arrangement example of a semiconductor region, a gate signal line, and a capacitance line.

FIG. 10 is a modification of the semiconductor region of the second embodiment and shows an example of arrangement of gate signal lines and capacitance lines.

FIG. 11 shows an arrangement example of a semiconductor region, a gate signal line, and a capacitance line of the third embodiment.

FIG. 12 shows an arrangement example of a semiconductor region, a gate signal line, and a capacitance line of Example 4.

FIG. 13 is a switching circuit diagram of a conventional active matrix display device.

[Explanation of symbols]

 100 ... Semiconductor regions 121 to 130 ... Thin film transistor 131 ... Image signal lines 132, 133 ... Pixel cells 134, 135 ... Gate signal line 136 ...・ ・ ・ Capacitance lines 154, 155 ・ ・ ・ Anodic oxides 156 to 159 ・ ・ ・ N type impurity region 160 ・ ・ ・ ・ Interlayer insulating film 161 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Source electrode / wiring 162・ ・ ・ ・ ・ Passivation film 163 ・ ・ ・ ・ ・ Pixel electrodes 201 to 204 ・ ・ ・ Active layers 205 to 208 ・ ・ ・ Gate signal lines 209, 210 ・ ・ ・ Capacitance lines 211 to 214 ・ ・ ・ Contact holes 215 ... Image signal lines 216 to 219 ... Pixel electrodes

Claims (8)

[Claims] 1. An image signal line and a gate signal line arranged in a matrix, and a pixel electrode arranged in a region surrounded by the image signal line and the gate signal line, the pixel signal line being in series with the pixel electrode. N of the same conductivity type (n
Is a natural number greater than or equal to 1), and in the n thin film transistors, the source or drain region of the n = 1st thin film transistor is connected to the image signal line, and the nth thin film transistor. Drain or source regions of the thin film transistors are connected to the pixel electrodes, and gate electrodes of nm (n> m) thin film transistors are connected to a common gate signal line, and m thin film transistors other than the nm thin film transistors are connected. In, the gate electrode of the thin film transistor connected to the pixel electrode in the odd-numbered row and the gate electrode of the thin film transistor connected to the pixel electrode in the even-numbered row are connected to the same capacitance line, and the channel formation region is formed by the capacitance line And a gate electrode to the same conductivity type as the drain region. An active matrix display device characterized by but fixed. 2. An image signal line and a gate signal line which are arranged in a matrix, and a pixel electrode which is arranged in a region surrounded by the image signal line and the gate signal line. N of the same conductivity type (n
Is a natural number greater than or equal to 1), and in the n thin film transistors, the source or drain region of the n = 1st thin film transistor is connected to the image signal line, and the nth thin film transistor. The drain or source region of the thin film transistor is connected to the pixel electrode, the gate electrodes of at least two thin film transistors of the thin film transistors connected in series are connected to different gate signal lines for each row, and the gate electrodes of the other thin film transistors are odd rows. And an even-numbered row are connected to the same capacitance line, and the capacitance potential fixes the gate potential to a potential at which the channel formation region has the same conductivity type as the source and drain regions. 3. A plurality of image signal lines, a plurality of gate signal lines arranged substantially perpendicular to the image signal lines, and a plurality of gate signal lines in odd rows and parallel gate signal lines in even rows. An active matrix display device having a plurality of capacitance lines, a pixel electrode provided in a region surrounded by the gate signal line and the image signal line, and a switching element provided so as to be connected to each of the pixel electrodes. In each of the switching elements, each of the switching elements has one semiconductor film having a substantially M-shape, and the semiconductor film has at least three overlapping portions with the gate signal line to form switching elements in odd-numbered rows. The semiconductor film and the semiconductor film forming the even-numbered switching elements have at least two overlapping portions with the common capacitance line. Matrix display device. 4. A plurality of image signal lines, a plurality of gate signal lines arranged substantially perpendicular to the image signal lines, and one line between the odd-numbered gate signal lines and the even-numbered gate signal lines. An active element having a capacitor line arranged in parallel with each other, a pixel electrode provided in a region surrounded by the gate signal line and the image signal line, and a switching element provided so as to be connected to each of the pixel electrodes. In the matrix display device, each of the switching elements has one semiconductor film having a substantially M shape, and in the semiconductor film, a region having a contact with the image signal line and a region having a contact with the pixel electrode. , The four or more regions separated by the capacitance line and the gate signal line each have an N-type or P-type conductivity type, and the semiconductor film has the gate signal different for each row. Are separated with the line, and an active matrix display device characterized by being separated by a common said capacitance line in odd-numbered rows and even-numbered rows. 5. The active matrix display according to claim 1, wherein the capacitance lines are arranged in parallel between the gate signal lines of odd rows and the gate signal lines of even rows. apparatus. 6. The active matrix display device according to claim 1, wherein the capacitance line does not overlap with a pixel in a corresponding row but overlaps with a pixel in a row adjacent to the relevant row. 7. A pair of adjacent pixel electrodes, a pair of gate signal lines arranged between the pair of pixel electrodes, a capacitance line arranged between the pair of gate signal lines, and a pair of the pair of gate signal lines. In an active matrix display device having a pair of island-shaped semiconductor regions connected to each of the pixel electrodes, one end of the island-shaped semiconductor region is connected to the pixel electrode, Each of them crosses each of the island-shaped semiconductor regions at three or more regions, and the capacitance line crosses each of the island-shaped semiconductor regions at two or more regions. Active matrix display device. 8. The image signal line according to claim 7, wherein the image signal line is arranged so as to be substantially orthogonal to the gate signal line, and the image signal line is connected to the other end of the island-shaped semiconductor region. An active matrix display device characterized by: