JPH09101931A - Network system controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate a local data buffer, to eliminate the degradation of a main memory access function for a CPU and further to accelerate the processing speed of network data by always detecting whether main memory access from a main control part is generated or not by a main memory access means. SOLUTION: When it is confirmed that the main memory access from a CPU 11 is not generated, the copy of data held in a data buffer 104 through DMA transfer to a main storage part 12 is instructed to a memory control part 102 by a DMA control part 101. When it is confirmed that the main memory access due to the CPU 11 is generated, on the other hand, it is retrieved whether the data related to the main memory access are held in the data buffer 104 or not. When the relevant data are retrieved, the CPU 11 switches the main memory access to access to the data buffer 104 through a CPU interface part 103, and the retrieved data are transferred to the CPU 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network system control device for storing data received from a network in a main storage unit, reading the stored data, and controlling the network system for processing by the main control unit. is there.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a conventional network system control device. The network system control device comprises a system control circuit 20 and a network control circuit 23 connected to the system control circuit 20 via an expansion bus 24. Further, the system control circuit 20 includes a CPU 21 and a main unit. The memory 22 is connected. Then, the network data received by the network control circuit 23 is DMA-transferred to the main memory 22 by the system control circuit 20, and the main memory 22
Read the network data stored in
Data processing is performed at 21.

The system control circuit 20 receives data from the network control circuit 23 via the CPU interface section 203 for connecting to the CPU 21, the memory control section 202 for connecting to the main memory 22, and the expansion bus 24. It is composed of a DMA control unit 201 for fetching. Further, the network control circuit 23 is provided with a local data buffer 231 that temporarily holds data received from the network.

As a network connected to the network control circuit 23, for example, Ethernet (Etherne
t) is used. Ethernet is a representative bus type LAN created by IEEE (Institute of Electrical and Electronics Engineers) 802.3, and its transmission speed is 10 Mbps (more recently, high-speed Ethernet with a transmission speed of 100 Mbps has also appeared. ing). When connecting to such an Ethernet, the capacity of the local data buffer 231 is, for example, about 32 KB. As the capacity of the main memory 22, for example, a capacity of about 2 MB is used.

FIG. 7 is a flow chart showing the processing of network reception data in the conventional network system control apparatus shown in FIG. First, the network control circuit 23 receives data from the external network (S71), and temporarily stores it in the local data buffer 23.
It is stored in 1 (S72). At the same time, in order to DMA transfer the stored received data to the main memory 22, the DMA control unit 2
Issue an "expansion bus acquisition request" to 01 (S7)
3).

Here, DMA means Direct Memory Acce
Abbreviation of ss, in the example shown here, the network control circuit 23, which is a peripheral device having high-speed data transfer capability, is
Data is directly transferred to the main memory 22 without the control of the CPU 21. In this data transfer, the DMA control unit 201 makes the expansion bus 24
Is managed, and data transfer is controlled by this. The expansion bus 24 is speeded up in order to improve the data transfer rate, and for example, a PCI ((Peripheral Component Interconnect) bus or the like is used.

Subsequently, in the DMA control unit 201 which has received the "expansion bus acquisition request", it is confirmed that no other access request has been issued to the main memory 22 by the memory control unit 202 and the CPU interface unit 203. After confirming the above, the expansion bus 24 is sent to the network control circuit 23.
Grant the right to use. Therefore, when the use of the expansion bus 24 becomes possible (Yes in S74), the network control circuit 23 transfers the data held in the local data buffer 231 to the expansion bus 24.
Send up. Further, the DMA control unit 201 takes in the data on the expansion bus 24 and, via the memory control unit 202,
DMA transfer to the main memory 22. In this manner, the DMA of the data received from the external network to the main memory 22
The transfer is completed (S75).

In the local data buffer 231, the network control circuit 23 holds the received data so as not to lose the received data while the right to use the expansion bus 24 is not granted.

[0009]

As described above, in the conventional network system control device, the system control circuit 20 and the network control circuit 23 are individually configured and both of them are buses (the expansion bus in the above example). 24)
It is configured to work by connecting with. The network control circuit 23 directly connected to the network has a function of communicating with the network. For this reason, in the network control circuit 23, the local data buffer 2 that temporarily retains the data in order not to lose the received data until the right to use the expansion bus 24 is acquired.
It was necessary to have 31.

However, when the conventional structure in which the local data buffer 231 is provided in the network control circuit 23 is adopted, the effect of the cost burden of the network control circuit 23 on the entire network system control device is not small. That is, the main function of the network control circuit 23 is a data transmission / reception function (which is a normal terminal function), and by adding the memory function, the cost increase cannot be denied. There are facts that affect the increase in overall cost. However, to make the system control circuit 20 have all the functions of the network control circuit 23,
In particular, the processing load is increased when communicating with a plurality of networks, and the configuration of the system control circuit 20 is complicated.
It is hard to say that changing the current form of bus connection between the network control circuit 23 and the network control circuit 23 is a good idea.

Further, in the conventional network system control device, the CPU held in the middle of the DMA transfer of the data held in the local data buffer 231 to the main memory 22.
When a main memory access from the CPU 21 occurs, the data will be lost if the data transfer is interrupted in order to prioritize the access. Therefore, the main memory access of the CPU 21 is normally set to wait. Therefore, the CPU
It cannot be denied that the main memory access function of 21 is deteriorated.

On the contrary, if the CPU 21 is given priority to the main memory access, it is necessary to re-execute the communication procedure for acquiring the expansion bus 24 in order to restart the data transfer which has been canceled once. , Greatly delays data processing. The present invention has been made in view of such a situation, and while eliminating the local data buffer used in the conventional network system,
The deterioration of the main memory access function of the CPU is eliminated, and
It is an object of the present invention to provide a network system control device capable of improving the processing speed of network data.

[0013]

In order to achieve the above object, the invention as set forth in claim 1 stores data received from a network in a main storage unit and reads the stored data to read the main control unit. A network system control device for controlling a network system to be processed in, comprising: a data holding means for fetching and holding data received from a network; Means and the main memory access detection means, when it is detected that the main memory access by the main control unit has not occurred,
A data copy means for copying the data held in the data holding means to the main memory by DMA transfer and the main memory access detecting means have detected that a main memory access by the main controller has occurred. In this case, access data searching means for searching whether or not the data related to the access is held in the data holding means, and data for the main memory access by the main controller is searched by the access data searching means. Access data transfer means for transferring the data to the main control unit in the case of being processed.

According to a second aspect of the present invention, the data holding means in the network system control apparatus according to the first aspect further stores the data storage area of the main storage unit for the data received from the network. It is characterized in that it comprises an address assigning means for assigning an address associated with, and holds data according to the address assigned by the address assigning means.

According to a third aspect of the present invention, the data copy means in the network system control apparatus according to the second aspect further comprises the main control section by the main memory access detection means during data copy. Main memory access by the main controller is terminated by the main memory access detection means during the data copy interruption, and the data copy interruption means for interrupting the data copy when it is detected that the main memory access has occurred. And a data copy resuming means for resuming the data copy when it is detected.

According to a fourth aspect of the present invention, the access data search means in the network system control device according to the third aspect further comprises the address of the main memory access by the main control section, and the address giving means. Address determination means for determining whether or not it matches the address given by the address determination means. When the address determination means determines that the addresses match, the corresponding data is searched based on the address. It has a feature.

According to a fifth aspect of the present invention, the access data transfer means in the network system control apparatus according to the fourth aspect further causes main memory access by the main control section to the data holding means. An access destination switching unit for switching to access is provided, and when the access destination switching unit switches the main memory access by the main control unit to the access to the data holding unit, the corresponding data is sent to the main control unit. The feature is that it is transferred.

Further, the invention according to claim 6 is the network system control device according to claim 1, wherein when individual data transmitted from a plurality of networks are received and processed, further, The present invention is characterized in that it is provided with a data fetching order allocating means for allocating the data fetching order from each network to the data holding means for each network.

[0019]

According to the above configuration, in the present network system control device, when the data transmitted from the network is received, the received data is held by the data holding means. On the other hand, the main memory access detection means always detects whether or not the main memory access by the main control unit occurs. Then, the data copy means executes the data copy of the held data to the main memory unit in the interval of the main memory access.

When a main memory access occurs, the access data retrieval means retrieves whether or not the data related to the main memory access is held. Then, when the corresponding data is retrieved, the data is transferred to the main control unit by the access data transfer means. Furthermore, in the case of receiving and processing individual data transmitted from a plurality of networks, the data fetching order allocating means allocates the data fetching order to the data holding means for each network and allocates the data. Individual data is taken in during the time zone.

As a result of the above, when the data received from the network is transferred to the main memory, even if the main memory is accessed by the main controller, the main memory access is not interrupted. Further, in that case, when it is confirmed that the data related to the main memory access is held in the data holding means, the data holding means exerts the cache function of the main control unit to transfer the corresponding data. Therefore, the access time by the main control unit can be significantly shortened. Furthermore, when receiving and processing individual data transmitted from multiple networks, the order of data acquisition is pre-assigned in time, so individual data is taken in during the assigned time zone and data is retained. Incorporation of individual data into the instrument is carried out without hindrance.

[0022]

Embodiments of the present invention will be specifically described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a network system control device according to a first embodiment of the present invention, which is compared with the configuration of the conventional network system control device shown in FIG.

This network system control device includes a system control circuit 10 and a network control circuit 13 connected to the system control circuit 10 via an expansion bus 14.
And a CPU 11 and a main memory 12. Then, the data received from the external network is transferred to the main memory 12 by DMA and stored, and
The stored data is read out and the CPU 11 processes the data. Here, the network control circuit 13 is not provided with the local data buffer 231 shown in the conventional example.

The system control circuit 10 receives data from the network control circuit 13 via the CPU interface section 103 for connecting to the CPU 11, the memory control section 102 for connecting to the main memory 12, and the expansion bus 14. DMA control unit 101 for fetching the
The data buffer 104 temporarily holds the data taken in by the A control unit 101.

Here, as the capacity of the data buffer 104, for example, the same capacity as the local data buffer 231 shown in FIG. 6 is used, but this data buffer 104 is incorporated in the system control circuit 10. By incorporating it as a part, compared to the case of the conventional example,
It is possible to reduce the cost of the entire network system control device.

Further, for example, the capacity of the main memory 12 is 2 MB.
If the capacity of the data buffer 104 is about 32 KB, the access time of the CPU 11 with respect to the main memory 12 is about 150 to 200 ns.
The access time of the U11 with respect to the data buffer 104 is about 50 ns. This is because the main memory 12 is a large-capacity memory and is composed of a DRAM (Dynamic RAM), so the access time is slow, whereas the data buffer 10
This is because the register memory 4 is composed of SRAM (Static RAM) as a register memory, so that the access time is fast. The same applies to the case of writing data from the network control circuit 13 to the data buffer 104 and the case of transferring data from the data buffer 104 to the main memory 12.

Next, the operation of each functional block constituting the system control circuit 10 will be described (details will be described later). First, the DMA control unit 101 takes in the data received by the network control circuit 13, attaches an address to the data, and writes it in the data buffer 104. The address in this case is matched with the address corresponding to the data storage area of the main memory 12. Further, the CPU interface unit 103 constantly monitors whether or not a main memory access by the CPU 11 has occurred by detecting the presence or absence of a signal (address signal) on the CPU bus.

Next, in the DMA control unit 101, the CPU 1
When it is confirmed that the main memory access by 1 has not occurred, the memory control unit 102 is instructed to copy the data held in the data buffer 104 to the main memory 12 by DMA transfer. Then, the memory control unit 102 having received this instruction starts data copy. Since the memory control unit 102 is configured to perform data copy, the data in the data buffer 104 remains in the buffer even after the data copy is completed until there is no write space when the next data is input. Held in.

In addition, the DMA control unit 101, which has confirmed that the main memory access by the CPU 11 has occurred during the data copy, immediately notifies the memory control unit 102 of the fact.
Instruct to suspend data copy. Then, the memory control unit 102 receiving this instruction suspends the data copy being executed. After that, the DMA control unit 101, which has confirmed that the main memory access by the CPU 11 has ended, instructs the memory control unit 102 to resume the interrupted data copy. Then, the memory control unit 102 receiving this instruction restarts the data copy.

Since the data copy is controlled in this way, even when the main memory access by the CPU 11 occurs, it is surely executed and the data in the data buffer 104 is surely executed. Main memory 1
2 is transferred. On the other hand, in the data buffer 104, C
When it is confirmed through the PU interface unit 103 that the main memory access by the CPU 11 has occurred, the data related to the main memory access is the data buffer 10
4 is searched for. In that case, CP
It is searched whether the data at the same address as the main memory access address by U11 is held. Then, when the corresponding data is retrieved, the main memory access by the CPU 11 through the CPU interface unit 103 is switched to the access to the data buffer 104, and the retrieved data is transferred to the CPU 11.

As described above, the data buffer 104 is C
It also functions as a cache memory of the PU 11, and when the CPU 11 accesses the data buffer 104 at this time, the data buffer 104 uses the SRA.
Since it is composed of M, its access time is greatly shortened as compared with the case of the conventional example. FIG. 2 is a flowchart showing processing of network reception data in the network system control device shown in FIG. First, the network control circuit 13 receives data from the external network (S21). Then, the network control circuit 13 immediately outputs the received data to the expansion bus 14 (S22). Therefore, the DMA control unit 101 takes in the data output to the expansion bus 14 and stores it in a data storage area (corresponding to that of the main memory 12) defined in advance by the system inside the data buffer 104 ( S23).

Thereafter, in the DMA control unit 101, the CPU
The state of occurrence of access to the main memory 12 from the CPU 11
While confirming with the control signal of the interface unit 103 (S
24), in the meantime, that is, when the main memory access of the CPU 11 is not occurring (No in S24), the data transfer instruction is issued to the memory control unit 104, and the memory control unit At 104, the data stored in the data buffer 104 is copied to the main memory 12 (S25). In this way, the DMA transfer of network data is completed.

Regarding the network data for which the DMA transfer is completed, the same data is left in the data buffer 104 until the buffer area for inputting the next network data is exhausted, so that the CPU 11 can access the main memory 12. On the other hand, it can function as a CPU cache. FIG. 3 is a flowchart showing a main memory access process in the network system control device shown in FIG. First, the CPU 11 is the CPU
An access request to the main memory 12 is issued to the interface unit 103 (S31). Upon receiving the main memory access request from the CPU 11, the CPU interface unit 103 determines whether the access address is the address area of the main memory 12, and at the same time, the data of the corresponding main memory address is stored in the data buffer 104. It is confirmed whether or not it exists in (S32). Therefore,
When it is confirmed that the corresponding data does not exist in the data buffer 104 (No in S32)
In the same manner as in the conventional system, an access request is issued to the memory control unit 102 to access the main memory 12 (S33), and the corresponding data is stored in the main memory 12 as C
It outputs to PU11 (S34).

On the other hand, when it is confirmed that the corresponding data exists in the data buffer 104 (S3
If Yes in 2), the data buffer 104
Network data stored inside the CPU1
It outputs to 1 (S35). At this time, the data buffer 1
In general, the CPU 04 has a small data capacity as compared with the large-capacity main memory 12 and is capable of high-speed access, so that the CPU access time is improved.

As described above, the data buffer 104 has both the function as a buffer for the received network data and the function as a CPU cache, so that the network system performance can be further improved. ing. By the way, in the above-described first embodiment, the network data stored in the data buffer 104 is stored in the main memory 12 between CPU accesses.
In this case, the DMA
It is difficult for the control unit 101 to completely grasp the timing when the CPU 11 accesses the main memory 12. Therefore, data copy from the data buffer 104 to the main memory 12 (that is, DM
Since the A transfer) and the access from the CPU 11 to the main memory 12 are duplicated, the CPU access speed may be reduced. In order to prevent such a problem from occurring, the network system control device may be operated as shown in FIG.

FIG. 4 is an operation time chart of the network system control apparatus shown in FIG.
Main memory access of the CPU 11 shown in FIG. 1 (access for reading data) and copying of network data held in the data buffer 104 to the main memory 12 (that is, network data by the memory control unit 102). , Which is the DMA transfer of the above), at which operation timing each functional unit should be operated.

In the figure, all control signals are Lo
It is displayed as w-Active. Further, AA is an address in the main memory 22 which is a DMA transfer destination of the held network data, and DA is network data DMA-transferred from the data buffer 104. Also, A
B is a main memory 22 for accessing the main memory of the CPU 11.
And the DB is data read from the main memory 12 by the main memory access of the CPU 11.

All functional blocks in this network system control device operate according to the system clock supplied from the CPU 11. DM
The memory control unit 102 which receives the data copy request from the A control unit 101 at the timing shown in the figure outputs the network data DA for the main memory 12 from the data buffer 104.

While the data copy is being executed, the CPU 11 accesses the main memory 12 (CPU
Access request) occurs at the timing shown in the figure,
The address AB is output on the CPU bus, and then the data DB related to the access is output on the CPU bus at the timing shown in the figure. On the other hand, when the memory control unit 102 receives a data copy request from the DMA control unit 101, the chip select signal C to the main memory 12 is sent.
Assert S. After that, when it is confirmed that the CPU bus address is AB through the CPU interface unit 103, the address output to the main memory bus is changed from AA to AB while the chip select signal CS to the main memory 12 is asserted. , And deasserts the write enable signal WE indicating data writing. As a result, the CPU 11 is immediately switched to the access to the main memory 12, the data copy access to the main memory 12 being executed is immediately stopped, and the data read access from the main memory 12 is started.

After that, the main memory access time elapses,
After the data DB read from the main memory 12 is output to the CPU bus and the CPU access request is deasserted, the memory control unit 102 changes the address output to the main memory bus from AB to AA. A write enable signal WE indicating writing is asserted to restart the data copy access.

As described above, the main memory 12 is operated by operating each functional unit of the network system control device.
Even if there is a conflict between the CPU access to the network and the data copy from the data buffer 104, the network data D can be transferred without degrading the CPU access speed.
It becomes possible to reliably execute the MA transfer. FIG. 5 is a time chart showing the operation of the network system control device according to the second embodiment of the present invention. In this embodiment, when performing a plurality of network controls, each network control circuit 13 connected to a plurality of networks (for example, Ethernet and a telephone line) is connected to the expansion bus 14 shown in FIG. The state (not shown) is assumed. In such a state, one expansion bus 14 is interleaved and shared by the individual network control circuits 13, so that the same effect as that of the first embodiment can be obtained.

Here, a concrete operation time chart for doing so is shown. For each functional block of this network system control device, CP
It operates according to the system clock supplied from U11. Then, in synchronization with this system clock, continuous interleave phases 1 to n (where n represents the number of connected networks) are periodically allocated. Specifically, regarding the network control circuit 13 of the device 1, the interleave phase 1
In the same manner, the network control circuits 13 of the device n are controlled so that they can be output in the interleave phase n.

Note that, even when it is possible to provide each network control circuit 13 with a dedicated bus instead of sharing the expansion bus 14 as described above, the present network system is also possible. It is possible to control a plurality of networks by the control device, but in such a case, it is necessary to control so that a plurality of network data are not simultaneously output to the expansion bus 14.

[0044]

According to the network system control device of the present invention, the network data received from the network is held in the data holding means provided inside the device. Therefore, the terminal only needs to have the function of transmitting / receiving data to / from the network, and the cost can be effectively reduced in constructing the system.

Further, since the network data held in the data holding means is copied to the main memory at intervals between main memory accesses of the main control unit,
Even when a main memory access by the main control unit occurs during data copying, the access can be preferentially executed. Therefore, it is possible to avoid the deterioration of the main memory access as in the conventional case.

Further, since the interrupted data copy is resumed immediately after the main memory access is completed, it is of course possible to prevent the data loss. As described above, since the procedure for fetching the network data held in the external local data buffer is completely unnecessary, the data processing time can be greatly shortened accordingly.

In addition, when it is confirmed that the data related to the main memory access of the main control unit is held in the data holding means, the corresponding data can be transferred to the main control unit. Therefore, it is possible to significantly reduce the access time by the main control unit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a network system control device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing processing of network reception data in the network system control device shown in FIG.

FIG. 3 is a flowchart showing a main memory access process in the network system control device shown in FIG.

FIG. 4 is an operation time chart of the network system control device shown in FIG.

FIG. 5 is a time chart showing the operation of the network system control device according to the second embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional network system control device.

FIG. 7 is a flowchart showing processing of network reception data in the conventional network system control device shown in FIG.

[Explanation of symbols]

 10, 20 System control circuit 11, 21 CPU 12, 22 Main memory 13, 23 Network control circuit 14, 24 Extended path 101, 201 DMA control unit 102, 202 Memory control unit 103, 203 CPU interface unit 104 Data buffer

Claims (6)

[Claims] 1. A network system control device for storing data received from a network in a main memory unit, controlling the network system for reading the stored data and processing the data in the main control unit, wherein the data received from the network A main memory access detection unit that detects whether or not a main memory access is generated by the main control unit; and a main memory access detection unit that generates a main memory access by the main control unit. If it is detected that the data held in the data holding means is DM
When the main memory access detection unit detects the occurrence of a main memory access by the main control unit, the data copying unit that copies the data to the main storage unit by A transfer, Access data searching means for searching whether the data is held in the data holding means; and when the access data searching means searches for data related to main memory access by the main control unit, main control the data. A network system control device comprising: an access data transfer unit that transfers the data to a unit. 2. The data holding means further comprises address giving means for giving an address associated with a data storage area of the main memory to data received from a network, and given by the address giving means. 2. The network system control device according to claim 1, wherein the data is held according to the generated address. 3. The data copying means further suspends the data copying when the main memory access detecting means detects that a main memory access by the main controller has occurred during the data copying. A data copy suspending means, and a data copy restarting means for restarting the data copy when the main memory access detecting means detects that the main memory access by the main control unit has ended during the data copy suspending, The network system control apparatus according to claim 2, further comprising: 4. The access data searching means further comprises address judging means for judging whether or not the address of the main memory access by the main control unit matches the address given by the address giving means, 4. The network system control device according to claim 3, wherein when the address determination unit determines that the addresses match, the corresponding data is searched based on the addresses. 5. The access data transfer means further comprises access destination switching means for switching main memory access by the main control portion to access to the data holding means, and the access destination switching means performs the main control. 5. The network system control apparatus according to claim 4, wherein when the main memory access by the unit is switched to the access to the data holding unit, the corresponding data is transferred to the main control unit. 6. The network system control device according to claim 1, further comprising: when receiving and processing individual data transmitted from a plurality of networks, further capturing data from each network to said data holding means. A network system control device, comprising: a data acquisition order assignment means for assigning a time to each network for each time.