JPH09101349A - Semiconductor tester - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize an inexpensive circuit by lessening the number of memories in use by making the memories in use common in a corrective computation device which corrects nonuniformity in a plurality of analog setting object circuits having a large number of channels and ensures a prescribed accuracy. SOLUTION: A first corrective memory 60 storing theoretical set data (x) set for each channel discretely and a second corrective memory 61 storing corrective data H in arrangement are provided. The theoretical set data (x) from the first corrective memory 60 and the corrective data H from the second corrective memory 61 are read out sequentially and subjected to corrective computation by a prescribed corrective computation circuit and corrected set data 230 are outputted to a setting object circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data correction calculation device for correcting and calculating individual variations in a circuit of an analog setting target (for example, VIO device) having a plurality of channels in a semiconductor test device.

[0002]

2. Description of the Related Art An example of prior art is shown in FIGS.
A specific example of a data correction circuit included in a VIO (Voltage input output) device will be described below. Generally, the driver circuit 110, the comparator circuit 120, and the DA converter 90 having a plurality of channels each have individual characteristic variations (linearity, offset, and temperature dependence).
have. Therefore, in the VIO device, by supplying the corrected setting data 230 after the data correction calculation processing so that the ideal high / low level is obtained at the target observation point, the DUT test maintaining a predetermined high accuracy is performed. It is possible.

In the semiconductor test device, as shown in the main part configuration diagram of the VIO device of the semiconductor test device of FIG. 5, after a predetermined high / low voltage level is set and supplied to a plurality of driver circuits 110 and comparator circuits 120, The device under test (DUT) is tested. In the configuration example of this figure, VI
This is a configuration example in which the O device is divided into two, one test head side 100 has a plurality of DA converters for converting digital code data into analog voltage signals, and the other main body side 300 has the digital code. There is a data correction circuit 200 that supplies data (correction setting data 230).

Since the semiconductor test apparatus itself is a measuring instrument, it is equipped with various correction functions for maintaining a predetermined accuracy and interfacing with the DUT. Data correction circuit 20
Even at 0, a correction means for maintaining this accuracy is installed. That is, the voltage characteristics (linearity, gain,
The offset voltage) is obtained by performing calibration in advance, and a calibration value for correcting this to a target voltage level is calculated and stored in an internal correction memory before being used.

The correction of the voltage level in the VIO device is performed by the secondary correction calculation formula, and as the correction data H, three kinds of correction parameters A, B and C are used. This correction calculation formula is Y = Ax ² + Bx + C. Here, x is theoretical setting data, A and B are gain correction coefficients, and C is an offset correction coefficient. Therefore, this correction calculation requires one setting data memory and three correction memories.

FIG. 4 shows an example of a data correction circuit corresponding to the quadratic correction calculation formula, which will be described below.
The circuit configuration of the data correction circuit 200 includes a set value data memory 60, a first gain correction memory 62, a second gain correction memory 64, an offset correction memory 66, a counter 70, and pipeline FFs 72, 74, 76. , First
A multiplier 82, a first adder 84, a second multiplier 86,
And a second adder 88.

This circuit has two operations, a batch setting operation and a single setting operation, depending on the operation mode of the counter 70. First
In this case, all DA converters are collectively output at high speed for correction calculation and set. In this case, the counter 70 operates while sequentially incrementing by 1 from the initial value to the final value. The second is a case where the correction calculation output to a single DA converter is set and set. In this case, the counter 70 functions as a register and ends in one operation.

The case of collective setting operation will be described below.
This circuit has a pipeline arithmetic processing configuration. The output address signal 70adr of the counter 70 is used as an address signal for each memory and also as address information for designating a plurality of DA converters. This counter 7
0 counts one by one for each clock CLK and generates an address signal. The output of the address signal 70 adr is supplied to the set value data memory 60, the first gain correction memory 62, and the pipeline FF 72.

The set value data memory 60 supplies the theoretical set data "x" of this address to the first multiplier 82 and the pipeline FF 76. The first multiplier 82 supplies the data “Ax” obtained by multiplying the theoretical setting data “x” with the gain correction data “A” from the first gain correction memory 62 to the first adder 84. In the first adder 84,
Upon receiving Ax ", the data" Ax + B "obtained by adding the gain correction coefficient" B "from the second gain correction memory 64 accessed by the pipelined address value is supplied to the second multiplier 86.

In the second multiplier 86, this data "Ax +
B ", the setting data" x "after the pipeline is received, and the data" Ax ² + Bx "obtained by multiplying both is supplied to the second adder 88. In the second adder 88, this data"
Ax ² + Bx "is received, and the corrected setting data 230, that is," Y = Ax ² + B "is obtained as a result of adding the offset data" C "accessed with the address contents after the two-stage pipeline.
x + C ″ is supplied to the external DA converter 90.
As described above, the pipeline calculation is sequentially performed to continuously generate and output the corrected setting data 230 that has been corrected to all the DA converters 90.

[0011]

As described above, the data correction circuit 200 uses the set value data memory 60 and three correction data storage memories. Here, the capacity of these correction memories is about 10 K words, which is a relatively small capacity memory. Although not shown in the figure, a switching circuit for arbitrarily reading and writing these memory contents from an external CPU is also provided. For this reason, when this circuit is integrated to form an LSI, it is necessary to separately provide a memory and a connection signal terminal,
Providing a plurality of these correction memories is not preferable in terms of board space and cost.

Therefore, the problem to be solved by the present invention is to correct the variation of the analog setting target circuit having a plurality of channels to ensure a predetermined accuracy, by using a common memory and reducing the number of memories used. The purpose is to reduce the cost and realize an inexpensive circuit.

In order to solve the above-mentioned problems, in the configuration of the present invention, a first correction memory 60 for storing theoretical setting data x for each channel is provided, and correction data H is arranged and stored. The second correction memory 61 is provided, the theoretical setting data x from the first correction memory 60 and the correction data (H) from the second correction memory 61 are sequentially read out, and correction calculation is performed by a predetermined correction calculation circuit to set. The constituent means outputs the setting data 230 to be corrected to the target circuit. As a result, a multi-channel analog setting target circuit (eg DA
Peripheral circuit including converter 90 and DA converter 90)
Correction data H which is at least two types of correction parameters for receiving theoretical setting data x of each channel and correcting characteristic variations of individual setting target circuits.
(For example, gain correction data “A”, “B” and offset correction data “C”), a device that outputs the correction setting data 230 that has been subjected to a predetermined correction calculation (for example, a secondary correction calculation formula) has two memories. Can be realized by reducing the number of memories used.

Further, a correction memory 60 for arranging and storing the theoretical setting data x for each channel and the correction data H in one memory is provided, and the theoretical setting data x and the correction data H are sequentially read from the correction memory 60. The constituent means for performing the correction calculation by the predetermined correction calculation circuit and outputting the correction target setting data 230 to the setting target circuit can be realized by one memory.

More specifically, the VIO device is provided with a first correction memory 60 for storing theoretical setting data x for each channel, and a second correction memory 61 for arraying and storing the correction data H. Correction parameters A, B,
A second correction memory 61 for arraying and storing the correction data H of C is provided, and the theoretical setting data x from the first correction memory 60,
There is a configuration means for sequentially reading the correction data H from the second correction memory 61, performing a correction calculation by a predetermined correction calculation circuit, and outputting the correction setting data 230 to the setting target circuit.
As a result, the correction data H (for example, the gain, which is three types of correction parameters, which has the multi-channel DA converter 90 having the characteristic variations of the linearity and the offset, receives the theoretical setting data x of each channel and corrects the theoretical setting data x. With the correction data “A” and “B” and the offset correction data “C”), a predetermined secondary correction calculation formula Ax ²
Corrected setting data 23 for which correction calculation of + Bx + C is performed
The VIO device that outputs 0 to the DA converter 90 can be realized with two memories, and the number of used memories can be reduced.

More specifically, in the VIO device, a correction memory 60 for arranging and storing theoretical setting data x for each channel and correction data H for three kinds of correction parameters A, B, and C in one memory. The correction memory 6
There is a configuration means for sequentially reading the theoretical setting data x and the correction data H from 0, performing a correction calculation by a predetermined secondary correction calculation circuit, and outputting the correction setting data 230 to the DA converter 90. In this case, It can be realized with one memory.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to examples.

[0017]

【Example】

(Embodiment 1) In the present embodiment 1, a clock four times as large as the conventional clock CLK is used. Therefore, the entire circuit has a circuit portion using a memory element arithmetic element that can operate at a speed four times higher. And three correction data A, B, C
Are arranged and stored in one memory, and are sequentially read out in a time-division manner to perform correction calculation. An embodiment of the present invention will be described below with reference to FIGS. 1, 2 and 3 in the case of a data correction circuit 200 in which three correction memories are replaced with one memory.

As shown in FIG. 1, the configuration of the data correction circuit 200 of the present invention has a set value data memory 60, a correction memory 61, a counter 71, and a latch decoder section 20.
, Pipeline FFs 22, 24, 26, a first multiplier 82, a first adder 84, a second multiplier 86, and a second adder 88. Here, the set value data memory 60, the first multiplier 82, the first adder 84, the second multiplier 86, and the second adder 88 are the same as the conventional ones.

The counter 71 is obtained by adding the lower 2 bits to the conventional counter, and is a quadruple speed clock C.
Works in LK. The lower 2 bits of this counter output are used to control the time-division reading and operation. Therefore, the lower 2 bits of the address signal 71adr are supplied to the latch decoder unit 20, and the lower 2 bits are supplied to the set value data memory 60.
The address signal 71 adr excluding bits is supplied, and the correction memory 61 is supplied with the whole address signal 71 adr.

As shown in the memory map of FIG. 3, the correction memory 61 has a gain correction coefficient “A” and a gain correction coefficient “B” of each DA converter in order of 4 words.
The correction data H of the offset correction coefficient "C" is stored in an array. Then, in response to the quadruple speed address signal, the three correction coefficients are sequentially read. On the other hand, in the set value data memory 60, reading is performed at the same speed as in the past.

The latch decoder section 20 of FIG. 1 receives the address signal 71adr of the lower 2 bits and the clock signal of quadruple speed and generates and supplies the latch clock of each arithmetic register. That is, the calculation proceeds as shown in the timing chart of FIG. First clock CLK of quad speed clock
30 is supplied to the second adder 88 and the pipeline FF 26, CLK31 is supplied to the first multiplier 82, and CLK32
Is supplied to the pipeline FF 22 and the CLK 33 is supplied to the pipeline FF 24 and the second multiplier 86.

As a result, the first multiplier 82 receives the theoretical setting data "x" from the setting value data memory 60 and the gain correction coefficient "A" from the correction memory 61,
As shown in, "A" is obtained by multiplying both by CLK31.
x "is latched and output. In addition, the pipeline FF 22
Receives the gain correction data "B" from the correction memory 61, and as shown in FIG.
B '"is latched and output. Similarly, pipeline FF2
4 receives the gain correction data "C" from the correction memory 61 and latches "C '" to the next stage by CLK33. The pipeline FF 26 receives the address signal 71 adr excluding the lower 2 bits of the counter 71, and supplies it as address information corresponding to the corrected setting data 230 to be output to the plurality of DA converters in synchronization with the timing of this output data. To do.

In the second multiplier 86, in the first adder 84,
Data "Ax" obtained by adding "Ax" and "B '" described above
+ B '", the theoretical setting data" x "from the setting value data memory 60, and the data" Ax "
² + B'x "is latched and supplied to the second adder 88.
Then, in the second adder 88, the correction setting data 230 obtained by adding this data and the offset data “C ′” from the pipeline FF 24, that is, “Y = Ax ² + B′x +”
Latch output of C '".

As described above, a quadruple speed clock,
Using the single correction memory 61 in which the gain correction coefficients “A” and “B” and the offset correction coefficient “C” are stored in an array, the correction setting data “Y = Ax ² + Bx + C” for the DA converter similar to the conventional one is used. "Can be calculated and output.

(Embodiment 2) In the present embodiment 2, a clock four times as large as that of the conventional clock CLK is used.
In, the one using the two memories of the set value data memory 60 and the correction memory 61 is stored in one memory,
This is a case where this is used as a means for sequentially reading out in a time division manner and performing a correction calculation.

An example of the present invention will be described below with reference to FIGS. 6 and 7. As shown in FIG. 6, the configuration of the data correction circuit 200 of the present invention is different from the configuration of the first embodiment in that the correction memory 61 is deleted, the pipeline FFs 27 and 28 are added, and the latch decoder section 20 is connected. It has a different configuration.

The set value data memory 60, as shown in the memory map of FIG.
The theoretical setting data “x”, the gain correction coefficient “A”, the gain correction coefficient “B”, and the offset correction coefficient “C” of the converter are array-stored. As a result, the entire address signal 71adr from the counter 71 is received, and the four respective data are sequentially read at the quadruple speed and are used.

The first theoretical setting data "x" in the array of setting value data memory 60 is CL from the latch decoder section 20.
It is supplied to the first multiplier 82 and the second multiplier 86 by being latched by the pipeline FF 28 by K31, and is used similarly to the first embodiment. The next set data “A” in the set value data memory 60 array is supplied to the first multiplier 82 as it is, multiplied by “Ax”, latched by CLK 32, and latched by the CLK 32, as in the first embodiment. 84. Setting data memory 60 Next setting data in array "
B "is latched by the pipeline FF 22 for use by the CLK 33 from the latch decoder unit 20 as in the first embodiment. Further, the next setting data" C "in the array of the setting value data memory 60 is also the same. The latch decoder unit 2
With CLK30 from 0, it is latched by the pipeline FF 24 and used as in the first embodiment.

The second multiplier 86 latches and outputs the data multiplied by "Ax ² + B'x" as in the first embodiment by CLK30. Then, in the second adder 88, "C" is added by CLK31, and the correction target setting data 230 similar to the first embodiment, that is, "Y = Ax ² + B'x + C '" is latched and output.

The pipeline FF 27 is a pipeline F.
By using it together with F26, the address signal 71adr excluding the lower 2 bits of the counter 71 is latched and output in synchronization with the output timing of the corrected setting data 230 to be output to the plurality of DA converters.

As described above, the theoretical setting data "x", the gain correction coefficients "A" and "B", and the offset correction coefficient "are stored in one memory using the quadruple speed clock.
By storing and using C ″ as an array, it is possible to calculate and output the corrected setting data 230 to the DA converter similar to the first embodiment.

(Application example) In the description of the first and second embodiments,
Although an example of the correction calculation by the secondary correction calculation formula “Y = Ax ² + Bx + C” has been described, other correction calculation formulas may be used, and by storing a plurality of correction parameters in a common memory, It can be implemented by the method of the above embodiment. Of course, in the above-described first and second embodiments, the correction calculation procedure in which the calculation order of the correction calculation formulas is changed may be used, and the correction calculation procedure can be implemented by using a circuit and a memory map corresponding thereto.

Further, in the above-mentioned embodiment, the example in which the setting data for the DA converter in the VIO device is corrected by the secondary correction calculation formula has been described, but it may be applied to other devices which require a correction means. The same applies.

In the above description of the first and second embodiments, all correction calculations are realized by circuits, but if desired, a high-speed DSP (instead of these calculation circuits (multiplying means, adding means)) may be used. A digital signal processor) may be used instead.

[0035]

Since the present invention is configured as described above, it has the following effects. As in the configuration of the first embodiment, a clock four times as long as the conventional clock is used, three correction data A, B, and C are arrayed and stored in one correction memory 61, and the data is sequentially read in a time-division manner for correction. By performing the calculation, the effect that only one memory can be used instead of using three in the past can be obtained.

In the configuration of the second embodiment, the conventional clock of 4 is used.
Using the double clock, the set value data “x” and the three correction data A, B and C are array-stored in one memory 60,
By sequentially reading out the data in a time-division manner and performing the correction calculation, it is possible to obtain the effect that only one memory is required instead of the conventional four.

As described above, the memories used can be made common, the number of memories used can be reduced, and the circuit can be realized at a lower cost.
Especially when the peripheral circuits except memory elements are integrated into LSI,
There is also an advantage that the number of connecting pins when using multiple memories can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data correction circuit 200 of a VIO device according to a first embodiment of the present invention.

FIG. 2 is a timing diagram of pipeline operation according to the first embodiment of the present invention.

FIG. 3 is a memory map diagram of the first embodiment of the present invention.

FIG. 4 is an example of a configuration diagram of a conventional data correction circuit 200 of a VIO device.

FIG. 5 is an example of a main part configuration diagram of a conventional VIO device of a semiconductor test device.

FIG. 6 is a configuration diagram of a data correction circuit 200 of the VIO device according to the second embodiment of the present invention.

FIG. 7 is a memory map diagram of the second embodiment of the present invention.

[Explanation of symbols]

20 Latch Decoder Part 22, 72, 74, 76, 24, 26, 27, 28 Pipeline FF 30, 31, 32, 33 CLK 60 Memory 61 Correction Memory 62 First Gain Correction Memory 64 Second Gain Correction Memory 66 Offset Correction Memory 70, 71 Counter 70adr, 71adr Address signal 82 First multiplier 84 First adder 86 Second multiplier 88 Second adder 90 DA converter 100 Test head side 110 Driver circuit 120 Comparator circuit 200 Data correction circuit 230 Corrected Setting data 300 Main unit side

Claims (4)

[Claims] 1. A multi-channel analog setting target circuit having individual characteristic variations of linearity and offset, receives theoretical setting data (x) of each channel, and corrects it. In a device that outputs corrected setting data that has been subjected to a predetermined correction calculation using correction data (H) that is at least two types of correction parameters, a first correction memory that stores the theoretical setting data (x) for each channel is provided, A second correction memory that stores the correction data (H) in an array is provided, and the theoretical setting data (x) from the first correction memory and the correction data (H) from the second correction memory are sequentially read, A semiconductor test apparatus characterized by performing a correction calculation in a predetermined correction calculation circuit and outputting the setting data to be corrected to the setting target circuit. 2. A multi-channel analog setting target circuit having linearity and characteristic variations of each offset receives theoretical setting data (x) for each channel, and uses correction data (H) which is a correction parameter for correcting the theoretical setting data (x). A device for outputting the setting data to be corrected, which has been subjected to a predetermined correction calculation, is provided with a correction memory for arranging and storing the theoretical setting data (x) and the correction data (H) for each channel in one memory. 2. The semiconductor test apparatus characterized in that the theoretical setting data (x) and the correction data (H) are sequentially read out, correction calculation is performed by a predetermined correction calculation circuit, and the correction target data is output. 3. A multi-channel DA converter (90) having characteristic variations in linearity and offset.
In addition, by receiving the theoretical setting data (x) of each channel, the correction data (H) which is the three types of correction parameters for correcting the theoretical setting data (x) is used to determine a predetermined secondary correction calculation formula (Ax ² + Bx).
+ C) Corrected setting data (23
0) is output to the DA converter (90), a first correction memory for storing the theoretical setting data (x) for each channel is provided in the VIO device, and a second correction memory for storing the correction data (H) in an array. And a second correction memory (61) for storing correction data (H) of three types of correction parameters (A, B, C) in an array, and the theoretical setting data (x) from the first correction memory. , Sequentially reading the correction data (H) from the second correction memory, performing a correction calculation by a predetermined correction calculation circuit, and outputting the correction target setting data (230) to the setting target circuit. Semiconductor test equipment. 4. A multi-channel DA converter (90) having characteristic variations in linearity and offset.
In addition, by receiving the theoretical setting data (x) of each channel, the correction data (H) which is the three types of correction parameters for correcting the theoretical setting data (x) is used to determine a predetermined secondary correction calculation formula (Ax ² + Bx).
+ C) Corrected setting data (23
0) to the DA converter (90), the VIO device outputs the theoretical setting data (x) for each channel and the correction data (H) of three types of correction parameters (A, B, C) into one. A correction memory (60) for arranging and storing in a memory is provided, the theoretical setting data (x) and the correction data (H) are sequentially read from the correction memory (60), and correction calculation is performed by a predetermined secondary correction calculation circuit. Then, the semiconductor test apparatus is characterized in that the correction setting data (230) is output to the DA converter (90).