JPH0898149A - Video signal processor - Google Patents

Abstract

PURPOSE: To record a non-standard video signal in a device which digitally records a picture signal. CONSTITUTION: A synchronizing signal from which a horizontal/vertical synchronizing signal is separated by a synchronization separator 2 is synchronously protected by using a clock which is stable in terms of a frequency. The protected horizontal synchronizing signal hd is supplied to a clock selector 7. The clock selector 7 selects the clock whose phase is the nearest to the fall edge of hd, and outputs it to a frequency divider 4. A video signal supplied to an input terminal 1 is A/D-converted by using the selected clock, is latched by the clock which the frequency divider 4 outputs and is written into a memory 12. A PLL unit 13 generates the clock synchronized with the vertical synchronizing signal and outputs it to a read controller 15. The read controller 15 generates a read control signal and reads data from the memory 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device capable of handling a (non-standard) video signal having a jitter or a pseudo sync signal when digitally recording an image signal.

[0002]

2. Description of the Related Art Recently, D1, D2 and D3 video tape recorders (hereinafter abbreviated as VTRs) for digitizing and recording and reproducing video signals have been developed. As consumer equipment, video floppy capable of recording and reproducing digital still images and VTR capable of recording digital moving images have been developed. As an example of the development of a consumer digital VTR, a journal of the Television Society (Vol. 45 No. 7) is available.
pp813-819 1991). These digital VTRs are basically developed for recording standard signals with stable jitter and synchronization signals.

A conventional video signal processing device will be described below. FIG. 4 is a block diagram of a conventional video signal processing device. In the figure, 50 is a video signal input terminal,
Reference numeral 51 is a sync separator for separating a horizontal sync signal and a vertical sync signal from an input video signal, 52 is a control signal generator for generating a reference signal based on the horizontal sync signal and the vertical sync signal, 53
Is a PLL device that receives a reference signal as input and generates a clock that is phase- and frequency-synchronized by following the fluctuation, and 54 is an analog-digital converter (hereinafter abbreviated as A / D converter) that analog-digital converts the input video signal. , 55 is a memory for storing data, 56 is a write controller for controlling writing to the memory 55 based on a reference signal, 57
Is a read controller for controlling the reading of the data stored in the memory 55 based on the reference signal, 58 is a signal processor for performing various digital signal processing on the data output from the memory 55, and 59 is a signal processor 58. Is an output terminal to which a reference signal for controlling the relative position of the magnetic head and the recording medium is supplied.

The operation of the video signal processing apparatus configured as described above will be described below with reference to FIG.

The video signal input to the input terminal 50 is supplied to the sync separator 51, and the horizontal sync signal and the vertical sync signal are separated. The control signal generator 52 generates a reference signal from the separated sync signal. This reference signal is the PLL device 5
3 and a clock synchronized with the input video signal is generated. The video signal supplied to the input terminal 50 is converted into a digital signal by the A / D converter 54 using this clock (clock of the PLL device 53 output). The output signal of the A / D converter 54 is stored in the memory 55 based on the write control signal output from the write controller 56. The write control signal is generated based on the reference signal. The reading of data from the memory 55 is similarly performed based on the read control signal generated by the read controller 57 from the reference signal. The data read from the memory 55 is sequentially supplied to the signal processor 58, and various digital processes such as shuffling, compression, error correction and modulation are performed.
The digital signal processed signal is output from the output terminal 59.

The control signal generator 52 generates a reference signal of the servo circuit using the vertical synchronizing signal in the input video signal and outputs it to the output terminal 60. In a video signal processing device for highly efficient encoding and recording / reproducing a video signal, a servo circuit controls the relative position of the magnetic head and the recording medium (tape or disk) (not shown in FIG. 4). Then, the data output from the output terminal 59 is recorded at a predetermined position on a recording medium such as a tape or a disk.

[0007]

However, in the above-mentioned conventional configuration, as the video signal, a non-standard signal (a video signal having a pseudo sync signal, a video signal having a large jitter, a horizontal frequency and a vertical frequency are normal). Irrelevant video signals, signals with discontinuity (skew) in the horizontal sync signal, such as signals reproduced from home VTRs, home movies V
When a signal such as a tape reproduced in a state where synchronization is disturbed due to a large vibration that is sometimes applied during shooting in TR is input, the horizontal frequency, vertical frequency and clock frequency cannot be synchronized with each other. In reading from the memory 55, there is a problem that relative fluctuation of data with respect to the input video signal becomes large and stable signal processing cannot be performed. Further, there is a problem in that it is not possible to stably perform a process of extracting a normal signal from the sync signals separated by the sync separator 51 or inserting a missing sync signal at a normal position.

The present invention solves the above-mentioned conventional problems. Even if the input video signal includes a large fluctuation or a pseudo sync signal, the sync signal component is stably extracted and the data is written in the memory. It enables stable reading. An object of the present invention is to provide a video signal processing device which can surely perform the subsequent digital signal processing and stably record on a recording medium.

[0009]

In order to achieve this object, a video signal processing apparatus of the present invention uses a clock A having a constant frequency.
And a control signal generator that generates a horizontal reference signal and a vertical reference signal using clock A,
A selector for phase-shifting clock A and outputting clock B based on the rising or falling edge of the horizontal reference signal, and an analog input video signal using clock B
A / D converter for digital conversion, phase converter for latching output signal of A / D converter with clock A, memory for temporarily storing output signal of phase converter, and clock D synchronized with vertical reference signal , A write controller for generating a memory write signal from the clock A based on the horizontal sync signal, a read controller for generating a memory read signal from the clock D, and a memory output signal. It has a configuration having a signal processor that performs various digital processing of data using a clock D.

To achieve this object, the video signal processing apparatus of the present invention comprises a clock generator for generating a clock A having a constant frequency, and a control signal generator for generating a horizontal reference signal and a vertical reference signal using the clock A. Device, a first PLL device for generating a clock B synchronized with the horizontal reference signal, an A / D converter for analog-digital converting an input video signal using the clock B, and an output signal of the A / D converter , A second PLL device that generates a clock D synchronized with a vertical reference signal, a write controller that generates a write signal of the memory from the clock A based on the horizontal synchronization signal, and a memory from the clock D. And a signal processor for digitally processing the data output from the memory by using the clock D. There.

In order to achieve this object, the video signal processing apparatus of the present invention comprises a clock generator for generating a clock A having a constant frequency, and a control signal generator for generating a horizontal reference signal and a vertical reference signal using the clock A. And a first PLL device for generating a clock B synchronized with the horizontal reference signal, and a clock C by phase-shifting the output signal of the first PLL device based on the rising or falling edge of the horizontal reference signal. A selector and an A / D converter for analog-digital converting the input video signal using a clock C;
A phase converter that latches the output signal of the / D converter with the clock B, a memory that temporarily stores the output signal of the phase converter, and a clock D that synchronizes with the vertical reference signal.
, A write controller that generates a memory write signal from clock B based on the horizontal sync signal, a read controller that generates a memory read signal from clock D, and data output from the memory. It has a configuration having a signal processor that performs various digital processes using the clock D.

[0012]

According to the present invention, the horizontal and vertical reference signals are generated after removing the pseudo sync signal from the input signal by using the clock having the stable frequency. After that, the input signal is converted into a digital signal by the clock generated by the fast-responsive clock generation circuit that is synchronized with the horizontal reference signal, and written to the memory. Reading from the memory and subsequent various digital signal processing are performed with a clock generated by a clock generator that is synchronous with the vertical reference signal and has a relatively slow response, so that a non-standard signal (video signal having a pseudo sync signal is generated. It is possible to perform stable processing even when a video signal having a large jitter or a video signal in which the horizontal frequency and the vertical frequency are not in a normal relationship is supplied.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a video signal processing apparatus according to the first embodiment of the present invention.

In the figure, 1 is an input terminal for video signals,
Reference numeral 2 is a sync separator for separating a horizontal sync signal and a vertical sync signal from an input video signal, and 3 is a clock generator incorporating a crystal oscillator, and an output signal is divided by a frequency divider 4. A protector 5 removes the pseudo sync signal from the sync signal detected by the sync separator 2 or inserts the missing sync signal. Reference numeral 6 is a control signal generator that generates horizontal and vertical reference signals, and 7 is a clock selector that delays the phase of the signal supplied from the clock generator 3 based on the hd signal output from the protector 5. The output signal of 7 is frequency-divided by the frequency divider 8 and then supplied to the A / D converter 9. 10 is a phase converter for re-latching the input signal with clocks having different phases, 11
Is a write controller for controlling writing to the memory 12,
Reference numeral 3 denotes a PLL device that generates a clock synchronized with the vertical reference signal output from the control signal generator 6, and the generated clock is divided by a frequency divider 14. A read controller 15 controls the reading of data from the memory 12. The signal read from the memory 12 is subjected to various kinds of digital processing by the signal processor 16, and then recorded on the tape 19 by the magnetic heads 18a and 18b mounted on the cylinder 17. Reference numeral 20 is a driver for rotating the cylinder 17 and traveling of the tape 19, and 21a and 21b are guide pins.

The operation of the video signal processing apparatus of the first embodiment constructed as above will be described below.

The video signal (luminance signal and BY-R, Y-R expression difference signal) input to the input terminal 1 is separated by a sync separator 2 into a horizontal sync signal and a vertical sync signal and supplied to a protector 5. To be done. The clock generator 3 is a 27M crystal oscillator.
It produces a very stable signal with a frequency of Hz. Then, the generated signal is supplied to the frequency divider 4 and divided by two. The protector 5 uses the clock A (1
3.5 MHz) is used to remove the pseudo sync signal and insert the sync signal when the sync signal is missing. The protector 5 outputs the falling edge information of the horizontal synchronizing signal as an hd signal to the clock selector 7 while protecting the fluctuation of the horizontal synchronizing signal within 2%. The horizontal and vertical synchronizing signals protected by the protector 5 against jitter and noise are sent to the control signal generator 6. The control signal generator 6 adjusts the timing of these synchronizing signals and generates a horizontal reference signal and a vertical reference signal.

The clock selector 7 delays the 27 MHz signal supplied from the clock generator 3 in units of 2 ns, and outputs hd from the protector 5 from the delayed signal group.
A signal whose phase of the falling edge is closest to that of the rising edge is selected and output to the frequency divider 8. By this processing, a fast response which cannot be obtained by the PLL device is obtained. The output signal B (13.5 MHz) of the frequency divider 8 is used to convert the luminance signal and the expression difference signal supplied to the input terminal 1 into an A / D converter 9
Is converted into a digital signal by. The output signal of the A / D converter 9 is latched by the phase converter 10 with the clocks A having different phases. The output signal of the phase converter 10 is written in the memory 12 based on the write signal wr generated by the write controller 11 using the horizontal reference signal and the clock A.

Next, reading of the memory 12 will be described. The PLL device 13 is a PLL that receives the vertical reference signal supplied from the control signal generator 6. The PLL device 13 is composed of a voltage controlled oscillator using LC resonance and a phase device for phase comparison at 30 Hz, and simultaneously realizes a pull-in of about ± 10% and low jitter of the generated clock. Then, the signal (54 MHz) having a stable frequency is divided by the frequency divider 14
Output to. The frequency divider 14 supplies the 18 MHz clock D to the lead controller 15. The read controller 15 generates a read signal re from the clock D supplied from the frequency divider 14 and reads data from the memory 12 based on this signal.

Here, the structure of the memory 12 will be described in detail. The memory has a two-stage structure. First stage is FIFO
, The luminance signal is written at clock A (13.5 MHz), and at the same time, at the clock A, two types of equation difference signals are alternately
It is written while being thinned out to 4. As a result, the luminance signal is 13.5 Mbps, and each formula difference signal is 3.75 Mbps.
Is written to the FIFO. Reading is performed with an 18 MHz clock D synchronized with the horizontal reference signal. Therefore, jitter absorption and frequency conversion are achieved at the same time.

When reading from the FIFO, the luminance signal is 32
Samples are followed by 8 samples of RY signals and finally 8 samples of BY signals. The signal to be read is subsequently stored in the one-frame memory using the clock D. This frame memory cannot be used with a shuffling function (a method of changing the transmission order of video signals in order to smooth the compression rate of each video signal of one frame so that the transmission order of video signals is changed) and a small capacity FIFO. It realizes large jitter absorption. The frame memory absorbs the jitter by giving a necessary phase difference between the write control signal and the read control signal generated from the clock D.

The signal processor 16 uses the clock D to make a luminance signal 20 DCT (discrete cosine conversion) block from 5 positions on one frame screen and a formula difference signal each 5 DCT block (1 DCT block is composed of 8 × 8 pixels). ) Are collected and compressed to a predetermined number of bits or less using DCT, quantization, and variable length coding techniques. An error correction code is added to the compressed data, which is then modulated and supplied to the magnetic heads 18a and 18b mounted on the cylinder 17.

At the same time, the frame synchronizing signal generated from the clock D is supplied to the driver 20. Based on this signal, the driver 20 controls the relative positions of the magnetic heads 18a, 18b of the VTR and the recording medium to control the cylinder 17 and the tape 1.
Drive 9 A recording signal is output from the signal processor 16 to the magnetic heads 18a and 18b based on the positions of the magnetic heads 18a and 18b on the tape 19. As a result, the output signal of the signal processor 16 is recorded on the tape 19 at a predetermined position.

As described above, according to this embodiment, the control signal generator for generating the horizontal reference signal and the vertical reference signal by using the frequency stable clock A, and the rising or falling edge of the horizontal reference signal. Based on this, a selector that phase-shifts a 27 MHz clock and outputs a clock B, an A / D converter that performs analog-digital conversion of the input video signal using the clock B, and an output signal of the A / D converter with the clock A A phase converter for latching, a memory for temporarily storing an output signal of the phase converter, a PLL device for generating a clock D synchronized with a vertical reference signal, and a write signal for the memory from a clock A based on a horizontal reference signal. A write controller and a read controller that generates a memory read signal from a clock D are provided, and a synchronization signal is generated with a frequency A stable clock A. Extracted, it converts an input video signal at the clock B, which phase shift the 27MHz clock based on the phase information of the horizontal synchronizing signal to a digital signal, and writes the write signal wr generated have using the clock A to the memory.
By reading the data from the memory with the clock D synchronized with the vertical synchronizing signal, (1) various digital processes thereafter can be stably performed even if there is a large change in the input video signal. That is, since the clock of the signal processor 16 is synchronized with the vertical synchronizing signal, the input video signal (the non-standard signal is 1 horizontal scanning period,
The number of clocks for one field or one frame in one vertical scanning period may vary. Particularly when performing field or N frame processing (N ≧ 1), it is not necessary to provide a margin such as a blanking period for processing such as data compression, error correction code addition, and modulation. For that reason,
The circuit can be configured for time-division processing and can be effectively used. (2) A delay occurs when signal processing is required between the A / D converter and the memory. When the delay of the image data is larger than the blanking period of the video signal and overlaps with the valid image data and the discontinuity point of the clock B, the data transmission may not be possible. This can be solved by re-latching the A / D converted data with the continuous clock A.
As a result, the output signal of the write controller 11 becomes continuous and the operation is stable. (3) Further, when the input video signal is a luminance signal (Y signal) and color difference signals (RY, BY signals) or R, G, B signals, when it is desired to monitor a composite signal obtained by encoding this input signal. There is. Frequency accuracy and stability are required for the subcarrier signal required when encoding a color signal. However, when the clock generator 3 is a crystal oscillation circuit, it can be used as a reference signal for generating subcarriers. At the same time, the clock of the encoder circuit becomes a continuous signal, so that the encoding process can be performed stably. Therefore, it is possible to directly connect the digital-analog converter and obtain an analog video signal. (4) The memory 12 for absorbing jitter can be used for frequency conversion (conversion from 13.5 MHz to 18 MHz in this embodiment) and data rearrangement (shuffling function). The shuffling function can be performed in units of one field and one frame, but even if the shuffling function is in units of one field and one frame, the storage capacity for one field and one frame is not necessarily required. Number 1 for jitter absorption of 1 to 2%
A memory that can store data of 0 horizontal scanning period is sufficient. (5) Further, the read timing of the memory 12, the rotation speed of the cylinder 17 and the feed speed of the tape 19 are synchronized with the clock D generated based on the vertical reference signal. As a result, the fluctuation range between the read timing of the memory 12 and the timing of the signal sent to the magnetic head is determined only by the mounting deviation of the magnetic head. Therefore, the margin of the buffer memory for aligning the recording positions can be reduced. (6) Further, when the input signal is switched, the phase of the vertical synchronizing signal of the input video signal becomes discontinuous. When this is input to the driver 20 as it is, in the case where the amount of discontinuity is large, the control of the rotation of the cylinder 17 and the running of the tape 19 is disturbed, and the signal from the signal processor 16 is correctly placed on the tape. It may not be possible to record. By delaying the response of the PLL device 13 to such an extent that the response of the servo is not affected so much, the disturbance of the servo circuit can be prevented. (7) In this embodiment, the clock synchronized with the horizontal reference signal is set to P
It is generated by the clock selector 7 instead of LL. When generated by PLL, there is no problem if the horizontal reference signal is stable,
When there is a large phase shift such as skew, the phase disturbance continues for a certain period of time. However, in the method using the clock selector 7, the disturbance of one horizontal synchronizing signal is limited to one horizontal scanning period, and the timing disturbance of writing to the image memory can be minimized.

Although the clock supplied to the frequency divider 4 and the clock selector 7 is the signal generated from the same crystal oscillator in this embodiment, another signal limit may be prepared. The frequency may be arbitrary.

Although the recording medium is a tape in this embodiment, it may be another medium such as a disk.

FIG. 2 is a block diagram of a video signal processing apparatus showing a second embodiment of the present invention. In the figure, 1 is a video signal input terminal, 2 is a sync separator for separating a horizontal sync signal and a vertical sync signal, 3 is a clock generator with a built-in crystal oscillator, 5 is a protector and is a sync separator 2. The pseudo sync signal is removed from the detected sync signal or the missing sync signal is inserted. 6 is a control signal generator for generating horizontal and vertical reference signals, 9 is an A / D converter, 11 is a write controller for controlling writing to the memory 12, and 13 is a vertical reference output from the control signal generator 6. The generated clock is frequency-divided by the frequency divider 14, which is a PLL device that generates a clock based on the signal. A read controller 15 controls the reading of data from the memory 12. The signal read from the memory 12 is subjected to various kinds of digital processing by the signal processor 16, and then the magnetic head 18 mounted on the cylinder 17.
It is recorded on the tape 19 by a and 18b. Reference numeral 20 denotes a driver for rotating the cylinder 17 and running the tape 19.
21a and 21b are guide pins. The above is the same as the configuration of FIG. The difference from FIG. 1 is that instead of the clock selector 7, frequency divider 8 and phase converter 10 of FIG.
The L unit 30 and the frequency divider 31 are newly installed.

The operation of the second video signal processing device configured as described above will be described below.

The video signal input to the input terminal 1 is separated into a horizontal sync signal and a vertical sync signal by the sync separator 2 and supplied to the protector 5. The clock generator 3 uses a crystal oscillator to generate a very stable clock A of 13.5 MHz. The protector 5 uses the clock A to remove the pseudo sync signal and insert the sync signal when the sync signal is missing. The protector 5 protects the fluctuation of the horizontal synchronizing signal within 2%. That is, a window is created with a clock having a stable frequency in a period in which the horizontal synchronizing signal and the vertical synchronizing signal should exist, and when the synchronizing signal does not exist in the window, the synchronizing signal is inserted. The horizontal and vertical synchronizing signals protected by the protector 5 against jitter and noise are sent to the control signal generator 6. The control signal generator 6 adjusts the timing of the synchronization signal sent from the protector 5 to generate a vertical reference signal and a horizontal reference signal.

The PLL device 30 performs a phase comparison with the horizontal reference signal output from the control signal generator 6 for an effective horizontal scanning period to generate a synchronized clock B. The clock B generated by the PLL device 30 is frequency-divided by the frequency divider 31 to the sampling frequency of the input video signal and supplied to the A / D converter 9. The output signal of the A / D converter 9 is written in the memory 12 based on the write signal wr generated by the write controller 11 from the horizontal reference signal and the clock B. Subsequent operations are the same as those in the first embodiment, so description thereof will be omitted.

As described above, according to the present embodiment, the control signal generator for generating the horizontal reference signal and the vertical reference signal by using the frequency stable clock A, and the clock B synchronized with the horizontal reference signal are generated. 1st PLL device, an A / D converter that performs analog-digital conversion of the input video signal using clock B, a memory that temporarily stores the output signal of the A / D converter, and a vertical reference signal A second PLL device for generating the clock D, a write controller for generating a memory write signal from the clock B based on the horizontal synchronizing signal, and a read controller for generating a memory read signal from the clock D are provided. By providing the frequency-stable clock A, the sync signal is extracted, and the input video signal is demodulated by dividing the clock B synchronized with the horizontal sync signal generated by the first PLL device. Into a digital signal and writes to memory. Then, by reading from the memory with the clock D synchronized with the vertical synchronizing signal generated by the second PLL device, (1) even if there is a large fluctuation in the input video signal as in the first embodiment, various digital signals thereafter are used. It enables stable processing. That is, since the clock D of the signal processor 16 is synchronized with the vertical synchronizing signal, the number of clocks for one field or one frame of the input video signal can be made constant. (2) Further, unlike the first embodiment, since the discontinuity does not occur in the clock B, the phase converter is unnecessary and the circuit configuration can be simplified. Also, the input video signal is a luminance signal (Y signal) and color difference signals (RY, BY signals) or R, G,
Even when a composite signal is encoded from the B signal, if a voltage controlled oscillator using LC resonance is used in the PLL device 30, low jitter can be achieved at the pull-in of about ± 10% at the same time. It is possible to use a clock. However, the protector 5 includes a PLL device 30.
The clock B generated in step 3 is not used. The reason is PLL
The output signal frequency of the device 30 may vary by ± 10%, and it becomes impossible to accurately measure the time of one horizontal scanning period.
Therefore, there arises a problem that the horizontal sync signal protection of the video signal supplied from the tuner cannot be performed stably when the electric field is weak. (3) The clock B synchronized with the horizontal reference signal is generated by the PLL device 30 in this embodiment. When generated by the PLL, it is difficult to sufficiently follow the VTR skew and tape head impact error jitter, which are step responses, because the response speed is slow. However, on the other hand, the horizontal reference signal is always followed (the clock B changes) during one horizontal scanning period, and therefore the followability to the low-frequency jitter is good. Further, when the electric field strength is a weak electric field of 40 dBμ or less, the video signal supplied from the tuner contains many pseudo sync signals. When such a video signal is used to generate a clock by the method as in the first embodiment, it over-responds to the pseudo horizontal sync signal (the pseudo sync signal which came first in the window period set to detect the horizontal sync signal). Select the clock with), causing image quality deterioration. In such a case, stable image quality can be obtained by providing the PLL device 30 with an integration effect with respect to noise.

FIG. 3 is a block diagram of a video signal processing apparatus showing a third embodiment of the present invention. In the figure, 1 is a video signal input terminal, 2 is a sync separator that separates a vertical sync signal and a horizontal sync signal, 3 is a clock generator with a built-in crystal oscillator, 5 is a protector and is a sync separator 2. The pseudo sync signal is removed from the detected sync signal or the missing sync signal is inserted. 6 is a control signal generator for generating horizontal and vertical reference signals, 30 is a PLL device, 31 is a frequency divider, and 7 is a PL.
A clock selector that delays the phase of the signal supplied from the L unit 30 based on the hd signal output from the protector 5. The output signal of the clock selector 7 is divided by the frequency divider 8 to obtain A /
It is supplied to the D converter 9. 10 is a phase converter that latches input signals with clocks having different phases, 11 is a memory 12
A write controller for controlling writing to the writing device, 13 is a PLL device for generating a clock based on the vertical reference signal output from the control signal generator 6, and the generated clock is the frequency divider 1
Divided by 4. A read controller 15 controls reading of data from the memory 12. The signal read from the memory 12 is subjected to various digital processes in the signal processor 16, and then the magnetic head 1 mounted in the cylinder 17
It is recorded on the tape 19 by 8a and 18b. Reference numeral 20 is a driver for rotating the cylinder 17 and traveling of the tape 19, and 21a and 21b are guide pins.

The operation of the third video signal processing apparatus configured as described above will be described below. The video signal input to the input terminal 1 is separated into a horizontal sync signal and a vertical sync signal by the sync separator 2 and supplied to the protector 5. The clock generator 3 uses a crystal oscillator to generate a very stable clock A of 13.5 MHz. Protector 5
Uses the clock A to remove the pseudo sync signal and insert the sync signal when the sync signal is missing. The protector 5 protects the fluctuation of the horizontal synchronizing signal within 2%, and incorporates the falling edge information (or the rising edge) of the horizontal synchronizing signal into the hd signal and outputs it to the clock selector 7.

The horizontal and vertical synchronizing signals protected by the protector 5 against jitter and noise are sent to the control signal generator 6. The control signal generator 6 adjusts the timing of the synchronization signal sent from the protector 5, and generates a vertical reference signal and a horizontal reference signal. The PLL device 30 performs a phase comparison with the horizontal reference signal output from the control signal generator 6 only during the effective horizontal scanning period, and generates a 27 MHz clock B synchronized with the horizontal reference signal. The clock selector 7 delays the 27 MHz clock B supplied from the PLL device 30 in units of 2 ns, and has the closest rising phase to the falling edge of the hd signal output from the protector 5 from the delayed signal group. The signal is selected and output to the frequency divider 8. The frequency divider 8 divides the input signal by two to divide the clock C (13.5 MHz) into A /
It is supplied to the D converter 9. The A / D converter 9 samples the video signal supplied to the input terminal 1 at the frequency of the clock C and converts it into a digital signal. The output signal of the A / D converter 9 is latched by the phase converter 10 with the clock B (the output of the frequency divider 31) having a different phase. The output signal of the phase converter 10 is the memory 1 based on the write signal wr generated by the write controller 11 based on the horizontal reference signal and the clock B.
Written to 2.

Since the following operation is the same as that of the first embodiment, its explanation is omitted. As described above, according to the present embodiment, the control signal generator that generates the horizontal reference signal and the vertical reference signal by using the clock A that is stable in frequency, and the first signal that generates the clock B that is synchronized with the horizontal reference signal. , A selector for phase-shifting the output signal of the first PLL device on the basis of the rising or falling edge of the horizontal reference signal to generate a clock C, and an analog-digital input video signal using the clock C. A / D converter for conversion and A
A phase converter that latches the output signal of the / D converter with the clock B, a memory that temporarily stores the output signal of the phase converter, and a clock D that synchronizes with the vertical reference signal.
, A write controller for generating a memory write signal from the clock B based on the horizontal synchronization signal, and a read controller for generating a memory read signal from the clock D are provided, and a clock having a stable frequency is provided. The sync signal is extracted by A, generated by the first PLL device, and the clock B synchronized with the horizontal sync signal is phase-shifted based on the phase information of the horizontal sync signal, and the input video signal is digitalized by the phase-shifted clock C. Convert to signal. Then, the A / D converted data is latched by the clock B and written in the memory. Then, the written signal is read from the memory at the clock D synchronized with the vertical synchronizing signal. As described above, (1) As in the first embodiment, various digital processes thereafter can be stably performed even if there is a large variation in the input video signal. That is, since the clock of the signal processor 16 is synchronized with the vertical synchronizing signal, the number of clocks for one field or one frame of the input video signal can be made constant. (2) Also, as in the first embodiment, the phase converter 10 is used for data
Since it is possible to remove the discontinuity of the clock and clock, it is possible to improve the stability of signal processing. (3) Further, the clock B synchronized with the horizontal reference signal in the second embodiment is supplied to the A / D converter 9 as it is. Therefore, it is difficult to sufficiently follow the VTR skew and tape head impact error jitter that are step responses. In the present embodiment, the above problem is solved by using the PLL device 30 and the clock selector 7 together. At the same time, since the clock B always changes in accordance with the horizontal reference signal during one horizontal scanning period, the clock B has a characteristic of good followability to low-frequency jitter.

[0036]

As described above, according to the present invention, a protector for protecting a synchronizing signal which operates with a stable clock, a means for generating a clock synchronized with a horizontal reference signal, and a clock for synchronizing a vertical reference signal. By providing the means and the memory, a non-standard signal (for example, a video signal in which the ratio of the vertical synchronizing signal and the horizontal synchronizing signal is not a regular value, a frequency of the vertical synchronizing signal, a video signal with large phase fluctuation, a pseudo synchronizing signal Even if the input video signal) is input, the effect can be absorbed by the protector and the memory. Then, the data can be stably read from the memory, and various digital processes thereafter can be stably performed. In addition, data rearrangement (shuffling function) and frequency conversion processing can be simultaneously achieved in this memory.

Further, by synchronizing the clock supplied to the circuit for processing various digital signals with the signal read from the memory with the vertical synchronizing signal, the number of clocks for one field or one frame of the input video signal becomes constant, which is suitable for signal processing. It is not necessary to provide a margin such as a blanking period, and various types of processing can be effectively used in time division processing.

Further, since the read timing of the memory and the servo circuit are synchronized, the deviation between the read timing of the memory and the timing of the signal sent to the magnetic head depends only on the mounting deviation of the magnetic head, and the recording signal is output. The capacity of the buffer memory for adjusting the timing can be reduced.

Furthermore, when the input signal is switched, the phase of the vertical video signal of the input video signal becomes discontinuous. If this is input to the cylinder or tape driver as it is, if the amount of discontinuity is large, the control of the magnetic head may be disturbed and the signal from the signal processor may not be correctly recorded on the tape. PLL that generates a clock synchronized with a vertical reference signal
If the response of is delayed to such an extent that it does not affect the response of the servo circuit, the influence on the servo can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram of a video signal processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a video signal processing device according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a video signal processing device according to a third embodiment of the present invention.

FIG. 4 is a block diagram of a conventional video signal processing device.

[Explanation of symbols]

 1 video signal input terminal 2 sync separator 3 clock generator 4 frequency divider 5 protector 6 control signal generator 7 clock selector 8 frequency divider 9 A / D converter 10 phase converter 11 write controller 12 memory 13 PLL device 14 Frequency divider 15 Lead controller 16 Signal processor 17 Cylinder 18a, 18b Magnetic head 19 Tape 20 Driver 21a, 21b Guide pin

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takao Kashiro 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. Within AV Technology

Claims (5)

[Claims] 1. A clock generator for generating a clock A having a constant frequency, and a horizontal reference signal and a vertical reference signal based on a horizontal synchronization signal and a vertical synchronization signal in an input video signal using an output signal of the clock generator. And a selector for generating a clock B that is phase-synchronized by phase-shifting the output signal of the clock generator based on the rising or falling edge of the horizontal reference signal, and the input video signal. An A / D converter that performs analog-digital conversion using the clock B supplied from the selector, a phase converter that latches the output signal of the A / D converter with the clock A, and the phase converter A memory for temporarily storing the output signal of the horizontal reference signal, a PLL device for generating a clock D whose phase and frequency are synchronized with the vertical reference signal, and the horizontal reference signal. A write controller that generates a write signal for the memory from the clock A based on the clock, a read controller that divides the clock D to generate a read signal for the memory, and the data output from the memory by the clock. A video signal processing device, comprising: a signal processor for performing various digital processes using D. 2. A clock generator for generating a clock A having a constant frequency, and a horizontal reference signal and a vertical reference signal based on a horizontal synchronization signal and a vertical synchronization signal in an input video signal using an output signal of the clock generator. And a control signal generator for generating a clock signal B, which is phase and frequency synchronized with the horizontal reference signal.
And a A / D for analog-digital converting the input video signal using the clock B supplied from the first PLL device.
A D converter, a memory for temporarily storing the output signal of the A / D converter, a second PLL device for generating a clock D whose phase and frequency are synchronized with the vertical reference signal, and the horizontal synchronization signal as a reference A write controller for generating a write signal for the memory from the clock B; a read controller for dividing the clock D to generate a read signal for the memory; and a data output from the memory for the clock. A video signal processing device, comprising: a signal processor for performing various digital processes using D. 3. A clock generator for generating a clock A having a constant frequency, and a horizontal reference signal and a vertical reference signal based on a horizontal synchronization signal and a vertical synchronization signal in an input video signal using an output signal of the clock generator. And a control signal generator for generating a clock signal B, which is phase and frequency synchronized with the horizontal reference signal.
A first PLL device for generating a clock, a selector for generating a phase-synchronized clock C by phase-shifting an output signal of the first PLL device based on a rising or falling edge of the horizontal reference signal, and the input An A / D converter that performs analog-digital conversion of the video signal using the clock C supplied from the selector; a phase converter that latches the output signal of the A / D converter with the clock B; A memory for temporarily storing the output signal of the converter, a second PLL device for generating a clock D whose phase and frequency are synchronized with the vertical reference signal, and writing of the memory from the clock B based on the horizontal synchronization signal. A write controller for generating a signal, a read controller for dividing the clock D to generate a read signal of the memory, and a read controller for outputting from the memory. A video signal processing apparatus characterized by comprising a signal processing unit for various digital processes by using the clock D the chromatography data. 4. A video signal processing apparatus according to claim 1, wherein the memory has a function of frequency conversion and rearrangement processing of luminance signal data and expression difference signal data. 5. A clock D whose phase and frequency are synchronized with a vertical reference signal as a reference signal for controlling the relative relationship between a magnetic head for recording or reproducing an output signal of a signal processor and a recording medium.
The video signal processing device according to claim 1, wherein the video signal processing device is generated by using the video signal processing device.