JPH0898029A - Coder - Google Patents

Abstract

PURPOSE: To improve the coding speed by finishing discrimination when a significant coefficient is detected at first and terminating coding of linear data series when the position for coding reaches a position at which the discrimination is finished. CONSTITUTION: At first counters 42, 43, a coder 44 and a discrimination device 45 are initialized. Then control signals ctrl, ctrl2 are asserted to start the coder 44 and the discrimination device 45. The coder 44 codes the received coefficient depending on a valid bit number and the discrimination device 45 discriminates whether the received coefficient is a significant coefficient or a non-significant coefficient. Then when the signal val is not asserted, a controller 46 continues the processing and the controller 46 stops the operation of the discrimination device 45 when asserted. Furthermore, the controller 46 checks whether or not addresses adr1 and adr2 are equal to each other and when not equal, the coder 44 codes the received coefficient, and when equal, the coding processing unit 44 is stopped to terminate the entire processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding device, and more particularly, to a two-dimensional one-dimensional data series consisting of N (N is a natural number) coefficients by the value of the significant coefficient and the number of continuous insignificant coefficients. The present invention relates to a coding device that performs entropy coding.

[0002]

2. Description of the Related Art Recently, as a technique for reducing storage capacity and communication time when handling digital image data,
Image compression technology, especially ISO / ITU-TS (old CC
JPEG algorithm (ISO / IECDIS 10918-1) standardized by the ITT as an international standard
Is attracting attention.

An outline of the JPEG algorithm for compressing data will be described below with reference to FIGS.

First, the input image data is divided into blocks of 8 pixels in the main scanning direction and 8 pixels in the sub scanning direction (hereinafter abbreviated as blocks) (not shown). Next, a two-dimensional discrete cosine transform (hereinafter abbreviated as DCT) according to the equation (1) is applied to the divided blocks (step 11). In equation (1), f (i, j) is the i-th main scanning direction and the sub-scanning direction j in the pre-conversion block as shown in FIG.
As for the value of the th pixel, F (u, v) represents the u-th sub-scanning direction v-th sub-scanning direction conversion value in the post-conversion block as shown in FIG.

[0005]

[Equation 1] A block (hereinafter abbreviated as DCT block) converted into frequency components (DCT coefficients) by DCT is quantized by a predetermined quantization table (step 12). The quantized DCT blocks are rearranged into a one-dimensional data series consisting of 64 coefficients by zigzag scanning according to the order shown in FIG. 4 (step 13). The rearranged one-dimensional data series is encoded (step 14). It is checked whether all blocks have been encoded (step 15),
If not finished, the next block is encoded by steps 11-14.

Next, the encoding of the one-dimensional data series in step 14 will be described with reference to FIG. In FIG. 2, n represents the second and subsequent coefficients of the one-dimensional data series, that is, the AC coefficient numbers, and zero represents the number of continuous insignificant coefficients. In addition, floor (a) is a modb which is a number obtained by converting a into an integer by rounding down to the decimal point.
Means the remainder when a is divided by b.

First, the leading coefficient, that is, the DC coefficient is one-dimensionally Huffman-encoded by the effective bit number of the value (for example, the effective bit number is 3 when the DC coefficient value is '7'), and the code is converted into a code string. Then, the effective bit of the coefficient is added to the code string (eg, the effective bit is "111" if the DC coefficient value is "7") (step 2).
03).

Next, from the second coefficient to the 64th coefficient,
That is, the encoding of the AC coefficient is the nth (n is 1 ≦ n ≦ 6
It is checked whether the AC coefficient of the integer 3) is "0" (step 205), and if it is not "0", zero is 1
Check whether it is less than 6 (step 206), ze
If ro is 16 or more, a code (ZRL code) that indicates that 16 integer insignificant coefficients that are obtained by cutting down the decimal point of the quotient obtained by dividing zero by 16 are added to the code string (step 207), and zero is added to zero. Is divided by 16 (step 208), and if zero is smaller than 16, nothing is done, and two-dimensional Huffman coding is performed according to the zero value at that time and the number of effective bits of the AC coefficient to obtain the code. Is added to the code string (step 209), the effective bit of the AC coefficient is added to the code string (step 210), and whether the AC coefficient is the 63rd AC coefficient, that is, the last coefficient of the one-dimensional data series. Check it (Step 21
1) If it is the last coefficient, the encoding is terminated, and if it is not the last coefficient, zero is set to zero, and the processing from step 205 is performed on the (n + 1) th AC coefficient.

If the nth AC coefficient is "0", it is checked whether or not the AC coefficient is the 63rd AC coefficient, that is, the last coefficient of the one-dimensional data series (step 213). If the coefficient is 0, a code (EOB code) indicating the end of the one-dimensional data sequence is added to the code string (step 214), and if it is not the last coefficient, 1 is added to zero, and step 205 is performed for the (n + 1) th AC coefficient.
Perform the following processing.

When the 63rd AC coefficient, that is, the last coefficient of the 1-dimensional data series is encoded in the above manner, step 14 is completed. In the above,
If the significance coefficient is a negative value, the number of significant bits is the number of significant bits of the absolute value of the coefficient, and the number of significant bits is the number of significant bits from the LSB of the 0's complement representation of the value obtained by subtracting 1 from the coefficient. is there. For example, if the significant coefficient is “−3”, the number of effective bits is 2 bits, and the value obtained by subtracting 1 from the coefficient is 8
Since the 0's complement representation in bits is 1111 and 1101, the effective bit is 01.

Since image data often changes smoothly in the range of blocks, significant coefficients are concentrated in the DC coefficient and the low frequency AC coefficient, and there are many blocks in which the ratio of the insignificant coefficient to the high frequency AC coefficient is high. The latter half of the above-mentioned one-dimensional data series often has almost insignificant coefficients. According to the above, if the coefficient from the next coefficient to the last coefficient of a certain significant coefficient in the one-dimensional data series is an insignificant coefficient, that part may be encoded into an EOB code, and the shortest or normal EOB code is used. Since a code having a code length close to that is assigned, high compression efficiency can be realized.

[0012]

However, the above-mentioned 64
In the encoding of the one-dimensional data series consisting of a number of coefficients, the one-dimensional data series is coded sequentially from the beginning, so that until the 64th coefficient of the one-dimensional data series is reached, Since the position of the last significant coefficient appearing at the time is not known, the improvement of the coding speed of the one-dimensional data series is hindered.

As a technique for solving this problem, for example, there is a technique disclosed in Japanese Patent Application Laid-Open No. 5-83564. This technique starts zigzag scanning from the end of the one-dimensional data series, starts encoding from the beginning of the one-dimensional data series when a significant coefficient is detected first, and encodes at the position where the significant coefficient is detected first. Is to end.

However, this is one in which the scanning order in the one-dimensional data series is exchanged, and the time required for encoding the one-dimensional data series is the time for encoding the one-dimensional data series from the beginning to the end. There is no difference with.

The present invention has been made in view of the above-mentioned problems, and a one-dimensional data series consisting of N (N is a natural number) coefficients is consecutively set to the value of the significant coefficient and before the significant coefficient. It is intended to improve the coding speed in a coding device that performs two-dimensional entropy coding depending on the number of coefficients.

[0016]

In order to solve the above-mentioned problems, the present invention provides N (N) encoding devices.
Is a natural number) and is a coding device for two-dimensional entropy coding a one-dimensional data series consisting of coefficients of significant coefficients and the number of continuous insignificant coefficients, and a storage means for storing the one-dimensional data series, First address generating means for generating a first address for sequentially reading the one-dimensional data series stored in the storage means from the beginning, and one-dimensional data series stored in the storage means sequentially from the end. Second address generating means for generating a second address for reading, encoding means for encoding the one-dimensional data sequence sequentially read from the storage means by the first address, and by the second address Determination means for determining whether each coefficient of the one-dimensional data sequence sequentially read from the storage means is a significant coefficient or an insignificant coefficient; Storage means, the first address generation means, the second address generation means, the control means for controlling the encoding means and the determination means, and the control means operates the encoding means and the determination means at the same time. When the judging means first detects the significant coefficient, the operation of the second address generating means and the judging means is stopped, and then the first address becomes equal to the second address, the first address. The operation of the generating means and the encoding means is stopped to end the encoding of the one-dimensional data series.

The encoding device according to a second aspect of the present invention performs two-dimensional entropy encoding on a one-dimensional data sequence consisting of N (N is a natural number) coefficients by the value of the significant coefficient and the number of consecutive insignificant coefficients. An encoding device, storage means for storing the one-dimensional data series, and first address generation means for generating a first address for sequentially reading the one-dimensional data series stored in the storage means from the beginning. When,
Second address generating means for generating a second address for sequentially reading the one-dimensional data series stored in the storage means from the end, and one-dimensional data series read from the storage means by the first address Generated by the first encoding means, the second encoding means for encoding the one-dimensional data sequence read from the storage means by the second address, and the first encoding means for encoding Connecting means for connecting the code string and the code string generated from the second encoding means into one code string, the storage means, the first address generating means, the second address Generating means, said first encoding means, said second address generating means and control means for controlling said connecting means, said control means comprising said first encoding means and said second encoding means When the second addresses reach a predetermined value, the second address generating means are stopped at the same time, and when the first address becomes equal to the second address, the first address generating means, The operation of the first encoding unit and the second encoding unit is stopped to end the encoding of the one-dimensional data series.

[0018]

In the encoding device according to the first aspect of the present invention, the one-dimensional data sequence consisting of N coefficients is subjected to the two-dimensional entropy code by the value of the significant coefficient and the number of consecutive insignificant coefficients from the beginning. Simultaneously with the conversion, it is judged from the end whether each coefficient is a significant coefficient or an insignificant coefficient.When the first significant coefficient is detected, the judgment is ended and the coding position reaches the position where the judgment is ended. Then, the encoding of the one-dimensional data sequence is completed, so that the encoding speed can be improved.

Further, in the encoding device according to the second aspect of the present invention, a one-dimensional data sequence consisting of N coefficients is two-dimensionally composed of the value of the significant coefficient and the number of consecutive insignificant coefficients from the beginning. While entropy coding,
When the coding is performed from the end as well, and the coding is completed from the end to the predetermined position, the coding ends, and when the position where the coding is performed from the beginning reaches the position where the coding from the end is completed, both encodings are performed. Since the generated code strings are concatenated to complete the coding as one code string, the coding speed can be improved.

[0020]

Embodiments of the present invention will now be described with reference to FIGS.
3 will be used for the explanation. In the following, a number string with x added to the end is in binary notation, a number string with h added is in hexadecimal notation, and a number string with nothing added is 1
It is a zero-based notation.

First, an embodiment of the encoding device described in the first claim will be described with reference to FIGS. 5 to 7 and 8.

In FIG. 5, reference numeral 41 is a memory for storing a one-dimensional data series consisting of 64 coefficients input from an input terminal (not shown) and outputting a coefficient designated by an input address, and 42 is a count. .Enable signal c
If e1 is active, a counter that generates addresses for reading coefficients from the memory 41 in ascending order in synchronization with a clock signal (not shown), and 43 is a clock (not shown) if the count enable signal ce2 is active. A counter which generates addresses for reading coefficients from the memory 41 in a descending order in synchronization with the signal, and 44 encodes the coefficient input first while the control signal ctrl1 is active, by the effective bit number of the coefficient. Left-justified to the code string, the effective bit of the coefficient is extracted, left-justified to the code string, and if the second and subsequent coefficients are insignificant coefficients, an internal insignificant coefficient counter (not shown) ) Is incremented to find a significant coefficient, and if the value of the insignificant coefficient counter at that time is 16 or more, the fourth bit (LS) of the counter Is the 0th bit) and the number of ZRL codes represented by bits equal to or greater than 0 is left-justified in the code string, and the number represented by the lower 4 bits of the counter (for example, if the value of the counter is '20' 4) and the number of significant bits of the significant coefficient, which is left-justified in the code string, and the significant bits of the significant coefficient are cleaved and left-justified in the code string, and 45 is a control signal While ctrl2 is active, determine whether the input coefficient is a significant coefficient or an insignificant coefficient,
A determiner that asserts the signal val if it is a significant coefficient, and 46 is the address adr output from the counter 42
1, a controller that controls the count enable signal cel, the count enable signal ce2, the control signal ctrl1, and the control signal ctrl2 according to the address adr2 output from the counter 43 and the signal val output from the determiner 45. .

Hereinafter, as shown in FIG. 6, a one-dimensional data series consisting of 64 coefficients is stored in the memory 41, and the counter 42, the counter 43, and the insignificant coefficient counter in the encoder 44 (hereinafter (Simply called the insignificant coefficient counter)
Is a 6-bit counter, and the initial values of the counter 42 and the insignificant coefficient counter are '00h' and the initial value of the counter 43 is '3fh', and will be described with reference to the control flowcharts shown in FIGS. 7 and 8. . Note that FIG.
The coefficient map shown in (a) is a one-dimensional data sequence obtained by zigzag scanning the coefficient block shown in FIG. 6 (b) in the order shown in FIG.
It is stored from the beginning up to the address fh. Also,
The flow chart shown in FIG. 7 is a control flow chart of the counter 42 and the encoder 44, and the flow chart shown in FIG. 8 is a control flow chart of the counter 43 and the determiner 45. Zero in FIG. 7 and FIG. The value of the counter, floor (a), represents the number obtained by rounding down the decimal point of a to make it an integer, and amod b represents the remainder of dividing a by b.

First, the initialization operation is performed, and the counter 42,
The counter 43, the encoder 44, and the determiner 45 are initialized (step 611 and step 631). As a result, the coefficient at address 00h for the encoder 44 and the coefficient at address 3fh for the determiner 45, that is, the head coefficient and the tail coefficient of the one-dimensional data series, are output from the storage unit 41 (step 612 and Step 632). Next, the control signal ctrl1 and the control signal ctrl2 are asserted to start the encoder 44 and the determiner 45 (step 613).
And step 633). The encoder 44 encodes the input coefficient from the number of effective bits and adds it to the code string in a left-justified manner (step 614), extracts the effective bit of the coefficient and adds it to the code string in a left-justified manner (step 614). 615), the determiner 4
5 determines whether the input coefficient is a significant coefficient or an insignificant coefficient (step 634).

Thereafter, the decision unit 45 outputs the signal va.
Check if l is asserted (step 63
5) If not asserted, the controller 46 asserts the count enable signal ce2, outputs the coefficient at the next address from the memory 41, and outputs the count enable signal ce2.
2 is negated (step 636) to continue the processing of step 634 and subsequent steps, and if asserted, the controller 46 negates the control signal ctrl2 to stop the operation of the determiner (step 637).

As for the encoder 44, the controller 4
6 checks whether the address adr1 and the address adr2 are equal, and if they are not equal, asserts the count enable signal ce1, outputs the coefficient at the next address from the memory 41, and negates the count enable signal ce1 (step 617). The encoder 44 encodes the input coefficient in the above-described manner (step 618 and thereafter), negates the control signal ctrl1 to stop the operation of the encoder (step 623) when the coefficients are equal, and the encoder 44 When the EOB code is added to the code string by left justification (step 624),
All processing is completed.

Next, another example of the encoding device will be described. The encoder of this other example is the same as the encoder of the above-described embodiment, in which the signal val is asserted or the address ad is added.
Realized by performing the processing of step 637 and thereafter when r2 reaches a predetermined value (for example, address 20h), and performing the processing of step 636 when the signal val is not asserted and the address adr2 does not reach the predetermined value. it can. That is, step 635 in the above embodiment.
Signal val is asserted or address a
It suffices to check whether or not dr2 has reached a predetermined value.

Still another example of the encoding device will be described. The encoding apparatus of this still another example performs the processing from step 637 onward when the signal val is asserted or the difference between the address adrl and the address adr2 reaches a predetermined value (for example, 1) in the above-described embodiment. If the signal val is not asserted and the difference between the address adr1 and the address adr2 does not reach the predetermined value, the process of step 636 can be performed. That is, in the above embodiment, step 635 is executed when the signal val is asserted or the address adr1 is set.
It suffices to check whether the difference between the address and the address adr2 has reached a predetermined value. The above predetermined value is 0,
It is arbitrary within a range up to the difference between the address where the leading coefficient of the one-dimensional data series is stored and the address where the trailing coefficient is stored, but the object of the present invention is to improve the coding speed. A small value is desirable.

Secondly, an embodiment of the encoding device described in claim 2 will be described with reference to FIGS. 9 to 12 and 13. In FIG. 9, reference numeral 71 denotes a storage unit that stores a one-dimensional data series input from an input terminal (not shown) and outputs a coefficient specified by an input address. Reference numeral 72 indicates if the count enable signal cel is active. , A counter for generating addresses in ascending order for reading coefficients from the memory 71 in synchronization with a clock signal (not shown), and 73 is a count enable signal ce
If 2 is active, a counter that generates addresses for reading coefficients from the memory 71 in descending order in synchronization with a clock signal (not shown), 74 is a control signal ctrl
While l is active, the number of significant bits of the coefficient input first is incremented by an internal meaningless coefficient counter (not shown) if the coefficient input is an insignificant coefficient, and if it is a significant coefficient, then If the value of the insignificant coefficient counter of 16 is 16 or more, the ZRL code of the number represented by the 4th bit (LSB is 0th bit) or more of the counter is left-justified to the code string, and the lower 4 bits of the counter are added. The control signal ctrl is encoded by the number expressed in bits and the number of significant bits of the significant coefficient and left-justified in the code string, and the significant bit of the significant coefficient is extracted and left-justified in the code string.
When l is negated, the forward encoder, which terminates the encoding operation after the termination operation described later, 75 is the control signal ctrl
While 2 is asserted, the input coefficient is subjected to backward two-dimensional Huffman coding, which will be described later, to output a code, and when the control signal ctrl2 is negated, the coding operation ends after the ending operation described below. Insignificant coefficient counter (not shown)
A backward encoder which incorporates a code, 76 is a concatenator which concatenates the code strings output from the encoder 74 and the encoder 75 and outputs as one code string, and 77 is an address adr1 output from the counter 72 Also, the controller controls the count enable signal cel, the count enable signal ce2, the control signal ctrl1 and the control signal ctrl2 according to the address adr2 output from the counter 73.

Here, the backward two-dimensional Huffman coding in the backward encoder 75 and the concatenation operation of the code strings in the concatenator 76 will be described.

First, the backward two-dimensional Huffman coding in the backward encoder 75 will be described with reference to FIGS. 10 and 11. For example, when two-dimensional Huffman coding is performed on a one-dimensional data sequence as shown in FIG. 10 by the number of significant bits of a significant coefficient and the number of consecutive insignificant coefficients before the coefficient, normal coding (forward coding 11), the corresponding significant code '1011x' on the encoding table illustrated in FIG. 11 is extracted by the effective bit number 4 of the first significant coefficient '10' and the number 0 of consecutive insignificant coefficients before that. Left-justified to the code string, and the effective bit of the coefficient '10'is' 101
0x 'is added left-justified to the code string. The next significant coefficient after the significant coefficient '10' is the coefficient '15', and since there are four insignificant coefficients before it, the significant bit number of the coefficient '15' and the number of consecutive insignificant coefficients 4 sign '1111,1
111,1001,0111x 'is extracted and added to the code string by left-justification, and the effective bit' 111 of the coefficient '15'.
1x 'is added to the code string left justified. The coefficient '15' is the last coefficient of the l-dimensional data sequence, so the code string '1'
011,1010,1111,1111,1001,0
111, llllx 'are finally obtained.

When backward coding a one-dimensional data sequence, effective bits of significant coefficients are right-justified in a code string, and an encoding table is obtained according to the number of effective bits of the significant coefficients and the number of consecutive insignificant coefficients. Add the corresponding code above with right justification. When the one-dimensional data series shown in FIG. 10 is subjected to backward two-dimensional Huffman coding, the first significant coefficient '1
5'significant bits '1llllx' are added to the code string right justified, counting the number of insignificant coefficients until the next significant coefficient is detected. The significant coefficient next to the coefficient “15” is the coefficient “10”, the number of insignificant coefficients following the coefficient “15” is 4, and the number of effective bits of the coefficient “15” is 4. Therefore, the sign “ 1111, 1111, 1001, 0111x 'are extracted and right-justified to the code string, and the effective bit' 1010x 'of the coefficient' 10 'is right-justified to the code string.
Since the coefficient "10" is the last coefficient in the one-dimensional data series when viewed from the opposite direction, it is signed by the number of effective bits 4 of the coefficient "10" and the number of consecutive insignificant coefficients 0.
1011x ′ is extracted and added right-justified to the code string.

As a result of the above, the same code string as that in the forward two-dimensional Huffman coding is finally obtained.

The backward encoder 75 encodes a code indicating that the coding of the one-dimensional data series is completed if the first input coefficient, that is, the last coefficient of the one-dimensional data series is an insignificant coefficient. After adding to the column right-justified, the above backward encoding is performed.

Next, the code string concatenation operation in the concatenator 76 will be described. As described above, the forward encoder 74 encodes the one-dimensional data sequence in the forward direction from the head, and the backward encoder 75 encodes the one-dimensional data sequence in the backward direction from the end. The encoded code strings are output. The concatenator 76 outputs the forward code string output from the forward encoder 74 as it is, and stores the backward code string output from the backward encoder 75 in the internal buffer in the right-justified manner. When the output from the forward coder 74 is completed, the stored backward code sequence following the forward code sequence is sequentially output from the left.

Hereinafter, as in the first embodiment, the one-dimensional data series is stored in the storage 71, and the counter 72, the counter 73, the insignificant coefficient counter in the forward encoder 74 and the backward encoder. The insignificant coefficient counter in 75 is a 6-bit counter. The initial values of the counter 72 and both insignificant coefficient counters are "00h", and the initial value of the counter 43 is "3".
Taking the case of fh ′ as an example, description will be made with reference to the control flowcharts shown in FIGS. 12 and 13. Note that the flowchart shown in FIG. 12 is a control flowchart of the counter 72 and the forward encoder 74, the flowchart shown in FIG. 13 is a control flowchart of the counter 73 and the backward encoder 75, and floor (a) is a mod b is the number obtained by rounding down the number after the decimal point of a to obtain an integer.
12 is the value of the insignificant coefficient counter in the forward encoder 74, and z2 in FIG. 13 is the value of the insignificant coefficient counter in the backward encoder 75. Represent

First, the initialization operation is performed, and the counter 72,
The counter 73, the forward encoder 74, and the backward encoder 76 are initialized (step 101 and step 12).
1). This causes 00h for the forward encoder 74.
For the address and backward encoder 75, the coefficient at address 3fh is output from the memory 71 (step 102 and step 122). Next, the control signal ctrl1 and the control signal ctrl2 are asserted to start the forward encoder 74 and the backward encoder 75 (step 103 and step 123). After that, the forward encoder 74 and the backward encoder 75 perform forward and backward encoding in the above-described manner (step 104 and after and step 124 and after). When the address adr2 becomes equal to the fixed address ADR, the controller 77 negates the control signal ctrl2 to stop the operation of the backward encoder 75 (step 137), and the backward encoder 75 forward codes. It waits for the output from the rectifier 76 (step 138). Also, the address a
When the dr1 and the address adr2 become equal, the controller 7
7 negates the control signal ctrl1 to stop the operation of the forward encoder 74 (step 113), and the forward encoder 74 performs backward encoding if the last input coefficient at that time is a significant coefficient. The operation is terminated without outputting anything to the device 75, and if it is an insignificant coefficient, the ZRL code of the number represented by the 4th bit or more of the insignificant coefficient counter in the forward encoder at that time is left. The data is padded and added to the code string, and the lower 4 bits of the counter are output to the backward encoder 75 (step 114 above). The backward encoder 75 receives the output from the forward encoder, and if the coefficient last input to the backward encoder 75 is a significant coefficient, the number of effective bits of the coefficient and the forward encoder are calculated. It is encoded by the output code3 from 76 and added to the code string in the right column, and the operation ends (step 189 above).

In another example, after the backward encoder 75 is started in the above embodiment, it is checked whether the difference between the address adrl and the address adr2 is a predetermined value, for example, 1 or less. For example, if the processing after step 137 is larger than the running value, the processing after step 136 or after step 128 may be performed. This is done by checking whether the difference between the address adrl and the address adr2 is less than or equal to a predetermined value. And that step 135 may be replaced.

The embodiments of the encoding device described in the first claim and the embodiments of the encoding device described in the second claim have been described above. It should be noted that the configuration and operation algorithm of any of the embodiments are not limited to those of the above embodiments, and in the first embodiment, the storage means for storing the one-dimensional data series and the storage means store the one-dimensional data series. A first address generating means for generating a first address for sequentially reading the existing one-dimensional data series from the beginning, and a second address for sequentially reading the one-dimensional data series stored in the storage means from the end. Second address generating means for generating,
Whether the encoding means for encoding the one-dimensional data series sequentially read from the storage means by the first address and the significant coefficient or the insignificant coefficient are each coefficient of the one-dimensional data series sequentially read from the storage means by the second address. And a control means for controlling the storage means, the first address generation means, the second address generation means, the encoding means and the determination means, and the operation of the encoding device according to the present invention. Any configuration and operation algorithm may be used as long as the configuration and operation algorithm are realized.

In the second embodiment, the storage means for storing the one-dimensional data series and the first address for sequentially reading the one-dimensional data series stored in the storage means from the beginning are generated. Address generating means, second address generating means for generating a second address for sequentially reading the one-dimensional data series stored in the storing means from the end, and the first address sequentially reading from the storing means. Coding means for coding the one-dimensional data series, coding means for coding the one-dimensional data series sequentially read from the storage means by the second address, and a code string generated by the first coding means. Fast connecting means for connecting the code strings generated from the second encoding means into one code string, storage means, first address generating means, second address Any configuration and operation algorithm may be used as long as the configuration and the operation algorithm are provided so as to realize the operation of the encoding device according to the present invention, and the control means for controlling the live means, the forward encoding means, and the backward encoding means. I do not care.

Further, in the above description, the two-dimensional Huffman coding is taken as an example of the coding, but if the one-dimensional data series is the two-dimensional entropy coding by the significant coefficient and the number of consecutive insignificant coefficients, the coding is performed. The type does not matter.

In the above, the one-dimensional data series shown in FIG. 6 is taken as an example, but it is clear that the contents and the number of coefficients are not limited to this.

[0043]

The encoding device according to the first aspect of the present invention can detect the final significant coefficient of the one-dimensional data series simultaneously with the encoding from the head of the one-dimensional data series,
Since the encoding can be completed at the final significant coefficient of the one-dimensional data series, the time required for encoding after the final significant coefficient can be reduced and the encoding speed can be improved.

Further, in the encoding device described in the second aspect of the present invention, the encoding speed is improved while the encoding device for encoding the one-dimensional data series only from the beginning and the generated code are completely compatible. Can be planned.

[Brief description of drawings]

FIG. 1 is a diagram showing a processing flow of a JPEG algorithm at the time of image compression.

FIG. 2 is a diagram showing a coding flow of a JPEG algorithm at the time of image compression.

3A and 3B are diagrams showing blocks before and after performing DCT.

FIG. 4 is a diagram showing a zigzag scan order in a JPEG algorithm during image compression.

FIG. 5 is an embodiment of an encoding device according to the first aspect of the present invention.

6A is a diagram showing an example of a one-dimensional data series stored in a storage device 41 in the embodiment of FIG.
FIG. 6B is a diagram showing a state before the zigzag scan of an example of the one-dimensional data series stored in the storage unit 41 in the embodiment of FIG.

FIG. 7 is a first part of a diagram showing a processing flow in the embodiment of FIG.

FIG. 8 is a second part of the diagram showing the processing flow in the embodiment of FIG.

FIG. 9 is an embodiment of an encoding device according to the second aspect of the present invention.

FIG. 10 is a diagram for explaining backward encoding in the backward encoder 75 in the embodiment of FIG.

FIG. 11 is a diagram showing an example of a two-dimensional encoding table.

FIG. 12 is a first part of a diagram showing a processing flow in the embodiment of FIG.

FIG. 13 is a second part of the diagram showing the processing flow in the embodiment of FIG. 9;

[Explanation of symbols]

11-15 ... Each step in the processing flow in FIG.
201-215 ... Each step in the encoding flow in FIG. 2, 41 ... Memory device, 42 ... Counter, 43 ... Counter, 44 ... Encoder, 45 ... Judgment device, 46 ... Controller, 6
01 to 617 and 621 to 627 ... Each step in the process flow in FIGS. 7 and 8, 71 ... Memory device, 72 ... Counter, 73 ... Counter, 74 ... Forward encoder, 75 ...
Reverse encoder, 76 ... Concatenator, 77 ... Controller, 101
To 117 and 121 to 142 ... Steps in the process flow in FIGS.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03M 7/40 9382-5K H04N 7/30

Claims (2)

[Claims] 1. An encoding device for performing two-dimensional entropy encoding of a one-dimensional data series consisting of N (N is a natural number) coefficients by the value of a significant coefficient and the number of continuous insignificant coefficients, said one-dimensional data A storage unit for storing the sequence, a first address generation unit for generating a first address for sequentially reading the one-dimensional data sequence stored in the storage unit from the beginning, and a storage unit stored in the storage unit. Second address generating means for generating a second address for sequentially reading the one-dimensional data series from the end, and encoding for encoding the one-dimensional data series sequentially read from the storage means by the first address Means and whether each coefficient of the one-dimensional data series sequentially read from the storage means by the second address is a significant coefficient or an insignificant coefficient. And a storage unit, a first address generation unit, a second address generation unit, a control unit for controlling the encoding unit and the determination unit, the control unit and the encoding unit The determining means are operated simultaneously, and when the determining means first detects a significant coefficient, the operations of the second address generating means and the determining means are stopped, and then the first address becomes equal to the second address. In this case, the operation of the first address generating means and the encoding means is stopped and the encoding of the one-dimensional data series is ended. 2. An encoding device for performing two-dimensional entropy encoding of a one-dimensional data series consisting of N (N is a natural number) coefficients by the value of a significant coefficient and the number of continuous insignificant coefficients, wherein the one-dimensional data Storage means for storing the sequence; first address generation means for generating a first address for sequentially reading the one-dimensional data sequence stored in the storage means from the beginning; and the storage means. Second address generating means for generating a second address for sequentially reading the one-dimensional data series from the end; and a first code for encoding the one-dimensional data series read from the storage means by the first address. Encoding means, second encoding means for encoding the one-dimensional data sequence read from the storage means by the second address, and the first encoding means Connecting means for connecting the code sequence generated by the second encoding means and the code sequence generated by the second encoding means into one code sequence, the storing means, the first address generating means, the first address generating means, A second address generating means, the first encoding means, a control means for controlling the second address generating means and the connecting means, wherein the control means is the first encoding means and the second code. The second address generating means is stopped when the second address reaches a predetermined value, and then the first address is generated when the first address becomes equal to the second address. A coding apparatus, characterized in that the operations of the means, the first coding means and the second coding means are stopped to finish the coding of the one-dimensional data sequence.