JP3276037B2 - Encoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding apparatus, and more particularly, to a two-dimensional encoding method for converting a one-dimensional data sequence composed of N (N is a natural number) coefficients into a two-dimensional data sequence by using significant coefficient values and continuous insignificant coefficient numbers. The present invention relates to an encoding device that performs entropy encoding.

[0002]

2. Description of the Related Art In recent years, techniques for reducing storage capacity and communication time when handling digital image data have been developed.
Image compression technology, especially ISO / ITU-TS (former CC
JPEG algorithm standardized as an international standard by (ITT) (ISO / IECDIS 10918-1)
Is attracting attention.

The outline of the JPEG algorithm for compressing data will be described below with reference to FIGS.

First, input image data is divided into blocks (hereinafter abbreviated as blocks) of 8 pixels in the main scanning direction and 8 pixels in the sub-scanning direction (not shown). Next, the divided blocks are subjected to a two-dimensional discrete cosine transform (hereinafter abbreviated as DCT) according to equation (1) (step 11). In equation (1), f (i, j) is the i-th main scanning direction and the sub-scanning direction j in the block before conversion as shown in FIG.
As shown in FIG. 3B, F (u, v) represents the u-th converted value in the main scanning direction and the v-th converted value in the sub-scanning direction in the converted block.

[0005]

(Equation 1) A block (hereinafter abbreviated as DCT block) converted into a frequency component (DCT coefficient) by DCT is quantized by a predetermined quantization table (step 12). The quantized DCT blocks are rearranged into a one-dimensional data sequence composed of 64 coefficients by zigzag scanning in the order shown in FIG. 4 (step 13). The rearranged one-dimensional data sequence is encoded (step 14). It is checked whether encoding of all blocks is completed (step 15).
If not, the next block is encoded by steps 11 to 14.

Next, the encoding of the one-dimensional data series in step 14 will be described with reference to FIG. In FIG. 2, n represents the number of the second and subsequent coefficients of the one-dimensional data series, that is, the number of the AC coefficient, and zero represents the number of consecutive insignificant coefficients. Floor (a) is a modb which is a number obtained by converting a to an integer by truncating the decimal part.
Means the remainder of dividing a by b.

First, the first coefficient, that is, the DC coefficient, is one-dimensionally Huffman-coded by the number of effective bits of the value (for example, if the DC coefficient value is “7”, the number of effective bits is 3), and the code is converted into a code string. (Step 202), and an effective bit of the coefficient (for example, if the DC coefficient value is '7', the effective bit is '111') is added to the code string (step 2).
03).

Next, from the second coefficient to the 64th coefficient,
That is, the coding of the AC coefficient is the nth (where n is 1 ≦ n ≦ 6).
It is checked whether or not the AC coefficient of “3” is “0” (step 205), and if it is not “0”, zero is 1
It is checked whether it is smaller than 6 (step 206).
If ro is equal to or greater than 16, a code (ZRL code) indicating that an integer number of 16 insignificant coefficients following the decimal point of the quotient obtained by dividing zero by 16 is added to the code sequence (step 207), and zero is added to zero. Is divided by 16 (step 208). If zero is smaller than 16, nothing is performed, and two-dimensional Huffman coding is performed using the value of zero at that time and the number of effective bits of the AC coefficient. Is added to the code string (step 209), the effective bit of the AC coefficient is added to the code string (step 210), and whether the AC coefficient is the 63rd AC coefficient, that is, the last coefficient of the one-dimensional data sequence. Check whether (Step 21
1) If the last coefficient, the coding is terminated; if not the last coefficient, zero is set to zero, and the processing from step 205 onward is performed for the (n + 1) th AC coefficient.

If the nth AC coefficient is "0", it is checked whether the AC coefficient is the 63rd AC coefficient, that is, the last coefficient of the one-dimensional data sequence (step 213). If it is the coefficient, the code (EOB code) indicating the end of the one-dimensional data sequence is added to the code string (step 214). If it is not the last coefficient, 1 is added to zero, and the step 205 is performed for the (n + 1) th AC coefficient.
The following processing is performed.

[0010] In the above manner, when encoding is performed up to the 63rd AC coefficient, that is, the last coefficient of the l-dimensional data sequence, step 14 ends. In the above,
If the significant coefficient is a negative value, the number of significant bits is the number of significant bits of the absolute value of the coefficient, and the number of significant bits is the number of significant bits from the LSB of the 0's complement representation of a value obtained by subtracting 1 from the coefficient. is there. For example, if the significant coefficient is '-3', the number of effective bits is 2 bits, and the value obtained by subtracting 1 from the coefficient is 8
Since the 0's complement expression in bits is 1111 and 1101, the effective bit is 01.

Since image data often changes smoothly in the range of blocks, significant coefficients concentrate on DC coefficients and low-frequency AC coefficients, and many blocks have a high ratio of insignificant coefficients in high-frequency AC coefficients. The latter half of the one-dimensional data series often has almost insignificant coefficients. According to the above, if a coefficient from a coefficient following a certain significant coefficient to a last coefficient in a one-dimensional data series is an insignificant coefficient, the part may be encoded into an EOB code. Since a code with a code length close to that is assigned, high compression efficiency can be realized.

[0012]

By the way, the above-mentioned 64
In the encoding of a one-dimensional data sequence composed of a number of coefficients, since the one-dimensional data sequence is sequentially encoded from the beginning, the one-dimensional data sequence is encoded until the 64th coefficient of the one-dimensional data sequence is reached. In this case, the position of the last significant coefficient is not known, which hinders an improvement in the encoding speed of the one-dimensional data sequence.

As a technique for solving this problem, for example, there is a technique disclosed in Japanese Patent Application Laid-Open No. 5-83564. In this technique, zigzag scanning is started from the end of a one-dimensional data sequence first, and when a significant coefficient is detected first, coding is started from the beginning of the one-dimensional data sequence, and coding is performed at a position where a significant coefficient is detected first. Is to end.

However, this is obtained by changing the scan order in the one-dimensional data sequence, and the time required for encoding the one-dimensional data sequence is the time required for encoding the one-dimensional data sequence from the beginning to the end. There is no difference.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and a method of converting a one-dimensional data sequence including N (N is a natural number) coefficients into a significant coefficient value and a continuous insignificant value before the significant coefficient. In a coding apparatus that performs two-dimensional entropy coding according to the number of coefficients, the coding speed is improved.

[0016]

According to the present invention, in order to solve the above-mentioned problems, the encoding apparatus according to claim 1 comprises N (N
A two-dimensional entropy coding of a one-dimensional data sequence consisting of natural number coefficients by the value of a significant coefficient and the number of continuous insignificant coefficients, and a storage means for storing the one-dimensional data sequence; First address generating means for generating a first address for sequentially reading the one-dimensional data series stored in the storage means from the beginning, and sequentially storing the one-dimensional data series stored in the storage means from the end Second address generating means for generating a second address for reading; encoding means for encoding a one-dimensional data sequence sequentially read from the storage means by the first address; Determining means for determining whether each coefficient of the one-dimensional data sequence sequentially read from the storage means is a significant coefficient or an insignificant coefficient; Control means for controlling the first address generating means, the second address generating means, the encoding means and the judging means, wherein the control means operates the encoding means and the judging means simultaneously. And when the determining means first detects a significant coefficient, stops the operations of the second address generating means and the determining means, and thereafter, when the first address becomes equal to the second address, the first address. The operation of the generating means and the encoding means is stopped, and the encoding of the one-dimensional data sequence is terminated.

Further, the encoding apparatus according to the second aspect performs two-dimensional entropy encoding of a one-dimensional data sequence composed of N (N is a natural number) coefficients by using the value of a significant coefficient and the number of consecutive insignificant coefficients. An encoding device, comprising: storage means for storing the one-dimensional data sequence; and first address generation means for generating a first address for sequentially reading the one-dimensional data sequence stored in the storage means from the beginning. When,
Second address generating means for generating a second address for sequentially reading the one-dimensional data series stored in the storage means from the end, and a one-dimensional data series read from the storage means by the first address First encoding means for encoding a one-dimensional data sequence read from the storage means by the second address; and Connecting means for connecting a code string generated by the second coding means to a code string generated by the second coding means, the storage means, the first address generating means, and the second address. Control means for controlling the generating means, the first coding means, the second address generating means and the linking means, wherein the control means comprises the first coding means and the second coding means Operating simultaneously, stopping the second address generation means when the second address reaches a predetermined value, and then when the first address becomes equal to the second address, the first address generation means, The operation of the first encoding unit and the second encoding unit is stopped, and the encoding of the one-dimensional data sequence is terminated.

[0018]

In the encoding apparatus according to the first aspect, a one-dimensional data sequence composed of N coefficients is converted into a two-dimensional entropy code by using a significant coefficient value from the beginning and the number of consecutive insignificant coefficients. At the same time, it is determined from the end whether each coefficient is a significant coefficient or an insignificant coefficient. When a significant coefficient is detected first, the determination ends, and the position where encoding is performed reaches the position where the determination is completed. Then, since the encoding of the one-dimensional data sequence is completed, the encoding speed can be improved.

Further, in the encoding device described in claim 2, the one-dimensional data sequence composed of N coefficients is converted into two-dimensional data by the value of the significant coefficient from the beginning and the number of continuous insignificant coefficients. At the same time as entropy coding,
Encoding is also performed from the end, and when encoding is performed from the end to a predetermined position, the encoding is terminated.When the position where encoding from the beginning reaches the position where encoding from the end is completed, both encodings are performed. Since the generated code strings are concatenated to end the coding as one code string, the coding speed can be improved.

[0020]

FIG. 5 to FIG. 12 and FIG.
3 will be described. Note that, in the following, a numeral string with x added at the end is represented in binary, a numeral string with h added is represented in hexadecimal, and a numeral string without any addition is 1
It is a decimal number notation.

First, an embodiment of the coding apparatus described in claim 1 will be described with reference to FIGS. 5 to 7 and FIG.

In FIG. 5, reference numeral 41 denotes a storage for storing a one-dimensional data sequence composed of 64 coefficients inputted from an input terminal (not shown) and outputting a coefficient designated by an inputted address; .Enable signal c
If e1 is active, a counter for generating addresses for reading coefficients from the storage device 41 in ascending order in synchronization with a clock signal (not shown) is provided. 43 is a clock (not shown) provided that the count enable signal ce2 is active. A counter 44 for generating an address for reading out a coefficient from the memory 41 in descending order in synchronization with the signal. The counter 44 encodes the first inputted coefficient by the number of effective bits of the coefficient while the control signal ctrl1 is active. To the code string left-justified, extract the significant bits of the coefficient and add it to the code string left-justified. If the second and subsequent coefficients are insignificant coefficients, an internal insignificant coefficient counter (not shown) ) Is incremented, and if the value of the insignificant coefficient counter at that time is 16 or more, the fourth bit (LS Is the zeroth bit) or more ZRL codes of the number represented by the bits or more are added left-justified to the code string, and the number represented by the lower 4 bits of the counter (for example, if the value of the counter is '20', 4) an encoder that encodes by using the significant bits of the significant coefficient and adds the significant bits to the code string left-justified, determines the significant bits of the significant coefficients and adds the significant bits to the code string left-justified, and 45 is a control signal. While ctrl2 is active, it is determined whether the input coefficient is a significant coefficient or an insignificant coefficient,
If it is a significant coefficient, the decision unit asserts the signal val. 46 is the address adr output from the counter 42.
1, a controller that controls the count enable signal cel, the count enable signal ce2, the control signal ctrl1, and the control signal ctrl2 according to the address adr2 output from the counter 43 and the signal val output from the decision unit 45. .

As shown in FIG. 6, a one-dimensional data sequence consisting of 64 coefficients is stored in a storage unit 41, and a counter 42, a counter 43, and an insignificant coefficient counter (hereinafter, referred to as a counter) in an encoder 44. Simply called the insignificant coefficient counter)
Is a 6-bit counter. The case where the initial value of the counter 42 and the insignificant coefficient counter is "00h" and the initial value of the counter 43 is "3fh" will be described with reference to the control flowcharts shown in FIGS. . FIG.
The coefficient map shown in (a) is a three-dimensional data series obtained by zigzag scanning the coefficient block shown in FIG. 6B in the order shown in FIG.
The data is stored in order from the head up to the address fh. Also,
The flowchart shown in FIG. 7 is a control flowchart of the counter 42 and the encoder 44, and the flowchart shown in FIG. 8 is a control flowchart of the counter 43 and the determiner 45. Zero in FIGS. The value of the counter, floor (a) represents a number obtained by rounding off a below the decimal point of a and converted to an integer, and amod b represents a remainder obtained by dividing a by b.

First, an initialization operation is performed, and a counter 42,
The counter 43, the encoder 44, and the determiner 45 are initialized (steps 611 and 631). Thus, the coefficient at address 00h for the encoder 44 and the coefficient at address 3fh for the decision unit 45, that is, the first coefficient and the last coefficient of the one-dimensional data sequence, respectively, are output from the storage unit 41 (steps 612 and 612). Step 632). Next, the control signal ctrl1 and the control signal ctrl2 are asserted to start the encoder 44 and the decision unit 45 (step 613).
And step 633). The encoder 44 encodes the input coefficient from the number of effective bits and adds it to the code string left-justified (step 614), extracts the effective bits of the coefficient, and adds it to the code string left-justified (step 614). 615), judgment device 4
5 determines whether the input coefficient is a significant coefficient or a meaningless coefficient (step 634).

Thereafter, the signal va
It is checked whether or not 1 is asserted (step 63
5) If not asserted, the controller 46 asserts the count enable signal ce2, outputs the coefficient at the next address from the memory 41, and outputs the count enable signal ce2.
2 is negated (step 636), and the processing following step 634 is continued. If asserted, the controller 46 negates the control signal ctrl2 and stops the operation of the determiner (step 637).

The encoder 44 includes a controller 4
6 checks whether the address adr1 is equal to the address adr2, and if they are not equal, asserts the count enable signal ce1 and outputs the coefficient of the next address from the memory 41 to negate the count enable signal ce1 (step 617). , The encoder 44 encodes the inputted coefficients in the manner described above (step 618 and thereafter), negates the control signal ctrl1 if they are equal, and stops the operation of the encoder (step 623). When the EOB code is added to the code string left-justified (step 624),
All processing ends.

Next, another example of the encoding apparatus will be described. In another embodiment of the encoding device, the signal val is asserted or the address ad is
When r2 reaches a predetermined value (for example, address 20h), the processing after step 637 is performed, and when signal val is not asserted and address adr2 does not reach the predetermined value, processing is performed by step 636. it can. That is, in the above embodiment, step 635 is performed.
Is determined whether the signal val is asserted or the address a
What is necessary is just to check whether dr2 has reached the predetermined value.

Further, another example of the encoding apparatus will be described. The encoding apparatus according to the still another example performs the processing after step 637 when the signal val is asserted or the difference between the address adrl and the address adr2 reaches a predetermined value (for example, 1) in the above-described embodiment. If the signal val is not asserted and the difference between the address adr1 and the address adr2 does not reach a predetermined value, the process of step 636 is performed. That is, in the above-described embodiment, step 635 is performed when the signal val is asserted or when the address adr1
It is sufficient to check whether the difference between the address and the address adr2 has reached a predetermined value. In addition, the above predetermined value is from 0,
Any one of the range up to the difference between the address at which the leading coefficient of the one-dimensional data sequence is stored and the address at which the ending coefficient is stored can be used. However, the object of the present invention is to improve the encoding speed. Desirably, the value is small.

Second, an embodiment of the encoding apparatus described in claim 2 will be described with reference to FIGS. 9 to 12 and 13. FIG. In FIG. 9, reference numeral 71 denotes a storage device for storing a one-dimensional data sequence input from an input terminal (not shown) and outputting a coefficient specified by an input address; and 72, if the count enable signal cel is active. A counter for generating addresses for reading coefficients from the storage device 71 in ascending order in synchronization with a clock signal (not shown);
If 2 is active, a counter 74 generates addresses for reading coefficients from the storage device 71 in descending order in synchronization with a clock signal (not shown), and a counter 74 generates a control signal ctrl.
While 1 is active, the number of effective bits of the coefficient to be input first is incremented by an internal insignificant coefficient counter (not shown) if the input coefficient is an insignificant coefficient, and if it is a significant coefficient, If the value of the insignificant coefficient counter is 16 or more, the number of ZRL codes represented by bits equal to or more than the fourth bit (LSB is the 0th bit) of the counter is added to the code string left justified, and the lower 4 A control signal ctrl is generated by coding the number represented by the bits and the number of significant bits of the significant coefficient and adding it to the code string left-justified, extracting the significant bits of the significant coefficient and adding it to the code string left-justified,
When n is negated, the forward encoder 75 that terminates the encoding operation after the termination operation described later, 75 controls the control signal ctrl.
While 2 is asserted, the input coefficient is subjected to backward two-dimensional Huffman encoding described later to output a code. When the control signal ctrl2 is negated, the encoding operation is terminated after the termination operation described later. Insignificant coefficient counter (not shown)
, A concatenator for concatenating the code strings output from the encoder 74 and the encoder 75 and outputting as one code string, 77 a address adr1 output from the counter 72 And a controller that controls the count enable signal cel, the count enable signal ce2, the control signal ctrl1, and the control signal ctrl2 in accordance with the address adr2 output from the counter 73.

Here, the operation of the backward two-dimensional Huffman coding in the backward encoder 75 and the concatenation of the code strings in the coupler 76 will be described.

First, the backward two-dimensional Huffman coding in the backward encoder 75 will be described with reference to FIGS. For example, when a one-dimensional data sequence as shown in FIG. 10 is subjected to two-dimensional Huffman coding by the number of significant bits of a significant coefficient and the number of consecutive insignificant coefficients before the coefficient, ordinary coding (forward code ), The corresponding code '1011x' on the coding table illustrated in FIG. 11 is extracted by using the number 4 of effective bits of the first significant coefficient '10' and the number of consecutive insignificant coefficients 0 before it. To the code string, left-justified, and the effective bit '101 of coefficient' 10 '
0x 'is added to the code string left-justified. The next significant coefficient after the significant coefficient '10' is the coefficient '15', which is preceded by four insignificant coefficients. Therefore, the sign is determined by the number of effective bits of the coefficient '15' and the number of consecutive insignificant coefficients '4'. '1111,1
111, 1001, 0llx 'are extracted and added to the code string left-justified, and the effective bit' 111 'of the coefficient' 15 'is extracted.
1x 'is added to the code string left-justified. Since the coefficient '15' is the last coefficient of the l-dimensional data series, the code string '1'
011,1010,1111,1111,1001,0
111, llllx 'is finally obtained.

When the one-dimensional data sequence is reverse-coded, the significant bits of the significant coefficient are added to the code string right-justified, and the coding table is calculated based on the number of significant bits of the significant coefficient and the number of subsequent insignificant coefficients. Encode the relevant code above and add it right-justified. When the one-dimensional data sequence shown in FIG. 10 is subjected to reverse two-dimensional Huffman coding, the first significant coefficient '1
A 5 'valid bit' 11llx 'is added to the code string right-justified, and the number of insignificant coefficients is counted until the next significant coefficient is detected. The next significant coefficient after the coefficient '15' is the coefficient '10', the number of insignificant coefficients following the coefficient '15' is four, and the number of effective bits of the coefficient '15' is four. 1111, 1111, 1001, 0llx 'are extracted and added to the code string right-justified, and the effective bit' 1010x 'of the coefficient' 10 'is added to the code string right-justified.
Since the coefficient '10' is the last coefficient in the one-dimensional data sequence when viewed from the opposite direction, the code '10' is signified by the number of effective bits 4 of the coefficient '10' and the number 0 of subsequent insignificant coefficients
1011x 'is extracted and added to the code string right-justified.

As described above, the same code sequence as in the forward two-dimensional Huffman coding is finally obtained.

The backward encoder 75 encodes the first input coefficient, that is, if the last coefficient of the one-dimensional data sequence is an insignificant coefficient, the code indicating that the encoding of the one-dimensional data sequence has been completed. After adding to the column right-justified, the above-described reverse encoding is performed.

Next, a description will be given of the operation of connecting the code strings in the connector 76. As described above, a code sequence obtained by coding the one-dimensional data sequence in the forward direction from the forward encoder 74 and the one-dimensional data sequence in the backward direction from the tail is output from the backward encoder 75. Each of the encoded code strings is output. The coupler 76 outputs the forward code string output from the forward encoder 74 as it is, and stores the backward code string output from the backward encoder 75 in the internal buffer right-justified. When the output from the forward encoder 74 is completed, the backward code sequence stored after the forward code sequence is sequentially output from the left.

Thereafter, as in the first embodiment, a one-dimensional data sequence is stored in the storage unit 71, and the counter 72, the counter 73, the insignificant coefficient counter in the forward encoder 74, and the reverse encoder are used. The insignificant coefficient counter in 75 is a 6-bit counter, the initial value of the counter 72 and both insignificant coefficient counters is “00h”, and the initial value of the counter 43 is “3”.
The case where fh ′ is set as an example will be described together with the control flowcharts shown in FIGS. Note that the flowchart shown in FIG. 12 is a control flowchart of the counter 72 and the forward encoder 74, and the flowchart shown in FIG. 13 is a control flowchart of the counter 73 and the backward encoder 75. a mod b is a number obtained by rounding down the decimal part of a and converting it to an integer.
12, z1 in FIG. 12 is the value of the insignificant coefficient counter in the forward encoder 74, and z2 in FIG. 13 is the value of the insignificant coefficient counter in the backward encoder 75, respectively. Represent.

First, an initialization operation is performed, and a counter 72,
Initialize the counter 73, the forward encoder 74, and the backward encoder 76 (Step 101 and Step 12).
1). This gives 00h to forward encoder 74.
The coefficient at the address 3fh is output from the storage unit 71 to the address / inverse encoder 75 (steps 102 and 122). Next, the control signal ctrl1 and the control signal ctrl2 are asserted, and the forward encoder 74 and the backward encoder 75 are started (steps 103 and 123). Thereafter, the forward encoder 74 and the backward encoder 75 perform forward and backward encoding in the manner described above (steps 104 and after and steps 124 and after). When the address adr2 becomes equal to the fixed address ADR, the controller 77 negates the control signal ctrl2 and stops the operation of the backward encoder 75 (step 137). The output from the converter 76 is waited (step 138). Address a
When dr1 and address adr2 become equal, the controller 7
7 negates the control signal ctrl1 and stops the operation of the forward encoder 74 (step 113), and the forward encoder 74 performs reverse encoding if the last input coefficient at that time is a significant coefficient. The operation is terminated without outputting anything to the encoder 75, and if it is an insignificant coefficient, the ZRL code of the number represented by the fourth or more bits of the insignificant coefficient counter in the forward encoder at that time is left The lower 4 bits of the counter are output to the reverse encoder 75 (step 114). After receiving the output from the forward encoder, the backward encoder 75, if the last coefficient input to the backward encoder 75 is a significant coefficient, determines the number of effective bits of the coefficient and the forward encoder. The code is encoded by the output code3 from the code 76 and added to the code string in the right column, and the operation is terminated (step 189).

In another example, after the backward encoder 75 is started in the above embodiment, it is checked whether the difference between the address adrl and the address adr2 is a predetermined value, for example, 1 or less. For example, the process after step 137 may be performed, and if it is larger than the preset value, the process after step 136 or step 128 may be performed. In step 127, it is determined whether the difference between the address adrl and the address adr2 is equal to or smaller than a predetermined value. And step 135 may be replaced.

As described above, the first embodiment of the coding apparatus described in claim 1 and the second embodiment of the coding apparatus described in claim 2 have been described. Note that, in any of the embodiments, the configuration and the operation algorithm are not limited to the above-described embodiments. For the first embodiment, a storage unit that stores a one-dimensional data sequence and a storage unit that stores the one-dimensional data series are used. A first address generating means for generating a first address for sequentially reading the one-dimensional data series from the beginning, and a second address for sequentially reading the one-dimensional data series stored in the storage means from the end. Second address generating means for generating,
Encoding means for encoding a one-dimensional data sequence sequentially read from the storage means by the first address; and determining whether each coefficient of the one-dimensional data series sequentially read from the storage means by the second address is a significant coefficient or an insignificant coefficient And a control means for controlling the storage means, the first address generation means, the second address generation means, the coding means and the determination means, and the operation of the coding apparatus according to the present invention. Any configuration and operation algorithm may be used as long as the configuration and the operation algorithm realize the above.

Further, in the second embodiment, a storage means for storing a one-dimensional data sequence and a first address for generating a first address for sequentially reading the one-dimensional data sequence stored in the storage means from the head. Address generating means, a second address generating means for generating a second address for sequentially reading the one-dimensional data series stored in the storage means from the end, and sequentially read from the storage means by the first address. Encoding means for encoding the one-dimensional data sequence, encoding means for encoding the one-dimensional data sequence sequentially read from the storage means by the second address, and a code sequence generated from the first encoding means. Quick connection means for concatenating a code string generated from the second encoding means into one code string, storage means, first address generation means, and second address And a control unit for controlling the forward encoding unit and the backward encoding unit, and any configuration and operation algorithm that realizes the operation of the encoding device according to the present invention. I do not care.

Further, in the above description, two-dimensional Huffman coding is taken as an example of coding, but if two-dimensional entropy coding of a one-dimensional data sequence is performed using a significant coefficient and the number of consecutive insignificant coefficients, the coding is performed. Does not matter.

In the above description, the one-dimensional data series shown in FIG. 6 is taken as an example, but it is apparent that the contents and the number of coefficients are not limited to this.

[0043]

According to the encoding device described in claim 1 of the present invention, it is possible to detect the final significant coefficient of a one-dimensional data sequence simultaneously with the encoding from the beginning of the one-dimensional data sequence,
Since the encoding can be completed at the last significant coefficient of the one-dimensional data sequence, the time required for encoding after the last significant coefficient can be reduced, and the encoding speed can be improved.

Further, the encoding device described in claim 2 improves the encoding speed while the generated code is completely compatible with the encoding device that encodes the one-dimensional data sequence only from the beginning. Can be planned.

[Brief description of the drawings]

FIG. 1 is a diagram showing a processing flow of a JPEG algorithm at the time of image compression.

FIG. 2 is a diagram showing an encoding flow of a JPEG algorithm during image compression.

FIGS. 3A and 3B are diagrams showing blocks before and after applying DCT. FIGS.

FIG. 4 is a diagram showing the order of zigzag scanning in the JPEG algorithm during image compression.

FIG. 5 is an embodiment of an encoding device according to claim 1 of the present invention.

FIG. 6A is a diagram showing an example of a one-dimensional data series stored in a storage device 41 in the embodiment of FIG. 5,
FIG. 6B is a diagram illustrating a state before zigzag scanning of an example of a one-dimensional data sequence stored in the storage device 41 in the embodiment of FIG.

FIG. 7 is a first part of a diagram showing a processing flow in the embodiment of FIG. 5;

FIG. 8 is a second part of a diagram showing a processing flow in the embodiment of FIG. 5;

FIG. 9 shows an embodiment of an encoding device according to claim 2 of the present invention.

FIG. 10 is a diagram for explaining backward encoding in the backward encoder 75 in the embodiment of FIG. 9;

FIG. 11 is a diagram illustrating an example of a two-dimensional encoding table.

FIG. 12 is a first part of a diagram showing a processing flow in the embodiment of FIG. 9;

FIG. 13 is a second part of a diagram illustrating a processing flow in the embodiment of FIG. 9;

[Explanation of symbols]

11 to 15... Each step in the processing flow in FIG.
201 to 215 each step in the encoding flow in FIG. 2, 41 storage, 42 counter, 43 counter, 44 encoder, 45 determiner, 46 controller 6,
01 to 617 and 621 to 627... Each step in the processing flow in FIGS. 7 and 8, 71... Memory, 72... Counter 73, counter 74, forward encoder, 75.
Reverse coder, 76 ... connector, 77 ... controller, 101
To 117 and 121 to 142... Each step in the processing flow in FIGS.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 1/41-1/419 H03M 7/30 H04N 7/30

Claims (2)

(57) [Claims] 1. An encoding apparatus for two-dimensionally entropy-encoding a one-dimensional data sequence composed of N (N is a natural number) coefficients using a value of a significant coefficient and the number of consecutive insignificant coefficients, Storage means for storing a series, first address generation means for generating a first address for sequentially reading the one-dimensional data series stored in the storage means from the beginning, and storage in the storage means Second address generating means for generating a second address for sequentially reading the one-dimensional data series from the end, and encoding for coding the one-dimensional data series sequentially read from the storage means by the first address Means for determining whether each coefficient of the one-dimensional data sequence sequentially read from the storage means by the second address is a significant coefficient or a meaningless coefficient. Determination means, and control means for controlling the storage means, the first address generation means, the second address generation means, the encoding means and the determination means, wherein the control means is The determination means is operated simultaneously, and when the determination means first detects a significant coefficient, the operations of the second address generation means and the determination means are stopped, and then the first address is equal to the second address. An encoding device, wherein the operation of the first address generating means and the encoding means is stopped and the encoding of the one-dimensional data sequence is terminated. 2. An encoding apparatus for two-dimensional entropy-encoding a one-dimensional data sequence composed of N (N is a natural number) coefficients using a value of a significant coefficient and the number of continuous insignificant coefficients, Storage means for storing a series, first address generation means for generating a first address for sequentially reading the one-dimensional data series stored in the storage means from the beginning, and storage in the storage means Second address generating means for generating a second address for sequentially reading the one-dimensional data series from the end, and a first code for coding the one-dimensional data series read from the storage means by the first address Encoding means; second encoding means for encoding a one-dimensional data sequence read from the storage means by the second address; and first encoding means. Concatenating means for concatenating a code string generated from the above and a code string generated from the second encoding means into one code string; the storage means, the first address generating means, Control means for controlling the second address generation means, the first encoding means, the second address generation means and the connection means, wherein the control means comprises the first encoding means and the second code The second address generation means is stopped when the second address reaches a predetermined value, and then the first address generation is performed when the first address becomes equal to the second address. Means, the operation of said first encoding means and said second encoding means is stopped, and the encoding of said one-dimensional data sequence is terminated.