JP2684887B2 - Encoding / decoding device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a coding / decoding device in a facsimile machine, and more particularly to a table reference system in a coding / decoding process.

[0002]

2. Description of the Related Art In a facsimile machine, data compression is performed in order to compress the amount of information to be transmitted and shorten the transmission time.
This is called extension.

As a compression encoding method, CCITT Recommendation T. G3 facsimile encoding method, Recommendation T.4. 6 standardizes the G4 facsimile encoding method. G3
Defines the MH method, which is a one-dimensional coding method, and the MR method, which is a two-dimensional sequential coding method. 2 for G4 facsimile
It defines the MMR method which is a dimensional sequential encoding method.

In accordance with these methods, compression processing (encoding processing) for converting image data into codes and decompression processing (decoding processing) for converting code data into image data are realized by dedicated hardware or software. .

Generally, the MM, which has a high compression ratio, is used.
The R method is realized by hardware because the transmission time is short and high speed compression and decompression processing is required.
The MH method, which has a lower compression rate than the MMR method, tends to be realized by software because it has a relatively long transmission time and does not require high speed.

A conventional example of compression processing and decompression processing using the MH system in a facsimile machine will be described below.

At the time of encoding processing, encoding is performed by the run length counting means for obtaining the run length value which is the length of consecutive pixels of white or black color from the pixel data.

In the MH system, the code is either a make-up code as shown in Table 1 or a termination code as shown in Table 2 depending on the run length which is the length of consecutive pixels of white or black color. The system code is used. This is a system in which the run length is divided by 64 and represented by a quotient and a remainder. The quotient corresponds to a make-up code, and the remainder corresponds to a termination code. Therefore, when the quotient is M and the remainder is T, the run length RL can be represented by RL = 64 × M + T, the termination code corresponds to the run length from 0 to 63, and the makeup code is 6
It is an integer multiple of 4 and corresponds to a maximum run length of 2560. Further, the code code is divided into one that expresses “white” and one that expresses “black”.

By the way, when performing encoding for each line,
The promise is to always give the white code as the first code. That is, the color of the code referenced at the beginning of the line is
It is decided to be "white". Therefore, when starting from a "black" pixel, the white code of run length 0 is transmitted first.

[0010]

[Table 1]

[0011]

[Table 2] FIG. 6 is a block diagram showing a main part of an example of a conventional coding / decoding apparatus that performs compression processing and decompression processing in a facsimile apparatus. CPU (Central Processing Unit) 1 which performs arithmetic processing, data processing, control processing of each part, and the like
00, and an image data memory 300 for storing a binary image data (image data) of the original read at the time of transmission,
A code data memory 400 for storing parallel data of received data at the time of reception, an encoding table 201 shown in Table 3 for converting image data into code data, and a table for converting code data into image data. Table ROM in which the decoding table 202 shown in FIG.
200 is connected to a FIFO memory 500 in which code data or image data obtained as a result of conversion is FIFO (first-infer-out) managed.

In the table ROM 200, information on a code to be obtained in advance by the encoding method described later based on the image data of the original to be transmitted and image data to be obtained by the decoding method described later according to the type of the received code are stored. The information for obtaining information is stored.

[0013]

[Table 3]

[0014]

[Table 4] First, the compression process will be described with reference to FIGS. 7, 8A, 8B and 8C, and 9A and 9B.

First, a document is read by a scanner or the like. Convert the read data into binary image data (image data),
It is stored in the image data memory 300.

Thereafter, the processing as shown in the flow chart of the encoding processing shown in FIG. 7 is performed, and the processing is as follows.

First, the CPU 100 reads the image data from the image data memory 300 and obtains the run length RL (step S11).

Next, the CPU 100 determines the run length RL.
8A, a bit AD7 indicating whether the image data is white or black, and a bit A indicating whether the makeup code or the termination code is generated, as shown in FIG.
D8, a bit field AD9 representing the quotient of the run length RL divided by 64 for a make-up code, a remainder obtained by dividing the run length RL by 64 for a termination code, and "0" for the least significant bit. Generate the value to configure. Then, the base address of the encoding table 201 is added to this value to generate the address ADR3 (step S12).

Next, the CPU 100 uses the table ROM 2
Code information data D in the area indicated by the address ADR3 of 00
Reference is made to T3 (step S13).

Then, code data is generated based on the information of the referred data DT3, and is sequentially stored in the FIFO memory 500.

Next, address A in step S12 of FIG.
Generation of DR3 will be described with reference to FIGS. 8B and 8C.

When a make-up code is generated, "1" indicating that it is a make-up code is set in bit 8 as shown in FIG. 8 (b).

Then, the quotient obtained by dividing the run length RL by 64 is set in bit 2 to bit 7. That is, the bits 6 to 11 of the run length RL expressed by a binary number are set. This is CCITT Recommendation T. In the case of 4, the maximum run length of 2560 is required. Therefore, since bits 12 to 15 of the run length RL are always "0000", 6 bits can be used for expression.

Furthermore, if the target image data is white, "0" is set in bit 1, and if it is black, "1" is set. Then, with bit 0 set to "0", the base address of the encoding table 201 in the table ROM 200 is added to the value set and generated as described above, and this is made the address ADR3.

When a termination code is generated, bit 0 is set to "0" indicating the termination code, as shown in FIG. 8 (c). Then, the remainder obtained by dividing the run length RL by 64 is bit 2
Set to bit 7. That is, bit 0 to bit 5 of the run length RL represented by a binary number are set. This has a maximum termination code of 6
Since up to 3 run lengths RL are supported, 6 bits can be used for expression.

Furthermore, if bit 1 is white, the bit 1 is set to "0", and if black, it is set to "1". Then, with bit 0 set to "0", the base address of the encoding table 201 in the table ROM 200 is added to the value set and generated as described above, and this is made the address ADR3.

Next, the data DT3 read in step S13 of FIG. 7 will be described.

Here, the table ROM 200 to be referred to
The code data information therein is one word, and as shown in FIGS. 9A and 9B, the code length is stored in the first byte and the code is stored in the second byte, right-justified in order from the least significant bit.

CCITT Recommendation T. The run-length code in 4 is always 0 for the 9th bit and above even if the code is 8 bits or above, so 1
As in the other cases, the code length is stored in the byte, and the code up to the 8th bit is stored in the second byte. When referring to this area of the table, "0" for the number of bits of the value obtained by subtracting 8 from the code length of the first byte is added to the code data of the second byte to form a code.

As an example, the image data is "00000000".
The encoding process in the case of "000000100111111 ..." will be described. The table base address for encoding is 0000H.

First, the CPU 100 operates the image data memory 3
When the number of consecutive pixels of the first white of the image data read out from 00 is counted, it is "14", so the run length RL
When expressed by a binary number of 16 bits, RL = 0000 0000 0000 1110 (step S11).

Next, the CPU 100 determines the run length RL.
Is 64 or less, only the termination code is generated. Therefore, since the pixel color is white, bit 8 is set to "0", bit 7 indicating the type of code is set to "0", bit 0 to bit 5 of run length RL is changed from bit 1 to bit 6, and bit 0 Set to "0" 0000 0000 0001 1100 (001C
H) is added with the encoding table base address (0000H) to generate 001CH + 0000H = 001CH as a table reference address (step S12).

Next, the CPU 100 uses the table ROM 2
The code information data of the area of address 001CH of 00 is referred to (step S13).

The data referred to is "060B" from Table 3.
Since it is “H”, the code length is “6” as represented by the upper 8 bits, and the code is 6 bits in order from the lower bit of “0BH = 0000 1011” represented by the lower 8 bits. , That is, “110100”.
This code "110100" is sent to the FIFO memory 500 (step S14).

After that, the black pixels of the following image data are coded, then the white pixels are coded, and so on.

Next, the decompression process will be described with reference to FIGS. 10 and 11 (a), (b) and (c).

First, serial code data received by a modem (not shown) is converted into parallel code data (code data) and stored in the code data memory 400.

After that, as shown in the flow of the decoding process shown in FIG.

First, the CPU 100 reads code data from the code data memory 400. Then, the number of consecutive "0" s from the beginning of the read code data is n, and the code (0 or 1) next to "1" detected after the consecutive "0" s is m, and "2 × n + m" The base address of the decoding table 202 is added to the value of “” to generate the address ADR4 (step S21).

Next, the data DT4 is referenced from the area indicated by the address ADR4 in the table ROM 200 (step S22).

Next, the CPU 100 executes this step S2.
It is determined whether the information of the data referred to immediately before the processing of No. 3 is the image data information to be finally obtained or the index data for generating the address of the table ROM 200 to be referred to next, in the eighth data. Judge by the bit value. For example, when the process of step S22 is shifted to the process of step S23, the data DT4 referred to in step S22 is set as the determination target, and when the process of step S23 described later is shifted to the process of step S23, step S28 is performed. The data DT6 referred to in step 1 is set as the determination target. As a result of the determination, if it is the final image data information, the process proceeds to step S25, and if not, the process proceeds to step S24 (step S23).

Next, the CPU 100 refers to the data D referred to.
Since T4 is index data, this data DT4
Address AD of the table to be referred to next based on the information of
R5 is generated (step S24).

Next, from the area in the table ROM 200 indicated by the address ADR5 generated in step S24,
Next, the data DT5 which is the index data for generating the address for referring to the next image data information is referred to (step S26).

Next, the CPU 100 generates the address ADR6 of the table ROM 200 to be referred to next based on the information of the data DT5 which is the index data referred to in step S26 (step S27).

Then, from the area of the table ROM 200 pointed to by the address ADR6 generated in step S27,
The image data information DT6 is referred to (step S28). Then, this image data information DT6 is newly added in step S23.
In step S23, the process proceeds to step S23 as the target data for determining that the image data information is the final image data information, and steps S23 to S28 are repeated until the final image data information is detected in step S23.

Then, in step S23, the image data is generated based on the data determined to be the final image data information, and is sequentially stored in the FIFO memory 500 (step S25).

Next, the data in the table ROM 200 referred to in steps S22, S26 and S28 of FIG. 10 will be described with reference to FIGS. 11 (a), 11 (b) and 11 (c).

The data referred from the decoding table 202 in the table ROM 200 is byte data, and the data shown in FIG.
As shown in (a), (b) and (c), bit 7 has a configuration for determining whether or not it is the final image data information. As shown in FIGS. 11A and 11B, when the bit 7 is “1”, it indicates the final data, and when it is “0” as shown in FIG. 11C, it is the index data. It is shown that.

When the data is image data information, as shown in FIGS. 11A and 11B, if bit 6 is "0", it is a termination code, and if it is "1", it is a make-up code. Indicates bit 0 to bit 5
In case of makeup, the run length RL of the corresponding image data is divided by 64, and in case of the termination code, the remainder is shown.

On the other hand, when the data is index data, as shown in FIG. 11 (c), the data of bits 0 to 6 are processed in steps S24 and S27 of FIG.
It is used as index data for the address generated in.

Next, the address generation method in steps S24 and S27 of FIG. 10 will be described.

In step S24, step S2
2 or the value of bits 0 to 7 of the index data having the format of FIG. 11C referenced in step S28 is added to the current address ADR4 of the table reference to generate the next address ADR5.

In step S27, step S2
The code corresponding to the value of bit 0 to bit 7 of the data having the format of FIG. 11 (c) referred to in FIG. .

As an example, code data “11010011”
The case of decoding "0111 ..." Will be described.
The white table base address for decryption is "020
0H ", black table base address is" 0300H "
And

First, "0" is counted from the beginning of the code data. In this case, since "0" does not exist, n = 0. Since the code next to the first detected "1" is "1", m = 1. Further, since the head of the code starts from white, the generated address is 2 × 0 + 1 + 0200H = 0201H (step S21).

Next, data "14" is read from the area indicated by the address "0201H" in the table ROM 200 shown in Table 4.
"H" is referred to (step S22).

Next, since the bit 8 of the referred data "14H" is "0", the CPU 100 determines that this data is index data (step S23).

The CPU 100 adds the data "14H" and the current table reference address "0201H". Therefore, 14H + 0201H = 0215H, which is the addition result, becomes the reference address of the next table ROM 200 (step S24).

Next, the area in the table ROM 200 indicated by the address "0215H" is referred to. The referenced data "02H" becomes index data for generating the next address (step S26).

Since the index data referred to by the CPU 100 is "02H", 1 is added to the code data "01" for the 2nd and 3rd bits of the 3rd and 4th bits next to m of the code data.
Addition is performed to obtain "10 = 2H". Then, this value is added to the current table reference address, that is, 2H + 0215H = 0217H is set as the next reference address (step S27).

The CPU 100 refers to the area of the address "0217H" of the table ROM 200 (step S).
28).

Since the referred data is "31H" and the bit 8 is "0", it is determined that this data is index data (step S23).

The CPU 100 adds the data "31H" and the current table reference address "0217H". Therefore, the addition result, 31H + 0217H = 0248H, becomes the reference address of the next table ROM 200 (step S24).

Next, the area in the table ROM 200 indicated by the address "0248H" is referred to. The referred data "01H" becomes index data for the next address generation (step S26).

Since the index data referred to by the CPU 100 is "01H", the first 1 of the code data
Adds 1 to the code data “0” which is the number of bits to obtain “1”
Get. Then, this value is added to the current table reference address, that is, 1 + 0248H = 0249H is set as the next reference address (step S27).

The CPU 100 refers to the area of the address "0249H" of the table ROM 200 (step S).
26).

Since the referred data is "45H" and the bit 8 is "0", it is determined that this data is index data (step S23).

The CPU 100 adds the data "45H" and the current table reference address "0249H". Therefore, the addition result of 45H + 0249H = 028EH becomes the reference address of the next table ROM 200 (step S24).

Next, the area in the table ROM 200 indicated by the address "028EH" is referred to. The referred data "01H" becomes index data for the next address generation (step S26).

Since the index data referred to by the CPU 100 is "01H", the first 1 of the code data
Adds 1 to the code data “0” which is the number of bits to obtain “1”
Get. Then, this value is added to the current table reference address, that is, 1 + 028EH = 028FH is set as the next reference address (step S27).

The CPU 100 refers to the area of the address "028F" of the table ROM 200 (step S2).
8).

Since the referred data is "8EH" and the bit 8 is "1", it is judged that this data is the finally obtained image data information (step S23).

Since the bit 7 of the data "8EH" determined to be the final image data information is "0", it can be seen that this code is a termination code. Then, since the lower 6 bits of the data become the run length RL, it can be seen that this image data has 14 consecutive white bits. Therefore, the CPU 100 sends "0000000000000000" to the FIFO memory 500 (step S25).

After that, the black image data may be similarly decoded with the seventh bit of the code data as the head, and then white, and so on.

In the example described here, the table ROM 20
Image data information could be obtained by referring to 0 seven times.

As described above, as a result of the determination in step S23 of FIG. 10, the process repeated when it is not the final data differs depending on the code length of the target code, and from the minimum of once from the nature of the decoding process. Up to 9 times.

[0077]

As described above,
In the conventional table citation method used in the encoding / decoding device of the facsimile apparatus, the number of table references in the encoding process is always fixed at once, but the number of table references in the decoding process depends on the code length. Since it is different, it is at least 1 to 9 times, and is not constant. That is, the processing time for reproducing the image data from the coded data becomes indefinite.

Thus, in synchronization with the final reading of the information of the image data as the decoding result from the table, the timing speed of the hardware relating to the decoding such as processing the information of the image data into the pixel format The drawback was that the design was difficult and complicated.

Further, in order to avoid such complexity, the timing design of the hardware is adjusted to the longest time, that is, in the conventional case, it is adjusted to the table reference time of 9 times at maximum, and the performance is improved. There were some drawbacks that didn't go up.

It is an object of the present invention to eliminate the above-mentioned drawbacks, thereby stabilizing the decoding process, simplifying the hardware design, and improving the performance of a facsimile apparatus having a table reference system. An object of the present invention is to provide a decoding / decoding device.

[0081]

According to the present invention, table storage means storing an encoding table and a decoding table, means for generating a reference address of the encoding table or the decoding table, and the generated reference. in coding and decoding apparatus of a facsimile apparatus and a processing means including means for encoding or decoding reads the code data corresponding to the address, the decoding table
Is the first area that stores the code length information, and the color information and
Type of code for Kupe-coding or terminate-coding
A second area that stores information and run length information
And the reference address of the decoding table is the number n of consecutive "0" s from the beginning of the coded data .
Area, a first bit field representing a value added with an address bias value , a second bit field indicating the color of the code data, and a third bit that is a predetermined number of bits of the code data. The processing means is configured to be generated based on an information word including a field, and the processing means obtains the number n of consecutive "0" s from the beginning of the code data at the time of decoding processing, and the counted "0". And a reference address generating means for generating the reference address of the decoding table by using the number of

[0082]

The reference address of the decoding table has a first bit field representing a value obtained by adding 1 to the number n of "0" s consecutive from the head of the code data.

That is, the number of bits of the remaining code data after "1" detected after consecutive "0" in one code data, that is, the number of bits of the remaining code code after the (n + 2) th bit is shown. This is information for determining the start position of the code data to be decoded next.

Therefore, the processing means refers to the decoding table only twice, when the run length RL is calculated from the image data information and when the data for the reference address obtained based on the run length RL is referred to. can do.

[0085]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the first embodiment of the present invention, FIG. 2 is a flow chart showing the decoding processing procedure, and FIG.
(A), (b) and (c) are diagrams showing the format of the reference address of the decoding table, and FIGS. 4 (a) and (b) are diagrams showing the data format of the decoding table. Table 5 shows an example of the decoding table 202a. The coding table 201 is the same as Table 3 shown in the conventional example.

According to FIG. 1, in the first embodiment, a table ROM 200a as a table storage means in which an encoding table 201 and a decoding table 202a are stored.
And an encoding table 201 and a decoding table 202
CPU 10 as processing means including means for generating the reference address of a and means for reading code data corresponding to the generated reference address to perform encoding and decoding.
0a, the image data memory 300, and the code data memory 4
00, a FIFO memory 500, and a bus 600, the reference address of the decoding table 202a, which is a feature of the present invention, is as shown in FIG.
As shown in (a) and (b), a first bit field (AD4) representing a value obtained by adding 1 to the number n of "0" s consecutive from the beginning of the code data and the color of the code data are shown. The CPU 1 is configured to be generated based on an information word including a second bit (AD5) and a third bit field (AD6) that is a predetermined number of bits of the code data.
Reference numeral 00a is a counting means for obtaining the number n of consecutive "0" s from the beginning of the code data during the decoding process, and an address generating means for generating a reference address of the decoding table 202a using the counted number of "0s". Includes and.

Next, the operation of the first embodiment will be described.

It is assumed that the table ROM 200a stores the decoding table 202a shown in Table 5 in advance.

[0090]

[Table 5] The encoding process of the first embodiment is the same as that of the above-mentioned conventional example.

Next, the decompression process will be described with reference to FIGS.
A description will be given with reference to (a), (b) and (c) and FIGS. 4 (a) and 4 (b).

First, similarly to the conventional example, serial code data received by a modem or the like is converted into parallel code data (code data) and stored in the code data memory 400 shown in FIG.

After that, as shown in the flow of the decoding process shown in FIG.

First, the CPU 100a reads code data from the code data memory 400. Then, the number of consecutive "0" s from the beginning of the read code data is n, the value obtained by adding 1 to this n is AD4, and the color of the code is AD.
5, the base address of the decoding table 202a is added to the value having the configuration shown in FIG. 3 where the code is AD6 to generate the address ADR2 (step S1).

Next, the data DT2 is referenced from the area designated by the address ADR2 in the table ROM 200a (step S2).

Next, the CPU 100a generates image data based on the information of the referred data DT2 and stores it in the FIFO memory 500 (step S3).

Further, the CPU 100a uses the value obtained by adding the base address of the decoding table 202a to the value of the referred data DT2 as the address, and the table ROM 200a.
See The referred data DT2-1 is the number of bits of the remaining code code after "1" detected after a continuous "0" in one code code, that is, the bits of the remaining code code after the (n + 2) th bit. The number indicates the number and serves as information for determining the start position of the code code to be decoded next (step S4).

Next, the address generating method in step S1 of FIG. 1 will be described.

First, as shown in FIG. 3B, consecutive "0" s are counted from the beginning of the code data, and the value is set to n. Then, as shown in FIG. 3C, the value obtained by adding 1 to this n is set in bits 8 to 11. Where MH
In the code code in the method, the maximum number of consecutive "0" s, that is, the value of n, is 7 from the beginning, and the maximum value is 8 when 1 is added.

If the target image data is white, "0" is set in bit 7, and if it is black, "1" is set, and "1" detected after "0" consecutive from bit 0 to bit 6 is detected. , The code for the 7th bit from the (n + 2) th is set to the right justification from the least significant bit.

An address ADR2 is generated by adding the base address of the decoding table 202a to the value thus set.

Next, regarding the data in the ROM 200a read in steps S2 and S4 of FIG.
A description will be given using (a) and (b).

The data DT2 referred to in step S2 is image data information. The data DT2 is referred to by byte data, and bit 7 is "0" as shown in FIG. 4 (a).
If it is, the target code is a white code, and if it is "1", it is black. If the bit 6 is "1", the target code is a make-up code, and if it is "0". If it is a termination code, if it is a make-up code from bit 0 to bit 5, the run length RL of the corresponding image data is divided by 64, and if it is a termination code, the remainder is shown. The base address of the decoding table 202a is added to the value to be taken to generate the address ADR2. Here, in the code code in the MH system, the run length RL can be represented by a maximum of 6 bits as described in the conventional example.

Data DT2-referenced in step S4
As shown in FIG. 4B, 1 stores a value obtained by subtracting the number n + 1 of consecutive "0" s from the code length of the code decoded in the processes of steps S1, S2 and S3.

As an example, the case of decoding coded data “110100110111 ...” Like the above-mentioned conventional example will be described. The base address of the decryption table 202a is “0200H”.

First, the CPU 100a reads a code from the code data memory 400, and continuously reads "0" from the beginning.
Is counted. In this case, since there is no "0", n = 0. The value obtained by adding 1 to this n is set in bit 8 to bit 11, and since the beginning of the code starts from white, bit 7
Is set to “0” and the code next to “1” that is first detected from bit 0 to bit 6, that is, the code for 7 bits from the n + 2nd code is set by LSB, “0000 0001 0110 0101 = 0165
H ”, and 0165H + 0200H = 0365H, which is the result of adding the base address of the decoding table 202a to this value, is the generated address (step S1).

Next, the data is referred to from Table 6 from the area designated by the address "0365H" in the table ROM 200a (step S2).

The data referred to is "0EH" and bit 7 is "0" to indicate that the color of the code is white. Since bit 6 is "0", the type of code is the termination code. I understand. Then, since the lower 6 bits of the data become the run length, it can be seen that this image data has 14 consecutive white bits. Therefore, the CPU 100a stores "00" in the FIFO memory 500.
"000000000000" is transmitted (step S
3).

Further, the CPU 100a refers to the table ROM 200a with the value 0EH + 0200H = 020EH obtained by adding the base address of the decoding table 202a to the referred data "0EH" as an address.
The referred data is "05H", and steps S1 and S
The code length of the code code decoded in 2 and S3 is a value obtained by adding the number n bits of "0" counted to this data value "05H" and one bit of "1" detected first, 0 + 1 + 05H = 06H (Step S4).

Thereafter, with the sixth code bit "1" from the code length "06H" of the decoded code code obtained in step S4 as the head, the black image data is similarly decoded, and the white is next. You can go to

As described above, the number of table references in the decoding process in the first embodiment is the same as the reference of the image data information in step S2 and step S4 in step S4.
1, twice with reference to the code length information of the code code processed in S2 and S3.

Next, a second embodiment of the present invention will be described.

The basic construction of the second embodiment is the same as that of the first embodiment shown in FIG.

The difference is that the maximum run length of 6 is added by adding the unique makeup code shown in Table 6.
It can handle up to 655. This code has a common code expressing "white" and a code expressing "black" as in the case of the makeup code in the case of run lengths 1792 to 2623.

[0115]

[Table 6] Next, the difference between the encoding process and the first embodiment will be described.

In the table ROM 200a, in addition to the data in the table ROM 200a of the first embodiment, predetermined data corresponding to an encoding system and a decoding system, which will be described later, corresponding to the extended code code is stored.

Similar to the first embodiment, the code processing of the second embodiment is performed in the processing order shown in FIG. 7 as in the conventional example. However, the generation of the reference address ADR3 of the table in step S12 of FIG. 7 in the second embodiment is as follows.

First, it is determined whether the run length RL of the image data to be encoded is 2624 or more. If the result of the determination is less than 2624, the address is generated as in the case of the conventional example. However, the base address of the table for encoding which is added in the conventional example is a code code corresponding to a run length of less than 2624 in the second embodiment, that is, a code code for generating the code code as shown in Table 1 of the conventional example. It is the base address of the table.

If the judgment result is 2624 or more,
For the termination code, the address ADR1 is generated as in the case of the conventional example, and when the makeup code is generated, it is as follows.

As in the first embodiment shown in FIGS. 4A and 4B, "0" is set in bit 8 if the target image data is white, and "1" is set in black. Then, bit 7 is set to "1" indicating that it is a make-up code. In bits 1 to 6, bits 6 to 11 of the run length RL represented by a binary number are set. This is the data of the lower 6 bits of the binary value of the value of the quotient obtained by dividing the run length RL by 64.
Then, bit 0 is set to "0".

Table 6 shows the values set as described above.
The base address of the table for generating the unique code code as shown in (1) is added to form the address ADR1.

Next, the contents of the decoding process will be described.

Also in the decoding processing of the second embodiment, the processing is performed in the processing order shown in FIG. 2 as described in the first embodiment. However, in step S of FIG. 2 in the second embodiment.
The data DT2 referred to from the table 2 is as follows.

When n, which is the number of consecutive "0" s counted in step S1 of FIG. 2, is 7 or less, as in the case of the first embodiment, as shown in FIG. 4 (a). It becomes data.

When n is 8 or more, as shown in FIG. 5, if bit 7 is "0", it indicates white, and if it is "1", it indicates black, and the run length RL from bit 0 to bit 6 is 64. It is configured to show the quotient divided by. This is because the unique code code as shown in Table 6 added in the second embodiment allows the run length to be up to 6655, so that a maximum of 7 bits is necessary to represent this, and the unique code This is because the code of is common to both white and black.

As described above, the number of table references in the decoding process is always two in the second embodiment as in the first embodiment.

[0127]

As described above, the present invention has the following effects. (1) When the table reference is used when performing the decoding process, the reference number of the table is always twice regardless of the type of code. This eliminates the need for a circuit for waiting such as when the information of the image data that is the decoding result is finally read from the table and processing the information of this image data into the pixel format. , The design of the hardware related to decoding becomes simpler than in the past.

(2) Since it is not necessary to judge whether the data read from the table is the information of the image data that can be finally obtained as compared with the conventional method, the decoding process for converting the code data into the image data is simpler. Be converted.

(3) In the present invention, it is possible to add not only the MH system code but also a unique code.

(4) In the decoding method of the present invention, the fixed time of the table reference count of 2 times is shorter than the conventional maximum 9 times of the table reference time. Therefore, the present invention has higher performance than the conventional one in comparison with the conventional hardware timing design which is adapted to the longest time. As a result, the MR method can be realized by software.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a flowchart showing the decoding processing procedure.

FIG. 3 is a diagram showing a format of a reference address of the decoding table.

FIG. 4 is a diagram showing a data format of the decoding table.

FIG. 5 is a diagram showing a data format of a decoding table according to the second embodiment of the present invention.

FIG. 6 is a block diagram showing a main part of a conventional example.

FIG. 7 is a flowchart showing the encoding processing procedure.

FIG. 8 is a diagram showing a format of a reference address of the encoding table.

FIG. 9 is a diagram showing a data format of the encoding table.

FIG. 10 is a flowchart showing the decoding processing procedure.

FIG. 11 is a diagram showing a data format of the decoding table.

[Explanation of symbols]

100, 100a CPU 200, 200a Table ROM 201 Encoding table 202, 202a Decoding table 300 Image data memory 400 Code data memory 500 FIFO memory 600 Bus S1 to S4, S11 to S14, S21 to S28 Steps

Claims (2)

(57) [Claims] 1. A table storage unit that stores an encoding table and a decoding table, a unit that generates a reference address of the encoding table or the decoding table, and read code data corresponding to the generated reference address. In a coding / decoding apparatus for a facsimile apparatus, comprising: a processing unit including a unit for performing coding or decoding according to the first embodiment, the decoding table includes a first area storing code length information.
Gamut and color information, make-up coding or termination
The code type information and the run length information of the encoding are
The reference address of the decoding table is composed of the stored second area, and the second area is indicated by the number n of “0” consecutive from the beginning of the code data.
Information including a first bit field indicating a value obtained by adding an address bias value for the above, a second bit field indicating the color of the code data, and a third bit field that is a predetermined number of bits of the code data. The processing means is configured to be generated based on words, and the processing means uses a counting means for obtaining the number n of consecutive "0" s from the beginning of the code data at the time of decoding processing and the counted number of "0s". A coding / decoding device, comprising: a reference address generation unit that generates a reference address of the decoding table. 2. A means for generating a reference address of the encoding table or the decoding table and a means for reading code data corresponding to the generated reference address to perform encoding or decoding are arithmetic processing means of a facsimile apparatus. The encoding / decoding device according to claim 1, which is included in.