JPH0897358A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0897358A JPH0897358A JP23553394A JP23553394A JPH0897358A JP H0897358 A JPH0897358 A JP H0897358A JP 23553394 A JP23553394 A JP 23553394A JP 23553394 A JP23553394 A JP 23553394A JP H0897358 A JPH0897358 A JP H0897358A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor element
- semiconductor
- lead
- lead terminals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、リードフレーム上に搭
載される半導体素子を樹脂封止することでパッケージ化
し、パッケージより複数のリード端子が導出される半導
体装置に関する。近年、半導体装置においては高集積化
が進んでいるが、パッケージの大型化を招くことなく集
積度を上げることが要求されている。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor element mounted on a lead frame is packaged by resin sealing and a plurality of lead terminals are led out from the package. In recent years, semiconductor devices have been highly integrated, but it is required to increase the degree of integration without increasing the size of the package.
【０００２】[0002]
【従来の技術】図７は、従来の半導体装置を説明するた
めの断面図である。従来の半導体装置は、図７に示すよ
うに、リードフレームのステージ２３上に搭載される半
導体素子２２の複数の電極部とリード端子２４とがワイ
ヤーボンディングによって接続され、ワイヤーボンディ
ング部を含んで半導体素子２２が樹脂封止されてパッケ
ージ２５を形成する構成となっている。2. Description of the Related Art FIG. 7 is a sectional view for explaining a conventional semiconductor device. In a conventional semiconductor device, as shown in FIG. 7, a plurality of electrode portions of a semiconductor element 22 mounted on a stage 23 of a lead frame and lead terminals 24 are connected by wire bonding, and a semiconductor including a wire bonding portion is provided. The element 22 is resin-sealed to form the package 25.
【０００３】通常、半導体素子２２は立方体をしてお
り、図示しないが表面の周囲に電極部が形成されてい
る。この電極部とリード端子２４の端部とをワイヤーボ
ンディングすることで電気的に接続した後、モールド金
型を使用して半導体素子２２の樹脂封止を行うことでパ
ッケージ化している。樹脂封止後、リードフレームの切
断及びリード端子２４の曲げ加工を行うことで、図７に
示す半導体装置を完成させる。Usually, the semiconductor element 22 has a cubic shape, and an electrode portion is formed around the surface, which is not shown. The electrode portion and the end portion of the lead terminal 24 are electrically connected by wire bonding, and then the semiconductor element 22 is sealed with resin using a molding die to form a package. After the resin sealing, the lead frame is cut and the lead terminals 24 are bent to complete the semiconductor device shown in FIG.
【０００４】[0004]
【発明が解決しようとする課題】以上説明したような従
来の半導体装置は、リードフレームのステージ上に１個
の半導体素子を搭載して樹脂封止するため、半導体装置
の集積度は半導体素子の容量で決定される。そのため、
高集積の半導体装置を得るに大型の半導体素子が必要で
あり、パッケージ化した後の半導体装置も大型となり、
半導体装置の実装面積が広くなる。In the conventional semiconductor device as described above, one semiconductor element is mounted on the stage of the lead frame and resin-sealed, so that the degree of integration of the semiconductor device depends on the semiconductor element. Determined by capacity. for that reason,
A large semiconductor element is required to obtain a highly integrated semiconductor device, and the semiconductor device after packaging also becomes large,
The mounting area of the semiconductor device is increased.
【０００５】また、小型の半導体装置の場合、集積度を
上げるには複数の半導体装置の実装が必要でその実装面
積はやはり広いものとなる。本発明は、上記課題を解決
して、パッケージの大型化、即ち広い実装面積を必要と
することなく集積度を上げることを目的としている。Further, in the case of a small semiconductor device, it is necessary to mount a plurality of semiconductor devices in order to increase the degree of integration, and the mounting area is still large. An object of the present invention is to solve the above-mentioned problems and to increase the degree of integration without increasing the size of the package, that is, requiring a large mounting area.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
の本発明は、半導体素子（１）が樹脂（６）により封止
され、該半導体素子（１）の電極部と電気的に接続され
る複数のリード端子（５）が前記樹脂（６）より導出さ
れて外部との接触部をなしている半導体装置において、
前記半導体装素子（１）が前記リード端子（５）上に複
数個立設された状態で樹脂封止されていることを特徴と
している。According to the present invention for solving the above problems, a semiconductor element (1) is sealed with a resin (6) and electrically connected to an electrode portion of the semiconductor element (1). In a semiconductor device in which a plurality of lead terminals (5) are connected to the outside by being led out from the resin (6),
It is characterized in that a plurality of the semiconductor device (1) are erected on the lead terminals (5) and resin-sealed.
【０００７】[0007]
【作用】上記本発明の半導体装置によれば、複数の半導
体素子（１）をリード端子（５）上に立設した状態で樹
脂封止するため、高さは高くなるものの実装面積を広く
することなく、集積度を上げることができる。According to the above semiconductor device of the present invention, the plurality of semiconductor elements (1) are resin-sealed in a state of standing on the lead terminals (5), so that the height is increased but the mounting area is increased. Without increasing the degree of integration.
【０００８】[0008]
【実施例】以下に本発明の実施例を図面を参照しながら
詳細に説明する。図１は本発明の第１実施例を説明する
ための図であり、図１（ａ）は半導体装置断面図、図１
（ｂ）は半導体装置の部分斜視図である。本実施例の半
導体装置は、図１（ａ）に示すように、半導体素子１が
搭載される絶縁性プレート２がリード端子５上に複数個
立設されており、これを樹脂封止することによって、パ
ッケージ６を形成している。絶縁性プレート（２）は例
えばガラスエポキシによって構成されている。Embodiments of the present invention will be described in detail below with reference to the drawings. 1A and 1B are views for explaining a first embodiment of the present invention, and FIG. 1A is a sectional view of a semiconductor device, FIG.
FIG. 3B is a partial perspective view of the semiconductor device. In the semiconductor device of this embodiment, as shown in FIG. 1A, a plurality of insulating plates 2 on which the semiconductor element 1 is mounted are erected on the lead terminals 5, and these are sealed with resin. To form the package 6. The insulating plate (2) is made of glass epoxy, for example.
【０００９】半導体素子１は、図１（ａ）の部分拡大斜
視図である図１（ｂ）に示すように、プレート２表面に
絶縁性接着剤等を介して搭載されており、半導体素子１
の図示せぬ電極はプレート２の端部に備えられる接触端
子３と金線よりなるワイヤー４によって電気的に接続さ
れている。半導体素子１の電極と接続される接触端子３
は、Ｌ字状に形成されており、その下面が導電性接着剤
によってリード端子５に接続されることで、プレート２
がリード端子５上に立設した状態となる。As shown in FIG. 1B, which is a partially enlarged perspective view of FIG. 1A, the semiconductor element 1 is mounted on the surface of the plate 2 via an insulating adhesive or the like.
The electrode (not shown) is electrically connected to the contact terminal 3 provided at the end of the plate 2 by the wire 4 made of a gold wire. Contact terminals 3 connected to the electrodes of the semiconductor element 1
Is formed in an L shape, and the lower surface thereof is connected to the lead terminal 5 by a conductive adhesive, so that the plate 2
Is erected on the lead terminal 5.
【００１０】図２及び図３は、本発明の第１実施例にお
ける半導体装置の製造工程を説明するための斜視図及び
断面図である。本実施例で使用するリードフレーム７
は、図２に示すように一端が連結された複数のリード端
子５が両側より中央に向かって延出しており、このリー
ドフレーム７のリード端子５上に半導体素子１が搭載さ
れたプレート２を固定する。2 and 3 are a perspective view and a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the first embodiment of the present invention. Lead frame 7 used in this embodiment
As shown in FIG. 2, a plurality of lead terminals 5 having one end connected to each other extend from both sides toward the center, and the plate 2 on which the semiconductor element 1 is mounted is mounted on the lead terminals 5 of the lead frame 7. Fix it.
【００１１】プレート２に設けられたＬ字状の接触端子
３下面に、予め導電性の接着剤を塗布しておき、これを
矢印で示すようにリード端子５上に接着させる。より固
着力を強める場合には接触端子３だけでなく、プレート
２の下面に絶縁性の接着剤を塗布しておき、これをリー
ド端子５に接着することもできる。リードフレーム７に
おける全てのリード端子５に対してプレート２を接着し
た後、樹脂封止工程を行う。A conductive adhesive is applied to the lower surface of the L-shaped contact terminal 3 provided on the plate 2 in advance, and the conductive adhesive is adhered onto the lead terminal 5 as indicated by an arrow. In order to further increase the fixing force, not only the contact terminals 3 but also the lower surface of the plate 2 may be coated with an insulating adhesive, and this may be bonded to the lead terminals 5. After adhering the plate 2 to all the lead terminals 5 in the lead frame 7, a resin sealing step is performed.
【００１２】図３は樹脂封止工程を説明するための断面
図であり、それぞれキャビティ１０ａ，１０ｂを有する
上型８と下型９との間にリードフレーム７を挟持してい
る状態を示している。プレート２を接着した面が下にな
るように、リードフレーム７を上型８と下型９との間に
挟持する。上型８及び下型９にはそれぞれキャビティ１
０ａ，１０ｂが形成されており、プレート２は下型９の
キャビティ１０ｂ内に位置する。FIG. 3 is a sectional view for explaining the resin sealing process, showing a state in which the lead frame 7 is sandwiched between an upper mold 8 and a lower mold 9 having cavities 10a and 10b, respectively. There is. The lead frame 7 is sandwiched between the upper mold 8 and the lower mold 9 so that the surface to which the plate 2 is bonded faces downward. The upper mold 8 and the lower mold 9 each have a cavity 1
0a and 10b are formed, and the plate 2 is located in the cavity 10b of the lower mold 9.
【００１３】下型９には外部からキャビティに通ずるゲ
ートが形成されており、図３の状態においてゲート１１
に溶融する樹脂を注入して、キャビティ１０ａ，１０ｂ
内に樹脂を充填する。樹脂は半導体素子を搭載するプレ
ート２を封止する。樹脂が冷却固化して図１（ａ）に示
すパッケージが形成された後、上型８及び下型９を開い
てリードフレーム７を取り出す。そして、リードフレー
ム７の所定部、即ち複数のリード端子５の連結部を切断
すると共にリード端子５を所定形状に曲げ加工すること
によって、半導体装置を完成させる。The lower mold 9 is formed with a gate leading from the outside to the cavity. In the state shown in FIG. 3, the gate 11 is formed.
The molten resin is injected into the cavities 10a, 10b
Fill the inside with resin. The resin seals the plate 2 on which the semiconductor element is mounted. After the resin is cooled and solidified to form the package shown in FIG. 1A, the upper die 8 and the lower die 9 are opened and the lead frame 7 is taken out. Then, the semiconductor device is completed by cutting a predetermined portion of the lead frame 7, that is, a connecting portion of the plurality of lead terminals 5 and bending the lead terminal 5 into a predetermined shape.
【００１４】尚、本実施例においては、同一の半導体素
子で同一要素の電極部をそれぞれ同一のリード端子５に
接続しているが、異なる半導体素子を複数個リード端子
５上に立設する場合には、同一のリード端子上には接続
できない。この場合、図４に半導体素子を省略した上面
図を示すが、各々のプレート２’の接触端子３’の位置
をずらして設けて、それぞれリード端子５’に交互に接
続するよう構成する。In this embodiment, the electrode parts of the same element are connected to the same lead terminal 5 in the same semiconductor element, but when a plurality of different semiconductor elements are erected on the lead terminal 5. Cannot be connected on the same lead terminal. In this case, although a top view in which the semiconductor element is omitted is shown in FIG. 4, the contact terminals 3 ′ of the respective plates 2 ′ are provided so as to be displaced so as to be alternately connected to the lead terminals 5 ′.
【００１５】また、本実施例では図１（ａ）に示すよう
に、プレート２の両面に対向する電極が同一要素になる
ような半導体素子をそれぞれ搭載することによって、よ
り集積度を高めている。以上説明した本実施例によれ
ば、両面に半導体素子１を搭載する４枚のプレート２を
リードフレーム７のリード端子５上に立設した状態で、
樹脂封止して半導体装置を構成しており、リードフレー
ムのステージ上に寝かせた状態で１個の半導体素子を搭
載する従来の半導体装置に比べて上方向に高くなるもの
の、実装面積に対する集積度は極めて高くなる。Further, in this embodiment, as shown in FIG. 1 (a), semiconductor elements are mounted on both surfaces of the plate 2 so that the electrodes facing each other are the same element, so that the degree of integration is further enhanced. . According to the present embodiment described above, in a state in which the four plates 2 having the semiconductor elements 1 mounted on both sides are erected on the lead terminals 5 of the lead frame 7,
The semiconductor device is encapsulated with resin, and it is higher than the conventional semiconductor device in which one semiconductor element is mounted on the stage of the lead frame in a lying state, but the degree of integration with respect to the mounting area is higher. Will be extremely high.
【００１６】図５は、本発明の第２実施例を説明するた
めの図であり、図５（ａ）は半導体装置断面図、図５
（ｂ）は半導体装置の部分斜視図である。図５（ａ）
（ｂ）に示すように、本実施例における半導体素子１２
は、その電極部に電極パッド１３を有するものであり、
この半導体素子１２を直接リード端子１４に立設してい
る。FIG. 5 is a diagram for explaining a second embodiment of the present invention. FIG. 5A is a sectional view of a semiconductor device, and FIG.
FIG. 3B is a partial perspective view of the semiconductor device. FIG. 5 (a)
As shown in (b), the semiconductor element 12 according to the present embodiment.
Has an electrode pad 13 on its electrode portion,
The semiconductor element 12 is erected directly on the lead terminal 14.
【００１７】半導体素子１２は、図示しないが第１実施
例同様複数のリード端子１４が連結されたリードフレー
ム上に固定される。リード端子１４の表面には複数の突
出部１５がエッチング加工によって一体形成されてお
り、半導体素子１２をリード端子１４上に立設した状態
で、半導体素子１２の電極パッド１３と突出部１５とが
接触する。Although not shown, the semiconductor element 12 is fixed on a lead frame to which a plurality of lead terminals 14 are connected as in the first embodiment. A plurality of protrusions 15 are integrally formed on the surface of the lead terminal 14 by etching. When the semiconductor element 12 is erected on the lead terminal 14, the electrode pad 13 of the semiconductor element 12 and the protrusion 15 are formed. Contact.
【００１８】半導体素子１２は、その下面を絶縁性の接
着剤によりリード端子１４上に固定されており、半導体
素子１２の電極パッド１３とリード端子１４の突出部１
５とは直接接触、或いは導電性接着剤を介して電気的に
接続されている。勿論導電性接着剤を使用すれば、半導
体素子１２のリード端子１４に対する固着力は強くな
る。The lower surface of the semiconductor element 12 is fixed on the lead terminals 14 by an insulating adhesive, and the electrode pads 13 of the semiconductor element 12 and the protruding portions 1 of the lead terminals 14 are fixed.
5 is directly contacted or electrically connected via a conductive adhesive. Of course, if a conductive adhesive is used, the fixing force of the semiconductor element 12 to the lead terminals 14 becomes stronger.
【００１９】リード端子１４上に半導体素子１２を直接
立設した状態で、第１実施例同様樹脂封止を行うことに
より、パッケージ１６を形成し、更にリードフレームに
おけるリード端子連結部の切断及びリード端子１４の曲
げ加工をおこなって半導体装置を完成させる。半導体素
子１をプレート２表面に搭載し、このプレート２をリー
ド端子５上に立設する第１実施例に対して、本第２実施
例は、電極パッド１３を有する半導体素子１２をリード
端子１４上に直接立設させるため、半導体素子のプレー
トへの搭載工程及びワイヤーボンディング工程が不要と
なり、製造工程を簡略化することができる。With the semiconductor element 12 standing upright on the lead terminals 14, the package 16 is formed by resin sealing as in the first embodiment, and further, the lead terminal connecting portion in the lead frame is cut and leads are formed. The semiconductor device is completed by bending the terminal 14. In contrast to the first embodiment in which the semiconductor element 1 is mounted on the surface of the plate 2 and the plate 2 is erected on the lead terminal 5, in the second embodiment, the semiconductor element 12 having the electrode pad 13 is connected to the lead terminal 14. Since the semiconductor element is directly erected on the plate, the step of mounting the semiconductor element on the plate and the step of wire bonding are unnecessary, and the manufacturing process can be simplified.
【００２０】尚、本実施例では、半導体素子１２の電極
パッド１３を一方の面のみに形成して、リード端子１４
の突出部１５と接触させているが、電極パッド１３を半
導体素子１２の両面に設けると共に、リード端子１４の
突出部１５を電極パッド１３に対応させるべく半導体素
子１２を挟むように設けることにより、その固着力をよ
り強固なものにすることも可能である。In this embodiment, the electrode pad 13 of the semiconductor element 12 is formed on only one surface, and the lead terminal 14 is formed.
Although the electrode pads 13 are provided on both surfaces of the semiconductor element 12 and the protrusions 15 of the lead terminals 14 are provided so as to sandwich the semiconductor element 12 so as to correspond to the electrode pads 13, It is also possible to make the fixing force stronger.
【００２１】図６は、本発明の第３実施例を説明するた
めの図であり、図６（ａ）は半導体装置断面図、図６
（ｂ）は半導体装置の部分斜視図である。本第３実施例
も、第２実施例と同様、電極パッドを有する半導体素子
を直接リード端子上に立設するものである。本実施例の
半導体素子１７は第２実施例同様電極パッド１８を有し
ており、これを直接リード端子１９上に立設する。リー
ド端子１９は半導体素子１７に対応する部分に凹部２０
が形成されており、この凹部２０内に半導体素子１７を
嵌合させる。FIG. 6 is a diagram for explaining a third embodiment of the present invention, and FIG. 6A is a sectional view of a semiconductor device, and FIG.
FIG. 3B is a partial perspective view of the semiconductor device. In the third embodiment, as in the second embodiment, the semiconductor element having the electrode pad is directly erected on the lead terminal. The semiconductor element 17 of the present embodiment has the electrode pad 18 as in the second embodiment, which is erected directly on the lead terminal 19. The lead terminal 19 has a recess 20 in a portion corresponding to the semiconductor element 17.
Is formed, and the semiconductor element 17 is fitted into the recess 20.
【００２２】リード端子１９は、図示しないが第１実施
例と同じく複数が連結されてリードフレームを成した状
態にされている。凹部２０は電極パッド１８を有する部
分の半導体素子１７の厚さとほぼ同様な幅で形成されて
おり、凹部２０の底面と半導体素子１７の下面とを絶縁
性接着剤を介して接着することで固定する。Although not shown, a plurality of lead terminals 19 are connected to each other to form a lead frame as in the first embodiment. The recess 20 is formed with a width substantially similar to the thickness of the semiconductor element 17 in the portion having the electrode pad 18, and is fixed by bonding the bottom surface of the recess 20 and the lower surface of the semiconductor element 17 with an insulating adhesive. To do.
【００２３】このように、リードフレームのリード端子
１９上に半導体素子１７を直接立設した状態で、第１実
施例同様樹脂封止を行うことにより、パッケージ２１を
形成し、更にリードフレームにおけるリード端子連結部
を切断すると共に、リード端子１９の曲げ加工を行って
半導体装置を完成させる。本実施例では直接半導体素子
１７をリード端子１９上に立設しているため、やはり第
１実施例の如く半導体素子１のプレート２への搭載工程
及びワイヤーボンディング工程が不要となる。As described above, the semiconductor device 17 is directly erected on the lead terminals 19 of the lead frame, and the package 21 is formed by resin sealing as in the first embodiment, and the leads of the lead frame are further formed. The semiconductor device is completed by cutting the terminal connecting portion and bending the lead terminal 19. In this embodiment, since the semiconductor element 17 is directly erected on the lead terminal 19, the step of mounting the semiconductor element 1 on the plate 2 and the wire bonding step as in the first embodiment are unnecessary.
【００２４】更に本実施例のリード端子１９は、その一
部に半導体素子１７を立設するための凹部２０を設けれ
ばよいため、エッチング加工は勿論、プレス加工によっ
ても容易に形成することができる。Further, since the lead terminal 19 of this embodiment may be provided with the recess 20 for standing the semiconductor element 17 in a part thereof, it can be easily formed not only by etching but also by pressing. it can.
【００２５】[0025]
【効果】以上説明した本発明の半導体装置によれば、複
数の半導体素子をリードフレーム上に立設した状態で樹
脂封止しているため、実装面積に対する集積度を高める
ことができ、高集積化が叫ばれる半導体分野において極
めて有効である。According to the semiconductor device of the present invention described above, a plurality of semiconductor elements are resin-sealed in a state of being erected on the lead frame, so that the degree of integration with respect to the mounting area can be increased, and high integration can be achieved. It is extremely effective in the semiconductor field, which is called for.
【図１】本発明の第１実施例を説明する半導体装置断面
図及び部分斜視図である。FIG. 1 is a sectional view and a partial perspective view of a semiconductor device illustrating a first embodiment of the present invention.
【図２】本発明の第１実施例における半導体装置の製造
工程を説明するためのリードフレーム斜視図である。FIG. 2 is a perspective view of a lead frame for explaining a manufacturing process of the semiconductor device according to the first exemplary embodiment of the present invention.
【図３】本発明の第１実施例における半導体装置の樹脂
封止工程を説明するための金型断面図である。FIG. 3 is a cross-sectional view of a mold for explaining a resin sealing process of the semiconductor device according to the first embodiment of the present invention.
【図４】異なる半導体素子を搭載する場合の半導体装置
の部分上面図である。FIG. 4 is a partial top view of a semiconductor device in which different semiconductor elements are mounted.
【図５】本発明の第２実施例を説明する半導体装置断面
図及び部分斜視図である。5A and 5B are a sectional view and a partial perspective view of a semiconductor device illustrating a second embodiment of the present invention.
【図６】本発明の第３実施例を説明する半導体装置断面
図及び部分斜視図である。6A and 6B are a sectional view and a partial perspective view of a semiconductor device for explaining a third embodiment of the present invention.
【図７】従来の技術を説明するための半導体装置断面図
である。FIG. 7 is a cross-sectional view of a semiconductor device for explaining a conventional technique.
Claims (5)
（６）により封止され、該半導体素子（１）の電極部と
電気的に接続される複数のリード端子（５）が前記パッ
ケージ（６）より導出されて外部との接触部をなしてい
る半導体装置において、 前記半導体装素子（１）が前記リード端子（５）上に複
数個立設された状態で樹脂封止されていることを特徴と
する半導体装置。1. A semiconductor element (1) is sealed by a resin package (6), and a plurality of lead terminals (5) electrically connected to an electrode portion of the semiconductor element (1) are provided in the package (6). In a semiconductor device which is further led out and forms a contact portion with the outside, a plurality of the semiconductor component elements (1) are erected on the lead terminals (5) and are resin-sealed. Semiconductor device.
ト（２）表面に搭載され、該半導体素子（１）の電極部
は前記プレート（２）に設けられる接触端子（３）を介
して前記リード端子（５）に接続されていることを特徴
とする請求項１記載の半導体装置。2. The semiconductor element (1) is mounted on the surface of an insulating plate (2), and the electrode portion of the semiconductor element (1) is connected via a contact terminal (3) provided on the plate (2). The semiconductor device according to claim 1, wherein the semiconductor device is connected to the lead terminal (5).
レート（２）の両面にそれぞれ搭載されていることを特
徴とする請求項２記載の半導体装置。3. The semiconductor device according to claim 2, wherein the semiconductor element (1) is mounted on each side of the insulating plate (2).
３）が形成され、リード端子（１４）には前記半導体素
子（１２）の電極パッド（１３）に対応する位置に突出
部（１５）が形成されており、該突出部（１５）と電極
パッド（１３）とが電気的に接続されるように、複数の
半導体素子（１２）が直接前記リード端子（１４）上に
立設されていることを特徴とする請求項１記載の半導体
装置。4. The semiconductor device (12) has an electrode pad (1
3) is formed, and a protrusion (15) is formed on the lead terminal (14) at a position corresponding to the electrode pad (13) of the semiconductor element (12), and the protrusion (15) and the electrode pad are formed. 2. The semiconductor device according to claim 1, wherein a plurality of semiconductor elements (12) are erected directly on the lead terminals (14) so as to be electrically connected to (13).
８）が形成され、リード端子（１９）には前記半導体素
子（１７）の電極パッド（１８）に対応する位置に凹部
（２０）が形成されており、該凹部（２０）と電極パッ
ド（１８）とが電気的に接続されるように、複数の半導
体素子（１７）が直接前記リード端子（１９）上に立設
されていることを特徴とする請求項１記載の半導体装
置。5. The semiconductor device (17) has an electrode pad (1
8) is formed, and a recess (20) is formed in the lead terminal (19) at a position corresponding to the electrode pad (18) of the semiconductor element (17), and the recess (20) and the electrode pad (18) are formed. 3. The semiconductor device according to claim 1, wherein a plurality of semiconductor elements (17) are erected directly on the lead terminals (19) so as to be electrically connected to the lead terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23553394A JPH0897358A (en) | 1994-09-29 | 1994-09-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23553394A JPH0897358A (en) | 1994-09-29 | 1994-09-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0897358A true JPH0897358A (en) | 1996-04-12 |
Family
ID=16987391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23553394A Withdrawn JPH0897358A (en) | 1994-09-29 | 1994-09-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0897358A (en) |
-
1994
- 1994-09-29 JP JP23553394A patent/JPH0897358A/en not_active Withdrawn
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