JPH0897073A - Formation of thin film terminal electrode - Google Patents

Formation of thin film terminal electrode

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Publication number
JPH0897073A
JPH0897073A JP6229445A JP22944594A JPH0897073A JP H0897073 A JPH0897073 A JP H0897073A JP 6229445 A JP6229445 A JP 6229445A JP 22944594 A JP22944594 A JP 22944594A JP H0897073 A JPH0897073 A JP H0897073A
Authority
JP
Japan
Prior art keywords
chip
thin film
bare chip
terminal electrode
bare
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6229445A
Other languages
Japanese (ja)
Inventor
Yasuhiro Shiyatou
康弘 社藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Materials Corp
Original Assignee
Mitsubishi Materials Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Materials Corp filed Critical Mitsubishi Materials Corp
Priority to JP6229445A priority Critical patent/JPH0897073A/en
Publication of JPH0897073A publication Critical patent/JPH0897073A/en
Withdrawn legal-status Critical Current

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  • Details Of Resistors (AREA)
  • Thermistors And Varistors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE: To form a thin film terminal electrode with high productivity while shortening the time required for the thin film formation process and enhancing the bonding strength of the thin film with respect to a bare chip. CONSTITUTION: When thin film terminal electrodes 15 are formed at the opposite end parts of an element of chip capacitor 10, chip thermistor, chip resistor, chip inductor or chip LC filter, i.e., a bare chip 11 of sintered ceramic, thin films 16, 17, 18 are formed at the opposite end parts of the bare chip 11 by vapor phase method in an inert gas under vacuum pressure at room temperature and then the bare chip 11 is heat treated in a reductive atmosphere.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はチップコンデンサ、チッ
プサーミスタ、チップ抵抗、チップインダクタ、チップ
LCフィルタ等のチップ型電子部品の端子電極の形成方
法に関する。更に詳しくはチップ型電子部品の素体であ
るセラミック焼結体のベアチップの両端部に薄膜による
端子電極を形成する方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming terminal electrodes of chip type electronic parts such as chip capacitors, chip thermistors, chip resistors, chip inductors and chip LC filters. More specifically, the present invention relates to a method for forming terminal electrodes made of a thin film on both ends of a bare chip of a ceramic sintered body which is an element body of a chip-type electronic component.

【0002】[0002]

【従来の技術】従来、この種の端子電極の形成方法とし
て、ベアチップの端部にスパッタリング法によりCrの
第1電極層を形成し、この上にスパッタリング法により
Cr−Ni合金、Cu−Ni合金又はCuの第2電極層
を形成した後、この上に電解メッキ又は無電解メッキ法
によりSn又はSn−Pb合金の第3電極層を形成する
方法が開示されている(特開昭60−195916)。
また別の形成方法として、第1電極層及び第2電極層に
加えて第3電極層もスパッタリング法、真空蒸着法又は
プラズマ溶射法により形成する方法が提案されている
(特開平3−225810)。
2. Description of the Related Art Conventionally, as a method of forming a terminal electrode of this type, a Cr first electrode layer is formed on the end of a bare chip by a sputtering method, and a Cr-Ni alloy or Cu-Ni alloy is formed on the first electrode layer by a sputtering method. Alternatively, a method of forming a second electrode layer of Cu and then forming a third electrode layer of Sn or Sn-Pb alloy thereon by electrolytic plating or electroless plating is disclosed (JP-A-60-195916). ).
As another forming method, a method of forming a third electrode layer in addition to the first electrode layer and the second electrode layer by a sputtering method, a vacuum vapor deposition method or a plasma spraying method has been proposed (JP-A-3-225810). .

【0003】前者の方法はスパッタリング中ベアチップ
を150℃〜200℃に加熱し、後者の方法はスパッタ
リング、真空蒸着又はプラズマ溶射している間ベアチッ
プを加熱するか、或いは室温下で電極層を形成してい
る。
The former method heats the bare chip to 150 ° C. to 200 ° C. during sputtering, and the latter method heats the bare chip during sputtering, vacuum deposition or plasma spraying, or forms an electrode layer at room temperature. ing.

【0004】[0004]

【発明が解決しようとする課題】しかし、従来のスパッ
タリング法等で加熱しながら薄膜を形成する場合には、
比較的高い薄膜接着強度が得られる反面、昇温過程で真
空度が低下するため所望の真空圧になるまで長い時間が
かかり、しかもスパッタリング法等で成膜した後真空中
で室温まで冷却するのに長い時間がかかり、結果として
生産性に劣る不具合があった。また室温でスパッタリン
グ法により薄膜を形成した場合には上記のような不具合
がない反面、ベアチップに対する薄膜の接着強度が十分
高くなかった。
However, when forming a thin film while heating by a conventional sputtering method, etc.,
Although relatively high thin film adhesion strength can be obtained, it takes a long time to reach a desired vacuum pressure because the degree of vacuum decreases during the temperature rising process. Moreover, after forming a film by a sputtering method etc., it is necessary to cool it to room temperature in vacuum. Takes a long time, and as a result, there is a problem that productivity is poor. Further, when the thin film was formed by the sputtering method at room temperature, the above-mentioned problems did not occur, but the adhesive strength of the thin film to the bare chip was not sufficiently high.

【0005】本発明の目的は、薄膜形成工程が短時間に
済み、生産性が高く、しかも薄膜のベアチップに対する
接着強度が高い薄膜端子電極の形成方法を提供すること
にある。
An object of the present invention is to provide a method for forming a thin film terminal electrode, which requires a short time for forming a thin film, has high productivity, and has high adhesion strength of a thin film to a bare chip.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するため
に、図1及び図2に示すように、本発明はチップコンデ
ンサ10等のチップ型電子部品の素体であるセラミック
焼結体のベアチップ11の両端部に薄膜の端子電極15
を形成する方法の改良である。その特徴ある構成は、真
空圧の不活性ガス中で気相法により室温下でベアチップ
11の両端部に薄膜16,17,18を形成した後、こ
の薄膜を形成したベアチップ11を還元性雰囲気で熱処
理することにある。
In order to achieve the above object, as shown in FIGS. 1 and 2, the present invention is a bare chip of a ceramic sintered body which is an element body of a chip type electronic component such as a chip capacitor 10. Thin film terminal electrodes 15 on both ends of 11
It is an improvement of the method of forming the. The characteristic structure is that after forming thin films 16, 17 and 18 on both ends of bare chip 11 at room temperature by a vapor phase method in an inert gas of vacuum pressure, bare chip 11 on which this thin film is formed is placed in a reducing atmosphere. It is in heat treatment.

【0007】以下、本発明を詳述する。本発明の端子電
極は、チップコンデンサ、チップサーミスタ、チップ抵
抗、チップインダクタ、チップLCフィルタ等のチップ
型電子部品の端子電極である。本発明の気相法として
は、スパッタリング法、真空蒸着法、プラズマ溶射法、
イオンプレーティング法、CVD(化学気相堆積)法等
がある。スパッタリング法は高周波式、マグネトロン式
等いずれの方法でもよいが、スパッタ中のベアチップの
温度上昇が少ないマグネトロン式スパッタ法が好まし
い。不活性ガスとしてはAr,He,Ne等の希ガスが
挙げられる。
The present invention will be described in detail below. The terminal electrode of the present invention is a terminal electrode of a chip-type electronic component such as a chip capacitor, a chip thermistor, a chip resistor, a chip inductor, and a chip LC filter. The vapor phase method of the present invention includes a sputtering method, a vacuum vapor deposition method, a plasma spraying method,
There are an ion plating method, a CVD (chemical vapor deposition) method, and the like. The sputtering method may be any of a high frequency method and a magnetron method, but a magnetron sputtering method in which the temperature of the bare chip during the sputtering is small is preferable. Examples of the inert gas include rare gases such as Ar, He and Ne.

【0008】端子電極15は、単一層の薄膜で構成して
もよいが、複数層の薄膜で構成することもできる。ベア
チップに直接接着する第1薄膜16として、接着強度の
高いV(バナジウム)又はCr(クロム)及びこれらの
合金からなる薄膜が好ましい。また第1薄膜上に形成さ
れる第2薄膜17として、チップ型電子部品をプリント
回路基板にはんだ付けしたときに薄膜がはんだ食われし
ないように、耐熱性の高いNi(ニッケル)又はCu
(銅)及びこれらの合金からからなる薄膜が好ましい。
更に第2薄膜上に形成される第3薄膜18として、第1
又は第2薄膜の酸化を防止しかつはんだ濡れ性を高める
ために、Au(金)からなる薄膜が好ましい。
The terminal electrode 15 may be composed of a single-layer thin film, but may be composed of a plurality of thin films. As the first thin film 16 that is directly adhered to the bare chip, a thin film made of V (vanadium) or Cr (chrome) and an alloy thereof having high adhesive strength is preferable. As the second thin film 17 formed on the first thin film, Ni (nickel) or Cu having high heat resistance is used so that the thin film is not eroded when the chip type electronic component is soldered to the printed circuit board.
Thin films of (copper) and alloys of these are preferred.
Further, as the third thin film 18 formed on the second thin film, the first
Alternatively, a thin film made of Au (gold) is preferable in order to prevent oxidation of the second thin film and enhance solder wettability.

【0009】薄膜を形成した後の熱処理温度は、100
℃〜400℃にあることが必要であり、150℃〜20
0℃が好ましい。またこの熱処理時間は、0.5時間〜
4時間にあることが必要であり、1時間〜2時間が好ま
しい。100℃未満又は0.5時間未満では薄膜の接着
強度が実用上十分でなく、400℃又は4時間を越えて
も薄膜の接着強度は400℃又は4時間のとき以上に高
くならない。この熱処理時の還元性雰囲気には、CO2
ガス又はN2ガスが用いられる。
The heat treatment temperature after forming the thin film is 100
℃ ~ 400 ℃ is required, 150 ℃ ~ 20
0 ° C is preferred. The heat treatment time is 0.5 hours
It is necessary to be 4 hours, and preferably 1 hour to 2 hours. If it is less than 100 ° C. or less than 0.5 hours, the adhesive strength of the thin film is not practically sufficient, and even if it exceeds 400 ° C. or 4 hours, the adhesive strength of the thin film does not become higher than that at 400 ° C. or 4 hours. The reducing atmosphere during this heat treatment contains CO 2
Gas or N 2 gas is used.

【0010】[0010]

【作用】室温下でチャンバ内を高真空に排気すると、比
較的速く所望の真空圧に到達する。この状態で不活性ガ
スを導入して薄膜を形成すると、不活性ガスの影響で成
膜速度が高まる。薄膜を形成した後に100℃〜400
℃の温度範囲で0.5時間〜4時間熱処理すると、ベア
チップとの界面で、又は薄膜が複数積層されている場合
には薄膜と薄膜の界面で、それぞれ金属層が拡散して薄
膜が密着する。その結果、ベアチップに強力に接着する
ようになる。熱処理時の雰囲気を還元性にすることによ
り、薄膜の酸化が防止される。
When the chamber is evacuated to high vacuum at room temperature, the desired vacuum pressure is reached relatively quickly. If an inert gas is introduced in this state to form a thin film, the film formation rate increases due to the influence of the inert gas. 100 ℃ ~ 400 after forming a thin film
When heat-treated at a temperature range of ℃ for 0.5 to 4 hours, the metal layers diffuse and adhere to each other at the interface with the bare chip or at the interface between thin films when a plurality of thin films are stacked. . As a result, it adheres strongly to the bare chip. By reducing the atmosphere during the heat treatment, oxidation of the thin film is prevented.

【0011】[0011]

【実施例】次に、本発明の実施例を図面に基づいて詳し
く説明する。図1に示すチップ型積層セラミックコンデ
ンサであるチップコンデンサ10を次の方法により製造
した。図1において、11はベアチップ、11aは内部
電極、16は第1薄膜、17は第2薄膜、18は第3薄
膜、15は第1〜第3薄膜で構成された端子電極であ
る。先ず図3に示すように多数のセラミック焼結体から
なるベアチップ11を収納するための多数の貫通孔12
のあいたチップ保持板13を用意し、このチップ保持板
13を保持板より面積の広いベース板14aの上に載せ
た。これにより貫通孔12の下部はベース板14aで塞
がれた。図2に示すようにチップ保持板13の厚さ、即
ち貫通孔12の深さはベアチップ11を挿入したときに
ベアチップ11の上端部が僅かに突出する程度の寸法を
有する。この状態で多数の貫通孔12に1つずつセラミ
ック誘電体である長さ4.40mm、幅3.15mm、
高さ1.13mmのベアチップ11を挿入した後、ベー
ス板14aとともにチップ保持板13を図示しないマグ
ネトロン式のスパッタリング装置のチャンバに入れてセ
ットした。
Embodiments of the present invention will now be described in detail with reference to the drawings. A chip capacitor 10, which is the chip type monolithic ceramic capacitor shown in FIG. 1, was manufactured by the following method. In FIG. 1, 11 is a bare chip, 11a is an internal electrode, 16 is a first thin film, 17 is a second thin film, 18 is a third thin film, and 15 is a terminal electrode composed of first to third thin films. First, as shown in FIG. 3, a large number of through holes 12 for accommodating bare chips 11 made of a large number of ceramic sintered bodies are formed.
The chip holding plate 13 having the above space was prepared, and the chip holding plate 13 was placed on the base plate 14a having a larger area than the holding plate. As a result, the lower portion of the through hole 12 was closed by the base plate 14a. As shown in FIG. 2, the thickness of the chip holding plate 13, that is, the depth of the through hole 12 has such a dimension that the upper end portion of the bare chip 11 slightly projects when the bare chip 11 is inserted. In this state, each of the through holes 12 has a ceramic dielectric of 4.40 mm in length and 3.15 mm in width.
After inserting the bare chip 11 having a height of 1.13 mm, the chip holding plate 13 together with the base plate 14a was placed in a chamber of a magnetron-type sputtering device (not shown) and set.

【0012】チャンバ内を高真空にしてArガスを2.
0×10-1Paになるまで導入し、20℃で、図2
(a)に示すように全てのベアチップ11の一方の端部
にスパッタリングをした。最初にVからなる第1薄膜を
形成し、次いでスパッタリング装置の通電電極を変え
て、第1薄膜の上にNiからなる第2薄膜を形成し、最
後に通電電極を変えて、第2薄膜の上にAuからなる第
3薄膜を形成した。一方の端部の端子電極の形成が終了
した後、ベース板14aとともにチップ保持板13をス
パッタリング装置から取出し、図2(b)に示すように
別のベース板14bをチップ保持板13の上に被せ、こ
のチップ保持板13をベース板14a及び14bで挟ん
だ状態で上下反転させてからベース板14aを外した。
ベアチップ11の他方の端部がチップ保持板13より突
出し、これによりベアチップ11を貫通孔に挿入する作
業を省略することができた。続いて図2(c)に示すよ
うにベース板14bとともにチップ保持板13をスパッ
タリング装置のチャンバに入れてセットし、ベアチップ
11の他方の端部に同様に第1〜第3薄膜を形成した。
図2において、符号Bはターゲットからスパッタリング
された金属原子である。
The inside of the chamber is evacuated to a high vacuum, and Ar gas is supplied.
It is introduced until it reaches 0 × 10 −1 Pa and then at 20 ° C., as shown in FIG.
As shown in (a), one end of all bare chips 11 was sputtered. First, the first thin film made of V is formed, then the current-carrying electrode of the sputtering apparatus is changed, the second thin film made of Ni is formed on the first thin film, and finally the current-carrying electrode is changed to change the thickness of the second thin film. A third thin film of Au was formed on top. After the formation of the terminal electrode at one end is completed, the chip holding plate 13 together with the base plate 14a is taken out from the sputtering apparatus, and another base plate 14b is placed on the chip holding plate 13 as shown in FIG. 2 (b). The chip holding plate 13 was placed on the base plate 14a and turned upside down with the chip holding plate 13 sandwiched between the base plates 14a and 14b, and then the base plate 14a was removed.
The other end of the bare chip 11 protrudes from the chip holding plate 13, whereby the work of inserting the bare chip 11 into the through hole can be omitted. Subsequently, as shown in FIG. 2C, the chip holding plate 13 together with the base plate 14b was placed in the chamber of the sputtering apparatus and set, and the first to third thin films were similarly formed on the other end of the bare chip 11.
In FIG. 2, symbol B is a metal atom sputtered from the target.

【0013】両端部に端子電極15が形成された多数の
チップコンデンサ10をスパッタリング装置から取出
し、これらのチップコンデンサ10を4等分して、第1
のグループ(実施例1)はN2(窒素)ガス雰囲気で1
50℃、1時間熱処理した。第2のグループ(実施例
2)はN2ガス雰囲気で180℃、1時間熱処理し、第
3のグループ(実施例3)はN2ガス雰囲気で200
℃、1時間熱処理した。第4のグループ(比較例1)は
熱処理しなかった。
A large number of chip capacitors 10 having terminal electrodes 15 formed on both ends thereof are taken out from the sputtering apparatus, and these chip capacitors 10 are divided into four equal parts.
Group (Example 1) in the N 2 (nitrogen) gas atmosphere was 1
It heat-processed at 50 degreeC for 1 hour. The second group (Example 2) was heat-treated at 180 ° C. for 1 hour in an N 2 gas atmosphere, and the third group (Example 3) was heated in an N 2 gas atmosphere to 200 ° C.
Heat treatment was performed at 1 ° C. for 1 hour. The fourth group (Comparative Example 1) was not heat treated.

【0014】実施例1〜実施例3及び比較例1のそれぞ
れ10個のチップコンデンサの両端部の端子電極に一対
のリード線をはんだ付けした後、チップコンデンサを引
張試験機にセットし、一対のリード線を掴んでこれらの
チップコンデンサのベアチップから薄膜16〜18が剥
離したときの引張強度を測定し、平均値を求めた。実施
例1〜実施例3及び比較例1のそれぞれ10個のチップ
コンデンサを厚さ1.6mmのガラスエポキシ基板の表
面にはんだ付けし、この基板の裏面中心に力を加えて基
板をたわませ、ベアチップの端部が欠けるか、或いはベ
アチップの端部から薄膜が剥離したときのアルミナ基板
のたわみ量を測定し、平均値を求めた。これらの結果を
表1に示す。
After soldering a pair of lead wires to the terminal electrodes at both ends of each of the ten chip capacitors of Examples 1 to 3 and Comparative Example 1, the chip capacitors were set in a tensile tester to make a pair. The lead wire was gripped, the tensile strength when the thin films 16 to 18 were peeled from the bare chips of these chip capacitors was measured, and the average value was obtained. Ten chip capacitors of each of Examples 1 to 3 and Comparative Example 1 were soldered to the front surface of a glass epoxy board having a thickness of 1.6 mm, and a force was applied to the back surface center of the board to bend the board. The amount of deflection of the alumina substrate when the edge of the bare chip was chipped or the thin film was peeled from the edge of the bare chip was measured, and the average value was obtained. Table 1 shows the results.

【0015】[0015]

【表1】 [Table 1]

【0016】表1から明らかなように、熱処理しない比
較例1のチップコンデンサと比べて実施例1〜3のチッ
プコンデンサは、端子電極の接着強度が高く、特に熱処
理温度が最高の実施例3の端子電極の接着強度は最も高
いことが判った。
As is clear from Table 1, the chip capacitors of Examples 1 to 3 have a higher bonding strength of the terminal electrodes than the chip capacitors of Comparative Example 1 without heat treatment, and in particular, the chip capacitors of Example 3 having the highest heat treatment temperature. It was found that the adhesive strength of the terminal electrode was the highest.

【0017】[0017]

【発明の効果】以上述べたように、本発明によれば、室
温でチャンバ内を真空状態にし、成膜するため、従来の
ように所望の真空圧に達するまでに長時間かからず、ま
た冷却を要しないため、薄膜形成工程が短時間に済み、
生産性が高い。成膜後の熱処理により薄膜のベアチップ
との界面の金属層が拡散し、ベアチップに対して高強度
で接着する。
As described above, according to the present invention, since the inside of the chamber is vacuumed at room temperature to form a film, it does not take a long time to reach a desired vacuum pressure as in the conventional case, and Since it does not require cooling, the thin film formation process can be completed in a short time,
High productivity. Due to the heat treatment after the film formation, the metal layer at the interface of the thin film with the bare chip is diffused and adheres to the bare chip with high strength.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例のチップ型積層セラミックコンデ
ンサの中央縦断面図。
FIG. 1 is a central longitudinal sectional view of a chip type monolithic ceramic capacitor according to an embodiment of the present invention.

【図2】本発明実施例の端子電極を形成する工程におけ
る図3のA−A線断面図。
FIG. 2 is a cross-sectional view taken along the line AA of FIG. 3 in the process of forming the terminal electrode of the embodiment of the present invention.

【図3】本発明実施例のチップ保持板とベース板の斜視
図。
FIG. 3 is a perspective view of a chip holding plate and a base plate according to the embodiment of the present invention.

【符号の説明】[Explanation of symbols]

10 チップコンデンサ 11 ベアチップ 12 貫通孔 13 チップ保持板 14a,14b ベース板 15 端子電極 16 第1薄膜 17 第2薄膜 18 第3薄膜 10 Chip Capacitor 11 Bare Chip 12 Through Hole 13 Chip Holding Plate 14a, 14b Base Plate 15 Terminal Electrode 16 First Thin Film 17 Second Thin Film 18 Third Thin Film

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 チップコンデンサ(10)、チップサーミス
タ、チップ抵抗、チップインダクタ又はチップLCフィ
ルタの素体であるセラミック焼結体のベアチップ(11)の
両端部に薄膜の端子電極(15)を形成する方法において、 真空圧の不活性ガス中で気相法により室温下で前記ベア
チップ(11)の両端部に薄膜(16,17,18)を形成した後、前
記薄膜を形成したベアチップ(11)を還元性雰囲気で熱処
理することを特徴とする薄膜端子電極の形成方法。
1. A thin film terminal electrode (15) is formed at both ends of a bare chip (11) made of a ceramic sintered body which is a body of a chip capacitor (10), a chip thermistor, a chip resistor, a chip inductor or a chip LC filter. In the method, after forming a thin film (16, 17, 18) on both ends of the bare chip (11) at room temperature by a vapor phase method in an inert gas of vacuum pressure, the bare chip (11) on which the thin film is formed A method for forming a thin film terminal electrode, characterized in that the film is heat-treated in a reducing atmosphere.
【請求項2】 不活性ガスを導入した真空圧のチャンバ
内でスパッタリング法により室温下でベアチップ(11)の
両端部にV又はCr及びこれらの合金からなる第1薄膜
(16)と、Ni又はCu及びこれらの合金からなる第2薄
膜(17)と、Auからなる第3薄膜(18)とを順次形成した
後、前記薄膜(16,17,18)を形成したベアチップ(11)を還
元性雰囲気で熱処理する請求項1記載の薄膜端子電極の
形成方法。
2. A first thin film made of V or Cr and an alloy thereof at both ends of a bare chip (11) at room temperature by a sputtering method in a vacuum pressure chamber into which an inert gas is introduced.
(16), a second thin film (17) made of Ni or Cu and their alloys, and a third thin film (18) made of Au are formed in this order, and then the thin films (16, 17, 18) are formed. The method for forming a thin film terminal electrode according to claim 1, wherein the bare chip (11) is heat-treated in a reducing atmosphere.
【請求項3】 熱処理が150℃〜200℃の温度を1
時間〜2時間保持して行われる請求項1又は2記載の薄
膜端子電極の形成方法。
3. The heat treatment is performed at a temperature of 150 ° C. to 200 ° C. for 1 hour.
The method for forming a thin film terminal electrode according to claim 1 or 2, which is carried out for a time of 2 hours.
JP6229445A 1994-09-26 1994-09-26 Formation of thin film terminal electrode Withdrawn JPH0897073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6229445A JPH0897073A (en) 1994-09-26 1994-09-26 Formation of thin film terminal electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6229445A JPH0897073A (en) 1994-09-26 1994-09-26 Formation of thin film terminal electrode

Publications (1)

Publication Number Publication Date
JPH0897073A true JPH0897073A (en) 1996-04-12

Family

ID=16892327

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6229445A Withdrawn JPH0897073A (en) 1994-09-26 1994-09-26 Formation of thin film terminal electrode

Country Status (1)

Country Link
JP (1) JPH0897073A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007109693A (en) * 2005-10-11 2007-04-26 Toray Ind Inc Capacitor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007109693A (en) * 2005-10-11 2007-04-26 Toray Ind Inc Capacitor

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