JPH0770411B2 - Chip electronic component manufacturing method - Google Patents

Chip electronic component manufacturing method

Info

Publication number
JPH0770411B2
JPH0770411B2 JP24364284A JP24364284A JPH0770411B2 JP H0770411 B2 JPH0770411 B2 JP H0770411B2 JP 24364284 A JP24364284 A JP 24364284A JP 24364284 A JP24364284 A JP 24364284A JP H0770411 B2 JPH0770411 B2 JP H0770411B2
Authority
JP
Japan
Prior art keywords
plating
chip electronic
electronic component
element body
silver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24364284A
Other languages
Japanese (ja)
Other versions
JPS61121415A (en
Inventor
鉉 板倉
巌夫 石川
孝之 黒田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP24364284A priority Critical patent/JPH0770411B2/en
Publication of JPS61121415A publication Critical patent/JPS61121415A/en
Publication of JPH0770411B2 publication Critical patent/JPH0770411B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
  • Details Of Resistors (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明はプリント配線基板への直付け実装に使用される
チップ電子部品の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a chip electronic component used for direct mounting on a printed wiring board.

従来例の構成とその問題点 チップ電子部品の代表として、チップ抵抗及びチップ型
積層セラミックコンデンサが一般的によく知られてい
る。これらのチップ電子部品の端子電極は銀とパラジウ
ムの合金ペーストを素体の端子部に塗布し、800〜900℃
で焼き付けをしたものが従来多かったが、プリント配線
基板への直付け実装の際におけるはんだ付温度条件が、
高温化するとともに、はんだ喰れの現象が頻発していた
ため、最近は素体の端子部に銀ペーストを塗布,焼付け
した後、ニッケルあるいは銅メッキを焼付けられた銀の
表面にほどこし、さらに錫または錫と鉛のはんだ付け可
能な合金メッキをほどこし、はんだ喰れの生じないチッ
プ電子部品が作られるようになった。
Configuration of Conventional Example and Its Problems Chip resistors and chip type multilayer ceramic capacitors are generally well known as representatives of chip electronic components. For the terminal electrodes of these chip electronic parts, apply an alloy paste of silver and palladium to the terminal parts of the element body, and
Although many of them were baked in the past, the soldering temperature conditions for direct mounting on the printed wiring board are
As the temperature increased and solder leaching occurred frequently, recently, after applying and baking silver paste on the terminal part of the element body, nickel or copper plating is spread on the surface of the baked silver, and tin or Solderable alloy plating of tin and lead has been applied to produce chip electronic components that do not cause solder erosion.

しかしながら、このようにメッキ処理をしたチップ電子
部品は上記の優れた特徴を有している反面、製造上厳し
いメッキ処理条件が要求されている。すなわち、電流密
度の大きいメッキ処理や長時間のメッキ処理により、端
子部に設けた銀の部分のみならず、素体の部分までメッ
キが成長する場合があり、外観不良のみならず短絡不良
にさえなるものも中には生じるため、メッキ処理条件は
おのずと低電流密度で短時間といった条件に制約される
ことがある。この場合、メッキ厚みはミクロンオーダー
の極めて薄い皮膜となってしまうことになるので、あま
り電流密度が低く、短時間の処理になると、メッキのつ
きまわりが悪くなり、このために、はんだ付性が悪くな
ってしまうことがあった。この現象は主に素体の中に含
まれる成分に大きく依存しており、したがって素体の種
類によってはメッキ処理条件の範囲を極めて狭くする必
要がある。このような臨界的な条件下では、10〜30万個
同時にメッキする際、数%の割合で素体上にメッキが成
長することはさけられない。したがって、厳しい選別が
必要となっている。
However, the chip electronic component plated as described above has the above-mentioned excellent features, but on the other hand, strict plating treatment conditions are required in manufacturing. That is, the plating may grow not only on the silver part provided on the terminal part but also on the element part due to the plating process with a large current density or the plating process for a long time. Since there are some that occur in some cases, the plating treatment conditions may be naturally limited to low current density and short time. In this case, the plating thickness will be an extremely thin film on the order of microns, so if the current density is too low and the treatment is performed for a short time, the throwing power of the plating will deteriorate, and therefore the solderability will be poor. Sometimes it got worse. This phenomenon mainly depends largely on the components contained in the element body, and therefore it is necessary to make the range of the plating treatment condition extremely narrow depending on the type of the element body. Under such a critical condition, when 100 to 300,000 pieces are plated at the same time, it is unavoidable that the plating grows on the element body at a rate of several percent. Therefore, strict selection is required.

発明の目的 本発明は素体上に成長したメッキを除去することを目的
とするものである。
OBJECT OF THE INVENTION The present invention aims to remove the plating that has grown on the element body.

発明の構成 この目的を達成するために本発明は、メッキ処理したチ
ップ電子部品をはんだ付けされる温度程度で熱処理する
ことにより、素体上に成長したメッキを除去するもので
ある。
To achieve this object, the present invention removes the plating grown on the element body by heat-treating the plated chip electronic component at a temperature at which it is soldered.

実施例の説明 以下、本発明を実施例にもとづき詳細に説明する。Description of Embodiments Hereinafter, the present invention will be described in detail based on embodiments.

積層セラミックコンデンサの端子電極として、まず端子
部に銀ペーストを塗布し、820±20℃で焼付けた後、ニ
ッケルを電気メッキし、その上にさらに錫と鉛の合金メ
ッキをほどこした。このようにして得られた積層セラミ
ックコンデンサを倍率20倍の実体顕微鏡にて観察し、第
3図に示すような素体上にメッキの成長した積層セラミ
ックコンデンサを100個取り出した。図中4は素体、5
は銀、6はニッケルメッキ、7は錫と鉛の合金メッキ、
8はメッキ成長部である。この100個の重量は約2gであ
り、この重量に対して50倍、すなわち100gのはんだ付け
される温度200〜250℃に加熱されたジルコニア中に上記
積層セラミックコンデンサを埋没させ、撹拌しながら熱
処理した。
As a terminal electrode of a monolithic ceramic capacitor, a silver paste was first applied to the terminal portion, baked at 820 ± 20 ° C., electroplated with nickel, and then an alloy plating of tin and lead was applied thereon. The thus-obtained monolithic ceramic capacitors were observed with a stereoscopic microscope at a magnification of 20 times, and 100 monolithic ceramic capacitors with plating grown on the element body as shown in FIG. 3 were taken out. In the figure, 4 is a body
Is silver, 6 is nickel plating, 7 is tin-lead alloy plating,
Reference numeral 8 is a plated growth portion. The weight of 100 pieces is about 2 g, which is 50 times the weight, that is, 100 g of the laminated ceramic capacitors are immersed in zirconia heated to a soldering temperature of 200 to 250 ° C. did.

この結果、5〜30秒間上記の方法で熱処理したものは第
1図に示すように素体1と銀2の境界部に沿ってニッケ
ルメッキ3、錫と鉛の合金メッキ4の端が切れており、
素体2の表面には完全にメッキ成長部は観察されなかっ
た。さらに表面の光沢が良好となり、はんだ付性も極め
て良好であった。
As a result, as shown in FIG. 1, when the heat treatment for 5 to 30 seconds was performed, the nickel plating 3 and the tin-lead alloy plating 4 were cut along the boundary between the element body 1 and the silver 2. Cage,
No plated growth was observed on the surface of the element body 2. Furthermore, the surface gloss was good, and the solderability was also very good.

次表は他の熱処理と本発明の熱処理との比較を示すもの
である。この表から明らかなように、メッキの素体への
成長除去の効果,はんだ付性,端子電極の光沢状況の全
てにおいて本発明は優れているといえる。
The following table shows a comparison of other heat treatments with the heat treatment of the present invention. As is clear from this table, it can be said that the present invention is excellent in all of the effect of removing the growth of the plating on the element body, the solderability, and the gloss condition of the terminal electrode.

また、第2図は本発明の処理条件における、熱処理温度
と処理時間の最適値を示す図である。この図からわかる
ように、220±20℃、5〜25秒が最適条件といえる。
Further, FIG. 2 is a diagram showing the optimum values of the heat treatment temperature and the treatment time under the treatment conditions of the present invention. As can be seen from this figure, 220 ± 20 ° C and 5 to 25 seconds are the optimum conditions.

発明の効果 以上のごとく本発明はチップ電子部品の銀を主体とする
端子電極上にニッケルメッキをほどこし、さらにその上
にはんだ付け可能な合金メッキをほどこした後、200〜2
50℃に加熱した熱媒体中を通して熱処理を行うものであ
り、上記温度で熱処理を行うとチップ電子部品素体にま
で成長したメッキ成長部を簡単、確実に除去して短絡不
良をなくすことができるだけでなく、上記合金メッキの
表面もはんだ付性の良いものとなり、しかも熱処理温度
が200〜250℃とはんだ付程度の低温処理であるのでチッ
プ部品素子等への熱的影響も少ないものとすることがで
きるのである。
As described above, according to the present invention, after nickel-plated on the terminal electrode mainly composed of silver of the chip electronic component and further solderable alloy plating on the terminal electrode, 200-2
The heat treatment is performed through a heat medium heated to 50 ° C. When the heat treatment is performed at the above temperature, it is possible to easily and surely remove the plated growth portion that has grown to the chip electronic component element body to eliminate short circuit defects. Not only that, the surface of the alloy plating also has good solderability, and since the heat treatment temperature is a low temperature treatment of about 200 to 250 ° C, such as soldering, there should be little thermal influence on the chip component element, etc. Can be done.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の方法によりチップ電子部品素体上に成
長したメッキを除去した後のチップ電子部品を示す一部
断面斜視図、第2図は本発明の方法における温度及び処
理時間の最適条件を示す特性図、第3図は従来の未処理
のチップ電子部品の状態を示す一部断面斜視図である。 1……素体、2……銀、3……ニッケルメッキ、4……
合金メッキ。
FIG. 1 is a partial cross-sectional perspective view showing the chip electronic component after removing the plating grown on the chip electronic component body by the method of the present invention, and FIG. 2 is the optimum temperature and processing time in the method of the present invention. FIG. 3 is a partial cross-sectional perspective view showing the state of a conventional unprocessed chip electronic component, which shows the condition. 1 ... Element, 2 ... Silver, 3 ... Nickel plating, 4 ...
Alloy plating.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 // H01C 1/142 H01G 4/232 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location // H01C 1/142 H01G 4/232

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】銀を主体とする端子電極上にニッケルメッ
キをほどこし、さらにその上にはんだ付け可能な合金メ
ッキをほどこした後、200〜250℃に加熱した熱媒体中を
通して熱処理を行うチップ電子部品の製造方法。
1. A chip electron in which a terminal electrode mainly composed of silver is plated with nickel, and a solderable alloy is further plated thereon, and then heat treatment is carried out by passing through a heating medium heated to 200 to 250 ° C. Manufacturing method of parts.
JP24364284A 1984-11-19 1984-11-19 Chip electronic component manufacturing method Expired - Lifetime JPH0770411B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24364284A JPH0770411B2 (en) 1984-11-19 1984-11-19 Chip electronic component manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24364284A JPH0770411B2 (en) 1984-11-19 1984-11-19 Chip electronic component manufacturing method

Publications (2)

Publication Number Publication Date
JPS61121415A JPS61121415A (en) 1986-06-09
JPH0770411B2 true JPH0770411B2 (en) 1995-07-31

Family

ID=17106855

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24364284A Expired - Lifetime JPH0770411B2 (en) 1984-11-19 1984-11-19 Chip electronic component manufacturing method

Country Status (1)

Country Link
JP (1) JPH0770411B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0824081B2 (en) * 1986-07-08 1996-03-06 松下電器産業株式会社 Manufacturing method of chip parts
JPH03167802A (en) * 1989-11-28 1991-07-19 Matsushita Electric Ind Co Ltd Manufacture of resistive element for rheostat

Also Published As

Publication number Publication date
JPS61121415A (en) 1986-06-09

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