JPH0895232A - Exposuring method for exposure mask and photoresist - Google Patents

Abstract

PURPOSE: To contribute to improve the precision of a pattern forming with use of a mask, in an exposure mask forming a light shielding pattern of chromium on a substrate and an exposure method for the photoresist using the mask. CONSTITUTION: Inside the light shielding pattern 2 of the exposure mask 1, the exposure hole 3 having the size > the resolution limit value of the photoresist on which the exposing image is formed with use of the exposure device and the mask, and the numerous slits 4 having the width < the resolution limit value is respectively composed. In the exposure mask 1 provided with the through hole 3 with use of the positive photoresist, any light shielding area is not disposed outside the hole forming area permitting the light shielding pattern 2 for forming the through hole 3. With use of the mask comprised of the slit 4 or the mask not disposing the light shielding area, the exposure process of photoresist is performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of exposing a mask for exposure and a resist used for manufacturing a semiconductor device or the like, and more particularly, to a mask structure for reducing variations in the warp of the mask and a resist pattern formed using the mask. Regarding refinement.

In recent years, as the performance and integration of semiconductor devices have increased, the constituent patterns have become finer, and the light-shielding patterns formed on the exposure mask have become finer. ， As for the overlay accuracy during use, higher precision is required.

[0003]

2. Description of the Related Art A mask substrate (original plate for mask) is a transparent substrate made of quartz or glass with a chromium film having a thickness of about 1000Å deposited thereon. Generally, the chromium film is made of chromium oxide or metallic chromium.・ Three layers of chromium oxide.

In such a mask substrate, the chromium film adhered surface warps in a concave shape due to the internal stress generated in the chromium film. The exposure mask that forms the exposure image on the resist is
A resist film is deposited on the chrome film of the mask substrate, and a resist pattern obtained by exposing and developing the resist film is used,
It is created by removing unnecessary portions of the chrome film by etching.

Such an exposure mask has a larger size than an area for forming an exposure through hole (a through hole formation allowing area), and a negative resist used for etching a chrome film is a predetermined exposure target. While there is no light-shielding region (chrome) outside the region, in the case where the positive resist is used for etching the chromium film, the light-shielding region exists outside the through hole formation region.

FIG. 5 is a cross-sectional view of a mask substrate and a conventional exposure mask. A mask substrate 20 in which a chromium film 22 having a thickness of about 1000 Å is adhered to the surface of a transparent substrate 21 is formed on the chromium film 22. The internal stress causes the chromium film 22 adhered surface to warp in a concave shape as shown in (a). The warp amount d is about 0.5 μm in the 6 inch × 6 inch substrate 20.

Then, as shown in (b), a large number of through holes 27 for exposure are formed by using a positive resist, and an exposure mask 23 is formed.
The light-shielding pattern 24 has a light-shielding region 26 outside the formation allowance region 25 of the through hole 27, and the warp of the mask 23 in which a part of the internal stress is released due to the formation of the through hole 27, etc. Less than the warp.

The amount of decrease in the warp depends on the type of the mask 23, that is, the aperture ratio (exposure ratio of the substrate) depending on the shape, size, and number of the through holes 27, and the warp is caused by the chromium film 22. 6 inch x 6 inch mask substrate 20,
When a pair of control marks at 100 mm intervals are formed by etching the chrome film 22 together with the required light-shielding pattern 24, the chrome film
The gauge length is 100mm + 0.03 due to the open difference of 22 internal stress.
It will be about μm to +0.05 μm.

Further, the warp of the exposure mask 23 is different depending on whether a positive resist or a negative resist is used for forming the exposure mask 23, that is, the presence or absence of the light shielding region 26, and
It may be necessary to use a mask formed using a positive resist and a mask formed using a negative resist in combination.

[0010]

As described above,
In the conventional exposure mask 23 in which the light shielding pattern 24 is formed from the chrome film 22 of the mask substrate 20, the amount of warp restoration differs depending on the difference in the through holes 27, and the positional accuracy of the through holes 27 in the mask 23 and when the mask 23 is used. However, there is a problem in that the overlay accuracy of the device is deteriorated and the miniaturization of the semiconductor device pattern is hindered.

Further, when a combination of a positive resist is used for forming the through holes 27 and a negative resist is used for forming the wiring pattern, that is, when a combination of those with and without the light shielding region 26 is used, The above problems became more remarkable.

[0012]

SUMMARY OF THE INVENTION An object of the present invention is to reduce variations in the amount of restoration of warpage that occurs when a chromium film on a mask substrate is etched, and to use a mask and a negative formed by using a positive resist. For the combined use of masks formed using a shaped resist, it is to be able to form a highly accurate exposure image, the purpose of which, in the exposure mask in which the light-shielding pattern of chromium is formed on the transparent substrate,
In the light-shielding pattern, an exposure through hole having a size larger than a resolution limit value of a resist on which an exposure image is formed using the exposure device and the mask, and a large number of slits having a width smaller than the resolution limit value. In the exposure mask in which the through holes and slits are formed by using the positive resist, the light-shielding pattern corresponds only to the formation allowable area of the through holes (outside the formation area of the through holes). No light-shielding region is provided on one side), and the resist formed on the wafer or the like is exposed using the exposure mask.

[0013]

In the above means, the plurality of slits having a width smaller than the resolution limit value of the resist on which the exposure image is formed by using the exposure device and the exposure mask, that is, the plurality of unresolved slits form a light shielding pattern. The internal stress of the chrome layer is divided to reduce the warp of the mask. As a result, variations in mask warpage are reduced.

Further, in the exposure mask formed by using the positive type resist, if the light shielding region is not provided outside the formation permissible region of the through hole for forming the exposure image, the warp of the mask uses the negative type resist. Then, the warp of the created exposure mask is approximated.

In the exposure method using the mask, the positional accuracy of the through-holes for forming the exposure image, the mask alignment accuracy, and the mask overlay accuracy are improved, which enables the exposure image to be finer and the semiconductor device pattern to be formed. Contributes to miniaturization and high density.

[0016]

1 is an explanatory view of an exposure mask according to a first embodiment of the present invention, and FIG. 2 is an explanatory view of an exposure mask according to a second embodiment of the present invention.

1A and 1B, an exposure mask 1 made from a conventional mask substrate 20 using a positive resist.
Is formed by forming a light-shielding pattern 2 containing Cr as a main material on the surface of a transparent substrate (quartz substrate) 21.

During the exposure process using the mask 1, the light-shielding pattern 2 in the central portion (perforation hole formation permitting region) of the substrate 21 corresponding to the chip pattern forming region of the resist to be exposed is shown in FIG.
As shown enlarged in (c), a large number of rectangular through holes 3 and slits 4 are formed.

A large number of rectangular through holes 3 for forming an exposure image on a resist to be exposed (resist on a wafer) by using a mask 1.
Are larger than the resolution limit value of the exposure apparatus and the resist, for example, in a size of 2 μm × 2 μm, and are aligned in a matrix in the vertical and horizontal directions at intervals of 5 μm.

A large number of slits 4 which do not form an exposure image on the resist on the wafer using the mask 1 have a width smaller than the resolution limit value of the exposure apparatus and the resist, for example, in the case of a magnifying mask 1 having a width of 5 times. Is about 1 μm and the length is about 4 μm.

When the resist on the wafer is exposed using the mask 1 as described above, as shown in FIG.
Although the exposure image 5 of the through hole 3 is formed on the resist, the exposure image of the slit 4 is not formed, and the through hole is formed in the exposed image 5 portion by the developing process after the exposure.

2A and 2B, an exposure mask 6 formed from a conventional mask substrate 20 using a positive resist.
Is formed by forming a light shielding pattern 7 on the surface of a transparent substrate (quartz substrate) 21.

At the time of the exposure process using the mask 6, the light-shielding pattern 7 in the central portion (perforation hole formation permitting region) of the substrate 21 corresponding to the chip pattern forming region of the resist to be exposed is shown in FIG.
As shown in an enlarged view in (c), a large number of rectangular through holes 3 and lattice-shaped slits 8 are formed.

A large number of rectangular through holes 3 for forming an exposure image on the resist to be exposed (resist on the wafer) using the mask 6.
Are larger than the resolution limit value of the exposure apparatus and the resist, for example, in a size of 2 μm × 2 μm, and are aligned in a matrix in the vertical and horizontal directions at intervals of 5 μm.

The grid-like slits 8 which do not form an exposure image on the resist on the wafer by using the mask 6 have a width smaller than the resolution limit value of the exposure apparatus and the resist, for example, in the case of the magnifying mask 1 having a width of 5 times. Is a combination of many linear slits of 1 μm.

When the resist on the wafer is exposed using such a mask 6, an exposure image 5 of the through hole 3 (see FIG. 1D) is formed, while an exposure image of the slit 8 is formed. However, a through hole is formed in the exposed image 5 portion by the developing process after exposure.

FIG. 3 is an explanatory view of an exposure mask according to the third embodiment of the present invention. In FIGS. 3A and 3B, an exposure mask 9 formed from a conventional mask substrate 20 using a positive resist has a light-shielding pattern 10 formed on the surface of a transparent substrate (quartz substrate) 21. .

Light-shielding pattern 10 that substantially covers the entire surface of the substrate 21
Is formed of a through hole formation permitting region 11 in the central portion corresponding to the chip pattern forming region of the resist to be exposed at the time of exposure processing using the mask 9 and a light shielding region 12 outside thereof.

As shown enlarged in FIG. 3 (c), the allowable area 11
A large number of rectangular through holes 3 and a grid-like slit 8 are formed in the same, and a slit 13 is formed in the light-shielding region 12 by extending the straight slit end portion forming the grid-like slit 8 with the same width.

A large number of rectangular through holes 3 for forming an exposure image on the resist to be exposed (resist on the wafer) using the mask 9.
Are larger than the resolution limit value of the exposure apparatus and the resist, for example, in a size of 2 μm × 2 μm, and are aligned in a matrix in the vertical and horizontal directions at intervals of 5 μm.

The grid-like slits 8 and the slits 13 which do not form an exposure image on the resist on the wafer using the mask 9 are
A width smaller than the resolution limit value of the exposure apparatus and the resist,
For example, in the magnifying mask 1 having a magnification of 5 times, the lattice-shaped slits 8 are formed by combining a plurality of linear slits each having a width of 1 μm, and the linear slits are extended with the same width to form the slit 13.

When the resist on the wafer is exposed using the mask 9 as described above, the exposure image 5 of the through hole 3 (see FIG. 1D) is formed, but the exposure images of the slits 8 and 13 are formed. Is not formed, and a through hole is formed in the exposed image 5 portion by the developing process after exposure.

FIG. 4 is an explanatory view of a test sample for confirming the effect of the present invention. (A) and (b) are explanatory views of the cross mark 17 formed for measuring the dimensional change of the mask, and (c) is. FIG. 3 is an explanatory diagram of the through holes 3 formed in the light shielding pattern 16 of the test sample A, and (d) is an explanatory diagram of the through holes 18 formed in the light shielding pattern of the test sample D.

In FIG. 4, a test sample 15 assuming a magnifying mask (reticle) of 5 times has a 6 inch × 6 inch and 0.25 inch thick quartz substrate 21 coated with a 1000 Å thick chromium film. The light shielding pattern 16 and the cross mark 17 are formed from the chrome film.

The interval between the pair of reference points 17 that sandwich the light-shielding pattern 16 in the up-down direction or the left-right direction is 120 mm (120000 μm), and in the light-shielding pattern 16 of 90 mm × 90 mm, A, B, C,
Different through holes were formed for each of the four types of samples D.

In the light-shielding pattern 16 of the test sample A corresponding to the conventional hole exposure mask, as shown in FIG.
A large number of 2 μm × 2 μm through holes 3 were formed in a matrix at a pitch of 5 μm.

In the light-shielding pattern 16 of the test sample B, which is an application example of the present invention, the same large number of through holes 3 and slits 4 as the mask 1 described with reference to FIG. 1 were formed. In the light-shielding pattern 16 of the test sample B corresponding to the hole exposure mask to which the present invention is applied, the same many through holes 3 and slits 4 as the mask 1 described with reference to FIG. 1 were formed.

In the light-shielding pattern 16 of the test sample C corresponding to another hole exposure mask to which the present invention is applied, the same many through holes 3 and slits 8 as the mask 6 described with reference to FIG. 2 are formed. .

In the light-shielding pattern 16 of the test sample D corresponding to the conventional wiring exposure mask, as shown in FIG. 4D, a large number of slits 18 having a width of 2 μm and extending over the entire width of 2 μm are provided.
It was formed at m intervals.

To prepare the samples 15 classified into A to D, a mask substrate having a thickness of 1000 Å and having a similar warpage was used, and the through hole 3, slit 4, slit 8 and slit were used.
For 18 and the control point 17, the same electron beam exposure apparatus was used to expose and develop the resist film deposited on the mask substrate to form a resist pattern, and the chromium film was etched using the resist pattern.

When the distance between the pair of gauges 17 that sandwich the light-shielding pattern 16 in the left-right direction is m and the distance between the pair of gauges 17 that sandwich the light-shielding pattern 16 in the vertical direction is n, the gauge-point spacings m and n are The distances m and n are slightly different depending on the peculiarities of the exposure apparatus.
On the other hand, the variation among the A to D categorized samples 15 is 0.001 μm or less, which is negligible with respect to the change due to the restoration of the warp of the mask substrate.

The following table shows the measurement results of the reference mark intervals m and n of the sample 15 prepared by etching the chromium film deposited on the mask substrate, classified by A to D,
Both the intervals m and n using the warped mask substrate change to the + side due to the formation of the light shielding pattern 16.

[0043]

[Table 1] From Table 1, the amount of warp restoration of A is minimum, the amount of warp restoration of D is maximum, and the amount of warpage restoration of B and C is smaller than that of D (B and C have the same amount of chromium film as D. (Internal stress cannot be reduced), B and C have a larger amount of warp restoration than A, B and C according to the present invention have a larger amount of C warp restoration, and the difference between A and D according to the conventional technique is the gauge length m. Is 0.07 μm, and the gauge length n is 0.047 μm.
It can be seen that the difference between B according to the present invention and D according to the prior art is 0.012 μm for the gauge length m and 0.015 μm for the gauge length n.

[0044]

As described above, the exposure mask according to the present invention has a large amount of warp restoration of the substrate, and as a result, the positional accuracy of the exposure image forming through hole, the mask alignment accuracy, and the mask overlay accuracy. Will get better. as a result,
Enables finer exposure image, finer semiconductor device pattern and higher density.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an exposure mask according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an exposure mask according to a second embodiment of the present invention.

FIG. 3 is an explanatory diagram of an exposure mask according to a third embodiment of the present invention.

FIG. 4 is an explanatory diagram of a test sample for confirming the effect of the present invention.

FIG. 5 is a sectional view of a mask substrate and a conventional exposure mask.

[Explanation of symbols]

 1,6,9 Exposure mask 2,7,10 Light-shielding pattern 3 Exposure hole 4,8,13 Slit 5 Exposure image 20 Mask substrate 21 Light transmission substrate

Claims (3)

[Claims] 1. An exposure mask in which a light-shielding pattern for forming a desired exposure image on a resist is formed on a transparent substrate,
In the light shielding pattern, an exposure through hole having a size larger than a resolution limit value of the exposure device and the resist, and a plurality of slits having a width smaller than the resolution limit value are formed. Exposure mask. 2. The exposure mask according to claim 1, wherein the through hole is formed by using a positive resist, wherein the light shielding pattern is formed only corresponding to a formation permitted region of the through hole. Characteristic exposure mask. 3. A method for exposing a resist, which comprises exposing the resist using the exposure mask and the exposure apparatus according to claim 1. Description: