JP2624335B2 - Resist exposure method - Google Patents

Resist exposure method

Info

Publication number
JP2624335B2
JP2624335B2 JP1156463A JP15646389A JP2624335B2 JP 2624335 B2 JP2624335 B2 JP 2624335B2 JP 1156463 A JP1156463 A JP 1156463A JP 15646389 A JP15646389 A JP 15646389A JP 2624335 B2 JP2624335 B2 JP 2624335B2
Authority
JP
Japan
Prior art keywords
light
resist
pattern
shielding film
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP1156463A
Other languages
Japanese (ja)
Other versions
JPH0321008A (en
Inventor
治 島田
Original Assignee
松下電子工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 松下電子工業株式会社 filed Critical 松下電子工業株式会社
Priority to JP1156463A priority Critical patent/JP2624335B2/en
Publication of JPH0321008A publication Critical patent/JPH0321008A/en
Application granted granted Critical
Publication of JP2624335B2 publication Critical patent/JP2624335B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、特に半導体装置製造分野におけるフォトリ
ソグラフィ工程に用いられるレジスト露光方法に関する
ものである。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resist exposure method used in a photolithography process particularly in the field of semiconductor device manufacturing.

従来の技術 近年、半導体装置の製造方法は工程が複雑になるとと
もに被処理半導体基板表面上での段差がますます大きく
なっている。一方パターンの微細化も進み、寸法の許容
値も小さくなり、フォトリソグラフィ工程における露光
装置の露光量コントロールが非常に難しくなってきてい
る。
2. Description of the Related Art In recent years, a semiconductor device manufacturing method has become complicated, and the level difference on the surface of a semiconductor substrate to be processed has been increasing. On the other hand, pattern miniaturization has progressed, and dimensional tolerance has become smaller, and it has become extremely difficult to control the exposure amount of an exposure apparatus in a photolithography process.

以下に従来の半導体装置の製造方法について説明す
る。
Hereinafter, a conventional method for manufacturing a semiconductor device will be described.

第2図は従来の半導体装置の製造方法のフォトリソグ
ラフィ工程の断面図を示す。第2図において、1は露光
装置の水銀ランプより発せられた光、2は石英板、3は
クロムパターン、5はレジストパターン、6は多結晶シ
リコン、8は酸化膜、9はシリコン基板、11は段差下部
のレジスト残りである。従来の方法は、平坦部に形成さ
れたレジストパターンの寸法Lを測定することで適正な
露光量を決定していた。即ち、希望するレジスト寸法L
を得て、かつ図中凹所に示したようなレジスト残り11が
ないようにした。
FIG. 2 is a cross-sectional view of a photolithography step in a conventional method for manufacturing a semiconductor device. In FIG. 2, 1 is light emitted from a mercury lamp of an exposure apparatus, 2 is a quartz plate, 3 is a chromium pattern, 5 is a resist pattern, 6 is polycrystalline silicon, 8 is an oxide film, 9 is a silicon substrate, 11 Is the resist residue below the step. In a conventional method, an appropriate exposure amount is determined by measuring a dimension L of a resist pattern formed on a flat portion. That is, the desired resist dimension L
Was obtained, and there was no remaining resist 11 as shown in the recess in the figure.

発明が解決しようとする課題 しかしながら上記従来の方法では、レジスト寸法Lは
シリコン基板に対して横方向成分であり、他方、段差下
部のレジスト残り11は、シリコン基板に対して深さ方向
成分であり、両者は必ずしも十分な対応が取れず、その
結果として段差下部においてレジスト残り11を発生させ
てしまうか、逆に、過度な露光量により必要以上にレジ
スト寸法を細らせてしまうという欠点を有していた。
However, in the above-described conventional method, the resist dimension L is a component in the lateral direction with respect to the silicon substrate, while the remaining resist 11 below the step is a component in the depth direction with respect to the silicon substrate. However, there is a drawback that the two cannot always cope sufficiently, and as a result, a resist residue 11 is generated below the step, or conversely, the resist dimension is reduced more than necessary due to an excessive exposure dose. Was.

本発明は上記従来の問題点を解決するもので、段差下
部においてレジスト残りを防ぎかつ適正なレジスト寸法
の得られる半導体装置の製造方法を提供することを目的
する。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing a resist remaining under a step and obtaining an appropriate resist size.

課題を解決するための手段 この目的を達成するために本発明のレジスト露光方法
は、光透過なガラス基板と、その一主面にパターン化さ
れ選択的に光を遮断する金属遮光膜と、前記金属遮光膜
と異なった位置において前記主面にパターン化され、選
択的に光強度を減衰する、複数の異なった水透過率を有
する複数の光半透過膜とを備えたフォトマスクのパター
ンを、等倍もしくは縮小投影露光法によってレジストを
塗布した基板上に央転写し、現像後、前記半透過膜のパ
ターンが転写された平坦部に、その光透過率に応じたレ
ジスト残りを発生させ、前記レジスト残りに基づいて適
正な露光量を決定することを特徴とする。
Means for Solving the Problems In order to achieve this object, a resist exposure method of the present invention comprises a light-transmitting glass substrate, a metal light-shielding film patterned on one main surface thereof and selectively blocking light, Patterned on the main surface at a position different from the metal light-shielding film, selectively attenuate the light intensity, a photomask pattern comprising a plurality of light translucent films having a plurality of different water transmittance, Centrally transferred onto a substrate coated with a resist by equal magnification or reduced projection exposure method, and after development, a flat portion where the pattern of the semi-transmissive film is transferred, a resist residue corresponding to the light transmittance is generated, A proper exposure amount is determined based on the remaining resist.

作用 この方法によって、フォトマスクを通過した光の強度
を選択的に変えることができ、被処理半導体基板上の平
坦部に残ったレジストの膜厚を測定することで、適正な
露光量を決定することができる。即ち、被処理半導体基
板上の段差下部のレジスト残りを防ぐことができる適正
な露光量と対応する平坦部のレジスト残膜量をモニター
しておくことで、適正露光量が平坦部のレジスト膜厚か
ら求められる。
According to this method, the intensity of light passing through the photomask can be selectively changed, and the appropriate exposure amount is determined by measuring the film thickness of the resist remaining on the flat portion on the semiconductor substrate to be processed. be able to. That is, by monitoring the appropriate exposure amount that can prevent the resist remaining below the step on the semiconductor substrate to be processed and the corresponding resist remaining film amount in the flat portion, the appropriate exposure amount can be adjusted to the resist film thickness in the flat portion. Required from.

実施例 以下本発明の一実施例について、図面を参照しながら
説明する。
An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の第1の実施例における半導体装置の
製造方法の被処理半導体基板及びマスクの断面を示すも
のである。第1図において、1は露光装置の水銀ランプ
より発せられる光、2はマスク基板としての石英板、3
はクロムパターン、4は光半透過膜の有機膜のパター
ン、5はパターン形成されたポジ型レジスト、6は多結
晶シリコン、7は半透過膜パターンによって形成された
ポジ型レジスト、8は酸化膜、9はシリコン基板であ
る。
FIG. 1 shows a cross section of a semiconductor substrate to be processed and a mask in a method of manufacturing a semiconductor device according to a first embodiment of the present invention. In FIG. 1, 1 is light emitted from a mercury lamp of an exposure apparatus, 2 is a quartz plate as a mask substrate, 3
Is a chrome pattern, 4 is a pattern of an organic film of a light semi-transmissive film, 5 is a patterned positive resist, 6 is polycrystalline silicon, 7 is a positive resist formed by a semi-transmissive film pattern, 8 is an oxide film , 9 are silicon substrates.

第1図で平坦部分にレジスト残り7が発生したとき、
その膜厚を測定する。その膜厚によって、そのときの露
光量が段差下部10の部分にレジスト残りを発生させない
十分な露光量であるかを判定できる。またその膜厚は第
1図には4種類パターンを示したが実際には、多数の連
続的に光透過率の異なった光半透過のパターンから、最
適のレジスト残りが発生する臨界点を求めることで容易
に測ることができる。
In FIG. 1, when a resist residue 7 occurs on a flat portion,
The film thickness is measured. Based on the film thickness, it can be determined whether or not the exposure amount at that time is a sufficient exposure amount that does not cause the resist to remain in the portion under the step 10. FIG. 1 shows four types of film thicknesses. In practice, however, a critical point at which an optimum resist residue occurs is obtained from a large number of continuous light transmissive patterns having different light transmittances. Can be easily measured.

以上のように本実施例によれば、マスクの一部分に有
機膜の光半透過膜を設けることにより、被処理半導体基
板上の一平坦部に所定のレジスト残り7を発生させ、そ
の膜厚を検知することで、段差下部にレジストを残すこ
とのない適正な露光量を決定することができる。
As described above, according to the present embodiment, by providing a light semi-transmissive film of an organic film on a part of the mask, a predetermined resist residue 7 is generated on one flat portion on the semiconductor substrate to be processed, and the film thickness is reduced. By detecting, it is possible to determine an appropriate exposure amount without leaving a resist under the step.

第1の実施例においてレジスト5はポジ型としたが、
レジスト5はネガ型でも良い。但し、その場合マスクの
遮光部及び透光部は逆転する。
In the first embodiment, the resist 5 is of a positive type.
The resist 5 may be a negative type. However, in that case, the light shielding part and the light transmitting part of the mask are reversed.

第1の実施例において多結晶シリコン6、酸化膜8は
一プロセスの例であり、これらに限定されることはな
く、随意の素材が利用可能である。
In the first embodiment, the polycrystalline silicon 6 and the oxide film 8 are examples of one process, and the present invention is not limited to these processes, and any material can be used.

発明の効果 以上のように本発明はマスクの金属遮光膜とパターン
を異にしたパターンで選択的に光強度を減衰する光半透
過膜を有し、そのパターンを被処理半導体基板上の平坦
部に転写し、その平坦部にレジスト残りを発生させるこ
とで、適正な露光量を選択でき、正確なパターンニング
をすることができる。
As described above, the present invention has a light transmissive film that selectively attenuates light intensity with a pattern having a different pattern from the metal light shielding film of the mask, and the pattern is formed on a flat portion on the semiconductor substrate to be processed. By transferring the resist onto the flat surface and generating a resist residue on the flat portion, an appropriate exposure amount can be selected and accurate patterning can be performed.

【図面の簡単な説明】[Brief description of the drawings]

第1図は本発明の第1の実施例における半導体装置の製
造方法の一工程断面図、第2図は従来の半導体装置の製
造方法の一工程断面図である。 1……光、2……石英板、3……クロムパターン、4…
…光半透過の有機膜パターン、5……レジストパター
ン、6……多結晶シリコン、7……レジスト残り、8…
…酸化膜、9……シリコン基板、10……段差下部、11…
…レジスト残り。
FIG. 1 is a cross-sectional view of one step of a method for manufacturing a semiconductor device according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of one step of a method of manufacturing a conventional semiconductor device. 1 ... light, 2 ... quartz plate, 3 ... chrome pattern, 4 ...
... Semi-transparent organic film pattern, 5 ... Resist pattern, 6 ... Polycrystalline silicon, 7 ... Remaining resist, 8 ...
... Oxide film, 9 ... Silicon substrate, 10 ... Lower step, 11 ...
... resist remaining.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】光透過なガラス基板と、その一主面にパタ
ーン化され選択的に光を遮断する金属遮光膜と、前記金
属遮光膜と異なった位置において前記主面にパターン化
され、選択的に光強度を減衰する、異なった水透過率を
有する複数の光半透過膜とを備えたフォトマスクのパタ
ーンを、等倍もしくは縮小投影露光法によってレジスト
を塗布した基板上に央転写し、現像後、前記半透過膜の
パターンが転写された平坦部に、その光透過率に応じた
レジスト残りを発生させ、前記レジスト残りに基づいて
適正な露光量を決定することを特徴とするレジスト露光
方法。
1. A light-transmitting glass substrate, a metal light-shielding film patterned on one main surface thereof to selectively block light, and a metal-light-shielding film patterned on the main surface at a position different from the metal light-shielding film. Attenuate the light intensity, the pattern of the photomask with a plurality of light semi-transmissive films having different water transmittance, centrally transferred onto a substrate coated with a resist by a 1: 1 or reduced projection exposure method, After the development, a resist residue corresponding to the light transmittance is generated on the flat portion where the pattern of the semi-transmissive film is transferred, and an appropriate exposure amount is determined based on the resist residue. Method.
JP1156463A 1989-06-19 1989-06-19 Resist exposure method Expired - Fee Related JP2624335B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1156463A JP2624335B2 (en) 1989-06-19 1989-06-19 Resist exposure method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1156463A JP2624335B2 (en) 1989-06-19 1989-06-19 Resist exposure method

Publications (2)

Publication Number Publication Date
JPH0321008A JPH0321008A (en) 1991-01-29
JP2624335B2 true JP2624335B2 (en) 1997-06-25

Family

ID=15628300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1156463A Expired - Fee Related JP2624335B2 (en) 1989-06-19 1989-06-19 Resist exposure method

Country Status (1)

Country Link
JP (1) JP2624335B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3462750B2 (en) 1998-05-14 2003-11-05 住友電気工業株式会社 Particulate trap for diesel engine

Also Published As

Publication number Publication date
JPH0321008A (en) 1991-01-29

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