JPH0894724A - Pattern generator for lsi testing device - Google Patents

Abstract

PURPOSE: To easily generate an infinite loop jump pattern by detecting the agreement between an address which is currently being executed and a register LpEND and then determining whether the detection result is valid or not. CONSTITUTION: First, a loop start address and a loop end address are set to a register LpSTA7 and a register LpEND8, respectively, and further a register Modereg 10 is set. With the setting value of the LpSTA7 and LpEND8, an arbitrary address for satisfying LpSTA7<=LpEND8 is set. Then, at the time of starting, the register STA1 is loaded into a counter AP3 and is incremented by one every time a CLK is appled. When the value of the AP3 matches that of the LpEND8, the value of the LpSTA7 is loaded. Namely, by repeating this sort of operation, a loop pattern can be generated infinitely between the LpSTA7 and LpEND8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generator for an LSI test apparatus having a circuit structure capable of easily realizing an infinite loop jump pattern required when measuring the power consumption of a device under test.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing the concept of the circuit configuration of a conventional pattern generator for an LSI test apparatus. (1) First, as a circuit configuration, an N-bit register STA1 for storing a start address for generating a test pattern, a memory STEMmemory6 for storing a test pattern,
A memory VGCMemory4 that stores instructions for generating the address, and a decoder D that decodes the output and creates a control signal for address generation.
It is composed of an EC5, a counter AP3 for generating a memory address by its control signal, and an N-bit multiplexer MUX2 for selecting an address value to be loaded into the counter AP3.

(2) Next, regarding the operation, VGCMem
The ory4 stores an instruction for controlling INC (increment), HOLD (hold), and JUMP (jump) of the counter AP3 and a jump destination address at the time of JUMP, and generates an address of the next cycle by them. . At the start of test pattern generation, the register STA1 is loaded into the counter AP3, the instruction of the address accessed thereby is decoded, and one of INC, HOLD, and JUMP is executed in the next cycle. And in this way, the sequencer V
The GCMemory4 controls the counter AP3, which is an address pointer, and the Vector13, which is a test pattern, is applied to the device under test according to a sequence from the STEMmemory6.

(3) The circuit configuration and operation of pattern generation according to the prior art have been described above. However, in a normal test of the device under test, it is not known that the test pattern generation is an infinite loop jump pattern. No, always end at some address and pass /
It is completed after judging Fail. However, the microcomputer,
When it is desired to measure the amount of power consumed by the ASIC, memory, etc. in the operating state in the test, it is necessary to set the test pattern generation to the infinite loop jump state. Because, in order to measure the power consumption, that is, to measure the power supply current, it takes a time of the order of several tens of ms,
This is because it is necessary to keep the device under test in the same state as the actual operation during that time.

(4) Therefore, if an infinite loop jump pattern is to be generated with the configuration of the conventional pattern generating circuit, the pattern program in the memory VGCMemory4 storing the sequence of the test pattern is rewritten to consume power. It is necessary to prepare separately for measurement. In order to realize the jump function, VG
The CMemory4 needs to have operand data for the address bit width corresponding to the depth direction of the capacity of the STEMmemory6. Alternatively, even if the hardware is implemented by a gate array having a built-in memory, it requires a huge number of cells and a high operation speed, which is not appropriate in terms of cost performance. That is, if the infinite loop jump pattern is generated as it is in the conventional technique, the capacity of the test vector of the device to be measured is rapidly increased from 4M to 8M to 16M words, and (a) a huge amount of pattern data is generated. It takes a long time to rewrite. (B) Similarly, it takes a long time to transfer and compile because of handling such a large pattern. (C) Further, there is a drawback that the pattern generator cannot be speeded up due to the delay of the circuit system passing through the sequencer, the decoder, the counter, the memory and the like.

[0006]

SUMMARY OF THE INVENTION The problem to be solved by the present invention is to provide an infinite loop jump pattern required when measuring the power consumption of an actual device under test using an LSI tester. The purpose is to obtain a circuit configuration of a pattern generator that can easily generate a pattern. That is, in order to obtain an infinite loop jump pattern, it is not necessary to rewrite to a dedicated pattern for that,
It does not take a long time to transfer or compile,
The purpose is to realize a circuit configuration of a pattern generator that can be easily performed at high speed.

[0007]

In order to achieve the above object, in the circuit configuration of the pattern generator of the present invention, J
A register LpSTA for storing the UMP destination address,
Register L that stores the address to execute the JUMP operation
pEND, currently executing address and register Lp
It is composed of a match detection circuit that detects a match with END and a register Modereg that determines whether the detection result is valid or invalid. That is, before starting the test, the loop start address of the register LpSTA, the loop end address of the register LpEND, and the register Modereg for forming an infinite loop jump are set. At the start, the N-bit register STA that stores the address for starting the test pattern generation is first incremented by 1 each time the counter AP is loaded and CLK is applied.
Next, when the value of the counter AP matches the value of the register LpEND, the value of the register LpSTA is changed to the counter A.
Loaded into P. With this repeated operation, the register Lp
Execute endlessly between STA and register LpEND.

[0008]

[Action]

(1) As a set value for the registers LpSTA and LpEND, an arbitrary address that satisfies LpSTA ≦ LpEND is set. (2) With the circuit configuration of the present invention, by controlling with the output signal of the sequencer VGCMemory as in the prior art,
Instead of outputting the pattern in the STEM memory according to the sequence, the start and end of the generation of the infinite loop jump pattern is repeatedly executed between the register LpSTA and the register LpEND, so that it is configured separately from the sequencer and the memory circuit system. It became possible, and it was possible to avoid the problem of delay amount by not rewriting the pattern program instruction, which was the most troublesome thing, and by not using the circuit system at all.

[0009]

1 is a block diagram showing the concept of an embodiment according to the present invention. FIG. 2 is a block diagram showing the concept of another embodiment of the present invention. FIG. 3 likewise shows another alternative embodiment. 4 shows a timing chart of the embodiment of the present invention, and FIG. 5 shows an example of a loop pattern program.

(1) As shown in FIG. 1, in order to generate the infinite loop jump pattern necessary for measuring the power consumption of the device under test in the operating state, in the present invention, the JUMP destination is used. A register LpSTA7 for storing an address, a register LpEND8 for storing an address for executing a JUMP operation, a match detection circuit 9 for detecting a match between an address under execution and an address of the register LpEND8, and whether the detection result is valid or invalid. Register Regreg and register LpSTA that determine
AND gate 11 which issues a signal to be fed back to 7
It is configured to add a circuit consisting of.

(2) As for the operation of the circuit described above, as shown in FIGS. 4 and 5, first, the register LpSTA7 is used.
The loop start address, the loop end address in the register LpEND8, and the register Modelreg.
Set 10 Register LpSTA7 and register L
As the set value of pEND8, an arbitrary address that satisfies LpSTA7 ≦ LpEND8 is set. At the start, the register STA1 is incremented by 1 each time the counter AP3 is loaded and CLK is applied. Counter AP3
When the value of the register matches the value of the register LpEND8,
The value of the register LpSTA7 is loaded into the counter AP3. That is, by repeating such an operation, the register Lp
The loop pattern can now be infinitely executed between the STA7 and the register LpEND8.

(3) In addition, while maintaining the conventional normal test pattern generation function unrelated to the measurement of power consumption, each register is rewritten, and the infinite loop jump pattern is set to the generation mode, and the Modereg 10 is set. By setting it, the control can be switched to the control for generating the required infinite loop jump pattern, so that it becomes possible to measure the power consumption during the operating state of the device under test.

(4) Further, as shown in FIG. 2, as a factor for detecting the coincidence in the coincidence detecting circuit 9, a pattern counter PCNT12 for counting the number of executed patterns is provided instead of the address, and an arbitrary value from the pattern counter PCNT12 is provided. It is also possible to adopt a circuit configuration that is performed by. In that case, the register LpSTA7 is loaded when the pattern counter is cleared at the time of matching detection and reaches an arbitrary value again.

(5) Further, the one shown in FIG. 3 is a combination of the embodiments shown in FIGS.
Set the loop start address in pEND8. The set value is the same as that of the register LpSTA7. Next, D1 of the mode register Modelreg10 is enabled.
D0 remains disabled. Then, the number of patterns forming a loop is set in the register LpEND2.15. When the program is started with the above settings, the register LpEND8 and the counter AP3 are first detected to match, the LpFLAG14 is set, and the pattern counter PCNT12 starts operating. Then N
When the pattern is executed and the value of the register LpEND2 · 15 and the value of the pattern counter PCNT12 match, A
Since the ND gates 2 and 16 are enabled, the register LpSTA7 is loaded in the counter AP3, the pattern counter PCNT12 is cleared at the same time, and the counting operation starts from 0 again. After that, similarly, the program is executed until a match is detected by the match detection circuit 9, and the counter AP3 is returned to the register LpSTA7 again by the match detection, thereby repeating a loop for N patterns from an arbitrary address of the program. You can form a loop to execute.

[0015]

Since the present invention is configured as described above, it has the following effects. That is, in the pattern generator that generates the infinite loop jump pattern necessary when measuring the power consumption of the device under test using the LSI test apparatus in the actual operating state, the circuit configuration of the present invention is used. (1) The normal test pattern and the pattern program instruction can be left as they are, and the work of rewriting to a dedicated pattern for generating the infinite loop jump pattern is not necessary. As a result, data transfer and program compilation are no longer required. (2) Further, since it is possible to control with a simple circuit system including only registers and counters without using a memory, sequencer, or decoder circuit system, high-speed operation is possible and efficient measurement work can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the concept of an embodiment of the present invention.

FIG. 2 is a block diagram showing the concept of another embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 shows a timing chart of an embodiment of the present invention.

FIG. 5 shows an example of a loop pattern program according to an embodiment of the present invention.

FIG. 6 is a block diagram showing the concept of a conventional pattern generator.

[Explanation of symbols]

 1 register STA 2 multiplexer MUX 3 counter AP 4 VGCMemory 5 decoder DEC 6 STEMmemory 7 register LpSTA 8 register LpEND 9 match detection circuit 10 mode register Modereg 11 AND gate 12 pattern counter PCNT 13 Vector 14 LpFLAND 2 register 15 register

Claims (3)

[Claims] 1. A register LpSTA (7) for storing a loop start address of an infinite loop jump, a register LpEND (8) for setting an arbitrary address for executing a jump operation, and a loop start address of the register LpSTA (7). Is started and executed, and the register LpEND
A match detection circuit (9) that detects a match with the arbitrary number of addresses to be executed set in (8), and controls whether the match detection signal is valid or invalid.
Mode register Modereg (10) that issues a feedback signal to TA (7) and AND gate (11)
A pattern generator for an LSI test apparatus, comprising: 2. The coincidence detection circuit (9) does not control by an address from a memory as a factor for performing coincidence detection, but
2. The pattern generator for an LSI test apparatus according to claim 1, wherein the number of executed patterns is controlled by an output signal of a pattern counter PCNT (12) that counts with a clock. 3. The register LpEND according to claim 1.
(8), coincidence detection circuit (9), mode register Mode
reg (10) and the pattern counter P according to claim 2.
An CNT (12) is provided, and the circuit functions according to claim 1 and 2 are combined, and an LpFLAG (14) that can set a flag at an arbitrary position is provided, and an N pattern is generated from an arbitrary address of a program. A pattern generator for an LSI test apparatus, characterized in that a loop for repeatedly executing minutes is formed.