KR20020014527A - Apparatus for supplying rom dump mode in microcontroller - Google Patents

Abstract

PURPOSE: A device for supporting a ROM(Read Only Memory) dump mode of a microcontroller is provided to reduce the ROM test time to a half by outputting doubly a ROM data to a port per one machine cycle. CONSTITUTION: The supporting device of a ROM dump mode comprises a command latch set by a specific command code for fetching ROM data twice in one machine cycle of commands of a microcontroller in the ROM dump mode, and a control circuit part for generating a light control signal controlling the ROM data in an inner bus between S2P1 and S5P2 to be outputted to the ROM data output port. In case of a two bite-one machine cycle command of the 8051 group microcontrollers, the ROM data are fetched twice per one machine cycle. At the ROM dump mode of the 8051 group microcontrollers, the ROM is automatically read out twice like a normal operation by performing only the two bite-one machine cycle command. If the 8051 group microcontroller is set in the ROM dump mode, the command latch is set to 74H.

Description

A device for supporting ROM dump mode of a microcontroller {APPARATUS FOR SUPPLYING ROM DUMP MODE IN MICROCONTROLLER}

The present invention relates to a microcontroller (hereinafter referred to as MCU), and more particularly to an apparatus for supporting a ROM dump mode for verifying whether a user's ROM code is properly recorded in an 8051 series of MCUs.

As is well known, it is very important to test whether your ROM code is properly written to the actual mask ROM in an Application Specific-MCU (ASCU) application. However, as the ROM size continues to grow to 16K, 32K, 64K, etc., the conventional ROM test requires too much test time, and it is important to reduce such test time.

FIG. 1 is a diagram illustrating machine cycles consisting of 12 oscillation clocks (osc.) In an 8051 series of MCUs according to operating periods. FIG. 1 is for the purpose of understanding the prior art and the present invention.

In the ROM dump mode of the 8051 MCU according to the related art, a ROM address is input through two ports (port 1 and port 2) in a reset state, and ROM data of the corresponding address is transferred to port 0 in a machine cycle. Is output via In more detail, the address data input through the port 2 and the port 1 are carried on an internal bus in the 'S6P1' section and the 'S1P1' section of FIG. 1, respectively, and transferred to the program counter. The updated PC value is then sampled by the ROM controller in the 'S2P2' section of the machine cycle, decoded in the 'S3P2' section, and the ROM data of the corresponding address is outputted to the 'S4P2'. The output ROM data is loaded on the internal bus at 'S5P1' and is output through port 0 at 'S5P2' section.

As a result, the ROM dump mode of the 8051 MCU according to the related art requires a lot of test time for the entire ROM test by outputting only one ROM data per port in one machine cycle. As an example, a 32K ROM test requires a time (393,216 oscillation clocks) for the '32K x 12 oscillation clock'. As a result, ROM testing is a heavy burden on AS-MCUs that require quick response. In addition, since the PC increment does not work, there is a problem that needs to be tested separately.

The present invention has been made to solve the above problems, the device for supporting the ROM dump mode of the microcontroller, which can reduce the ROM test time by half by outputting the ROM data twice in one machine cycle The purpose is to provide.

1 is a diagram illustrating a machine cycle consisting of 12 oscillation clocks (osc.) Divided by operation periods in an 8051 series of MCUs.

2A is a conventional instruction latch circuit diagram.

2B is a circuit diagram of an instruction latch in accordance with an embodiment of the present invention.

3A is a circuit diagram of a conventional Port 0 controller.

3B is a circuit diagram of a port 0 controller according to an embodiment of the present invention.

* Description of the main parts of the drawing

100, 110: unit latch portion 101: negative logic gate

111, 240: negative logical gate 102, 112: latch

200, 220: AND gate 210, 230: AND gate

250: multiplexer

In order to achieve the above object, the present invention provides a device for supporting a ROM dump mode of a microcontroller, wherein the ROM dump mode includes a specific instruction code for fetching ROM data twice in one machine cycle of the microcontroller's instructions. An instruction latch being set; And a control circuit unit configured to generate a write control signal for controlling the ROM data output on the internal bus to the ROM data output port in an interval between S2P1 and S5P1 of the machine cycle.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

The present invention utilizes the fact that two bytes of 8051 instructions fetch ROM data twice in one machine cycle in the case of one machine cycle instruction. Only machine cycle instructions) are used to automatically read the ROM twice, as in normal operation. To do this, when the 8051 enters ROM dump mode, the instruction latch is held at '74H'.

Here, the '74H' instruction is one machine cycle instruction as 'MOV A, #data', and reads the ROM twice to fetch the operation code (Opcode) and data. To this end, unlike the conventional instruction latch shown in Figure 2a is configured as shown in Figure 2b.

2B is a circuit diagram of an instruction latch in accordance with an embodiment of the present invention.

Referring to FIG. 2B, the instruction latch of the present invention receives each bit into two types of unit latch units 100 and 110 in order to latch an 8-bit instruction X from an internal bus. Each of the 110 latches the command in response to the mode signal tmd and the command write clock inst_wr indicating the ROM dump mode. At this time, the mode signal tmd is a signal enabled with '1' in the ROM dump mode.

In detail, the unit latch unit 100 receives an arbitrary logic bit and a mode signal tmd of an 8-bit command X, and negates the negative latch gate 101 and the instruction write clock inst_wr. The latch 102 is configured to latch and output the output of the OR gate 101, and the output is fixed to '1' in the ROM dump mode.

On the other hand, the unit latch unit 110 receives a random bit of the 8-bit command (X) and the inverted mode signal tmd and responds to the negative logical gate 111 and the command write clock inst_wr that perform negative logic multiplication. The latch 112 is configured to latch and output the output of the negative logic gate 111, and the output is fixed to '0' in the ROM dump mode.

Therefore, in order to fix the output of the instruction latch to '74H', that is, '01110100B' in the ROM dump mode as described above, the instruction latch according to the embodiment of the present invention is a unit latch in order from the most significant bit to the least significant bit. Unit 110, unit latch unit 100, unit latch unit 100, unit latch unit 100, unit latch unit 110, unit latch unit 100, unit latch unit 110, unit latch unit 110 '.

As a result, the 8051 MCU always executes a '74H' command in the ROM dump mode through the instruction latch illustrated in FIG. 2B. At this time, the PC continues to be incremented so that the data of the entire ROM region is read in sequence from address 0.

Meanwhile, in the 8051 normal operation, the timing of loading ROM data onto the internal bus is 'S2P1' and 'S5P1'. And on the internal bus at 'S5P1'. Therefore, in order to output the ROM data of the bus to port 0, the conventional port 0 controller must be modified.

3B is a circuit diagram of a port 0 controller according to an embodiment of the present invention. FIG. 3A illustrates a conventional port 0 controller circuit in comparison with the conventional art.

Referring to FIG. 3B, the port 0 controller of the present invention receives an active control signal (V_romrd) in the ROM dump mode and a signal S5 representing the 'S5' section of a machine cycle, and logically gates 200 and S5. And the OR gate 210 for ORing the signal S2 representing the 'S2' section of the machine cycle, the AND gate 220 for ANDing the output of the OR gate 210 and the mode signal tmd, and two AND gates ( An OR gate 230 for ORing the signals output from the signals 200 and 220 respectively, an AND logic gate 240 for negative logic multiplying the output of the OR gate 230 with a signal P1 representing a 'P1' section of the machine cycle, and control. In response to the result of the OR of the signal V_romrd and the mode signal tmd, the output of the write enable signal P0_sfr_wr for the port 0 or the negative logic gate 240 is converted into the write signal P0_wr for the port 0. Output multiplexer (2 50).

Here, the write enable signal P0_sfr_wr is a signal for writing to the port 0 when the control signal V_romrd is disabled.

As a result, a simple circuit change of the instruction latch of FIG. 2B and the port 0 control unit of FIG. 3B to support the ROM dump mode can implement a ROM dump mode twice as fast as the conventional one, and it cannot be tested in the conventional ROM dump mode. Verify the functionality of PC Increments.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, the ROM data is loaded in one machine cycle by automatically reading the ROM twice as in the normal operation by performing only a specific instruction (ie, 2 bytes-1 machine cycle instruction) in the 8051 ROM dump mode. It can output to two ports, reducing the overall test time by 1/2 compared to the conventional method.

Claims (5)

In the device for supporting the ROM dump mode of the microcontroller, An instruction latch set to a code of a specific instruction that fetches ROM data twice in one machine cycle of the microcontroller's instructions in the ROM dump mode; And Control circuit unit for generating a write control signal for controlling to output the ROM data on the internal bus to the ROM data output port in the 'S2P1' and 'S5P1' period of the machine cycle Device comprising a. The method of claim 1, wherein the instruction latch, And a plurality of first and second unit latches each latching a plurality of bit commands from the internal bus by one bit in response to a mode signal indicating the ROM dump mode and a command write clock. The first unit latch unit, Negative logic sum means for receiving a negative logic sum of any one bit of the command and the mode signal; And An output is set to '1' in the ROM dump mode including a first latch configured to latch and output an output of the negative logic means in response to the command write clock, The second unit latch unit, Negative logical product means for receiving a negative signal and an inverted mode signal of any one of the instructions; And And a second latch configured to latch and output an output of the negative logical means in response to the command write clock, wherein the output is set to '0' in the ROM dump mode. The method of claim 1 or 2, wherein the instruction latch, The device is set to '74H' in the ROM dump mode. The method of claim 3, wherein the instruction latch, When the command is 8 bits, the second unit latch unit, the three first unit latch units, and the second unit in order from the most significant bit to the least significant bit to set the output to '74H' in the ROM dump mode. And a unit latch unit, the first unit latch unit, and the second unit latch unit. The method of claim 1, wherein the control circuit unit, First logical multiplication means for receiving and multiplying a first control signal that is activated in the ROM dump mode and a first interval control signal representing an interval of 'S5' of the machine cycle; First logical OR means for receiving and ORing the first interval control signal and a second interval control signal representing an 'S2' interval of the machine cycle; Second logical AND means for receiving and outputting the output of the first AND unit and a mode signal indicating the ROM dump mode; Second logical OR means for ORing the signals output from the first and second logical product means, respectively; Negative logic means for negatively multiplying a third interval control signal indicative of a 'P1' interval of the machine cycle and the output of the second AND logic means; And Third logical sum means for ORing the first control signal and the mode signal; Selection means for outputting the write enable signal to the ROM data output port or the output of the negative logical product as a write signal to the ROM data output port in response to the output of the third logical sum means; Device comprising a.