JPH0883886A - Fabrication of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To enhance the reliability of a semiconductor integrated circuit device by forming a semiconductor in an element forming region on the major surface of a semiconductor substrate through extended impurity diffusion thereby suppressing fluctuation in the resistance of a resistive element. CONSTITUTION: An impurity introduction mask 5A for defining the width W1 of element forming region is formed on the major surface of a semiconductor substrate 1 through a buffer insulation layer. A resistor element R is then formed of a p<+> -type semiconductor region 6A which is formed in an element forming region on the major surface of the semiconductor substrate 1 defined by the impurity introduction mask 5A. The p<+> -type semiconductor region 6A is connected electrically, on one end side thereof, with a wiring 8A through a contact hole 7A made through the interlayer insulation film 7. A wiring 8B is formed on the other side of the p<+> -type semiconductor region 6A through a contact hole 7B made through the interlayer insulation film 7. Resistance of the p<+> -type semiconductor region 6A can be controlled freely and accurately by controlling the quantity of impurity being introduced therein.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly, it is applied to a semiconductor integrated circuit device having a resistance element formed of a semiconductor region formed in an element formation region of a main surface of a semiconductor substrate. It relates to effective technology.

[0002]

2. Description of the Related Art As a semiconductor integrated circuit device, for example, a semiconductor integrated circuit device having an analog circuit and a digital circuit is known. In this type of semiconductor integrated circuit device, a plurality of resistance elements are mounted.

The resistance element is composed of a semiconductor region formed in the element formation region of the main surface of the semiconductor substrate. The resistance element composed of this semiconductor region is generally formed by the following manufacturing method.

First, a field insulating film (silicon oxide film) that defines the periphery of the element formation region on the main surface of the semiconductor substrate is formed by using the selective oxidation technique. Next, impurities are introduced into the element formation region of the main surface of the semiconductor substrate whose periphery is defined by the field insulating film in self-alignment with the field insulating film. The impurities are introduced by, for example, an ion implantation method. Next, the impurities are stretched and diffused to form a semiconductor region in the element formation region on the main surface of the semiconductor substrate. The semiconductor region is formed in self-alignment with the field insulating film.

In the resistance element thus constructed, the resistance value can be freely controlled with high accuracy by controlling the introduction amount of impurities.

[0006]

In the semiconductor integrated circuit device, the resistance width of the resistance element is defined by the area width of the semiconductor area. The dimensional accuracy of the region width of the semiconductor region is determined by the dimensional accuracy of the field insulating film that defines the region width of the element formation region on the main surface of the semiconductor substrate. However,
Since the field insulating film is formed by the selective oxidation technique with low processing accuracy, the dimensional accuracy of the region width of the semiconductor region formed in self alignment with the field insulating film is low. For this reason, the region width of the semiconductor region varies, so that the resistance value of the resistance element fluctuates, and the reliability of the semiconductor integrated circuit device deteriorates.

An object of the present invention is to provide a semiconductor integrated circuit device having a resistance element formed of a semiconductor region formed in an element formation region of a main surface of a semiconductor substrate, suppressing variation in the resistance value of the resistance element, It is an object of the present invention to provide a technique capable of increasing the reliability of an integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

In a method of manufacturing a semiconductor integrated circuit device having a resistance element formed of a semiconductor region formed in an element forming region of a main surface of a semiconductor substrate, a semiconductor substrate having a uniform film thickness is formed on the main surface of the semiconductor substrate. Forming a polycrystalline silicon film, and patterning the polycrystalline silicon film by an anisotropic etching technique to form an impurity introduction mask that defines the region width of the element formation region of the main surface of the semiconductor substrate. And a step of introducing an impurity into the element formation region of the main surface of the semiconductor substrate in a self-aligned manner with respect to the impurity introduction mask, and an impurity on the main surface of the semiconductor substrate subjected to a diffusion process. Forming a semiconductor region in the formation region.

[0011]

According to the above-mentioned means, since the anisotropic etching technique for patterning a polycrystalline silicon film has higher processing accuracy than the selective oxidation technique, the area width of the element forming region on the main surface of the semiconductor substrate is reduced. The dimensional accuracy of the specified impurity introduction mask can be improved. As a result, the dimensional accuracy of the region width of the semiconductor region formed in self-alignment with the impurity introduction mask can be increased, so that fluctuations in the resistance value of the resistance element can be suppressed and the reliability of the semiconductor integrated circuit device can be reduced. You can improve your sex.

[0012]

EXAMPLES The structure of the present invention will be described below with reference to examples. In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and repeated description thereof will be omitted.

(Embodiment 1) Embodiment 1 is a first embodiment of the present invention in which the present invention is applied to a semiconductor integrated circuit device. A schematic configuration of a semiconductor integrated circuit device that is Embodiment 1 of the present invention is shown in FIG. 1 (plan view of a main part), FIG. 2 (cross-sectional view taken along the line AA shown in FIG. 1) and FIG. (A cross-sectional view taken along the line BB).

As shown in FIGS. 1, 2 and 3, the semiconductor integrated circuit device is mainly composed of a semiconductor substrate 1. The semiconductor substrate 1 is formed of, for example, a p-type semiconductor substrate made of single crystal silicon.

A resistance element R is formed on the main surface of the semiconductor substrate 1. The resistance element R is used as a constituent element of an A / D converter that performs analog processing, for example. An n-type well region 2 is formed on the main surface of the semiconductor substrate 1 on which the resistance element R is formed.

The resistance element R is formed on the main surface of the semiconductor substrate 1 whose periphery is defined by the field insulating film 3. The field insulating film 3 is formed of a silicon oxide film formed by a known selective oxidation method.

A semiconductor substrate 1 is formed on the main surface of the semiconductor substrate 1 (n-type well region 2) with a buffer insulating film 4 interposed therebetween.
An impurity introduction mask 5A that defines the region width W ₁ of the element formation region on the main surface is formed. Impurity introduction mask 5A
Is formed by patterning a polycrystalline silicon film having a uniform film thickness by an anisotropic etching technique.

The resistance element R comprises a p + type semiconductor region 6A. The p + type semiconductor region 6A is formed in the element forming region of the main surface of the semiconductor substrate 1 (n type well region 2) defined by the impurity introduction mask 5A. p + type semiconductor region 6A
Is formed by introducing p-type impurities into the main surface of the semiconductor substrate 1 in a self-aligned manner with respect to the impurity introduction mask 5A, and then subjecting the p-type impurities to a diffusion process.
That is, the region width W ₂ of the p + type semiconductor region 6A is defined by self-alignment with the impurity introduction mask 5A that defines the region width W ₁ of the element forming region of the main surface of the semiconductor substrate 1. The region width W ₂ of the p + type semiconductor region 6A defines the resistance width of the resistance element.

A wiring 8A is electrically connected to one end of the p + type semiconductor region 6A through a connection hole 7A formed in the interlayer insulating film 7. A wiring 8B is formed on the other end side of the p + type semiconductor region 6A through a connection hole 7B formed in the interlayer insulating film 7. The distance L between the connection hole 7A and the connection hole 7B defines the effective resistance length of the resistance element R.

In the resistance element R thus constructed, the resistance value can be freely controlled with high accuracy by controlling the amount of impurities introduced into the p + type semiconductor region 6A.

Next, a method of manufacturing the semiconductor integrated circuit device will be described with reference to FIGS. 4 to 7 (cross-sectional views for explaining the manufacturing method).

First, a semiconductor substrate 1 formed of a p-type semiconductor substrate is prepared.

Next, an n-type impurity is selectively introduced into the main surface of the semiconductor substrate 1 to form an n-type well region 2.

Next, a field insulating film 3 is formed on the element isolation region on the main surface of the semiconductor substrate 1. The field insulating film 3 is formed of a silicon oxide film formed by a known selective oxidation method.

Next, a buffer insulating film 4 is formed on the main surface of the semiconductor substrate 1 whose periphery is defined by the field insulating film 3. The buffer insulating film 4 is formed of, for example, a thermal silicon oxide film.

Next, as shown in FIG. 4, a polycrystalline silicon film 5 having a uniform film thickness is formed on the main surface of the semiconductor substrate 1. The polycrystalline silicon film 5 is deposited by the CVD method, for example.

Next, the polycrystalline silicon film 5 is patterned by an anisotropic etching technique, and as shown in FIG.
An impurity introduction mask 5A that defines the region width W ₁ of the element formation region on the main surface of the semiconductor substrate 1 is formed. Since the anisotropic etching technology has higher processing accuracy than the selective oxidation technology,
It is possible to improve the dimensional accuracy of the impurity introduction mask 5A that defines the region width W ₁ of the element formation region on the main surface of the semiconductor substrate 1.

Then, the p-type impurity 6 is introduced into the element formation region of the main surface of the semiconductor substrate 1 defined by the impurity introduction mask 5A in self-alignment with the impurity introduction mask 5A. The p-type impurity is introduced by, for example, an ion implantation method.

Next, the p-type impurity 6 is stretched and diffused to form an element formation region on the main surface of the semiconductor substrate 1.
A p + type semiconductor region 6A is formed. This p + type semiconductor region 6
The dimensional accuracy of the region width W ₂ of A is determined by the dimensional accuracy of the impurity introduction mask 5A that defines the region width W ₁ of the element forming region of the main surface of the semiconductor substrate 1.

Next, an interlayer insulating film 7 is formed on the entire main surface of the semiconductor substrate 1. The interlayer insulating film 7 is, for example, CVD.
It is formed of a silicon oxide film formed by the method.

Next, a connection hole 7A and a connection hole 7B that define the effective resistance length of the resistance element R are formed in the interlayer insulating film 7.

Next, a wiring material is formed on the entire main surface of the interlayer insulating film 7. The wiring material is formed of, for example, an aluminum film or an aluminum alloy film.

Next, the wiring material is patterned, and the wiring 8A is connected to one end side of the p + type semiconductor region 6A through the connection hole 7A, and is connected to one end side of the p + type semiconductor region 6A through the connection hole 7B. By forming each of the wirings 8B, as shown in FIGS. 1, 2 and 3, the resistance element R formed of the p + type semiconductor region 6A formed in the element formation region of the main surface of the semiconductor substrate 1 is formed. Complete.

As described above, in the method of manufacturing a semiconductor integrated circuit device having the resistance element R formed of the semiconductor region 6A formed in the element formation region of the main surface of the semiconductor substrate 1,
A step of forming a polycrystalline silicon film 5 having a uniform film thickness on the main surface of the semiconductor substrate 1; and a step of patterning the polycrystalline silicon film 5 by an anisotropic etching technique. A step of forming an impurity introduction mask 5A that defines the region width W ₁ of the element formation region of the main surface, and the impurity introduction mask 5 in the element formation region of the main surface of the semiconductor substrate 1.
A step of introducing the p-type impurity 6 in self-alignment with A,
And p-type semiconductor regions 6A are formed in the element formation region of the main surface of the semiconductor substrate 1 by subjecting the p-type impurities to a diffusion process. As a result, the polycrystalline silicon film 5
Since the anisotropic etching technique for patterning the substrate has a higher processing accuracy than the selective oxidation technique, the dimensional accuracy of the impurity introduction mask 5A that defines the region width W ₁ of the element forming region of the main surface of the semiconductor substrate 1 can be improved. Can be increased. As a result, the dimensional accuracy of the region width of the semiconductor region 6A formed in self-alignment with the impurity introduction mask 5A can be increased, so that the resistance value of the resistance element R can be suppressed from varying, and the semiconductor integrated circuit can be suppressed. The reliability of the device can be increased.

Further, since the impurity introduction mask 5A is formed with a uniform film thickness, the introduction depth of the p-type impurity 6 introduced in self-alignment with the impurity introduction mask 5A can be made constant. The width of the p + type semiconductor region 6A W ₂
The dimensional accuracy of can be improved. As a result, fluctuations in the resistance value of the resistance element R can be suppressed, and the reliability of the semiconductor integrated circuit device can be improved.

(Embodiment 2) Embodiment 2 is a second embodiment of the present invention in which the present invention is applied to a semiconductor integrated circuit device. A schematic configuration of a semiconductor integrated circuit device that is Embodiment 2 of the present invention is shown in FIG. 8 (plan view of relevant parts) and FIG.

As shown in FIGS. 8 and 9, the semiconductor integrated circuit device mainly comprises a semiconductor substrate 1 formed of a p-type semiconductor substrate made of, for example, single crystal silicon.

A p channel M is formed on the main surface of the semiconductor substrate 1.
ISFET (M etal I nsulator S emiconductor F iel
d E ffect T tansistor) Qp and the resistor R1, the resistor element R2, the resistance element R3 is formed. An n-type well region 2 is formed on the main surface of a semiconductor substrate 1 on which these elements are formed.

The p-channel MISFET Qp and the resistance elements R1, R2, R3 are formed on the main surface of the semiconductor substrate 1 whose periphery is defined by the field insulating film. The field insulating film 3 is formed of a silicon oxide film formed by a known selective oxidation method.

The p-channel MISFET Qp has an n-type structure in the region defined by the field insulating film 3.
It is formed on the main surface of the mold well region 2. That is, the p-channel MISFET Qp is mainly composed of the n-type well region (channel forming region) 2, the gate insulating film 4, the gate electrode 5B, and the pair of p + -type semiconductor regions 6B which are the source region and the drain region. The wirings 8C are electrically connected to the pair of p + type semiconductor regions 6B, which are the source region and the drain region, respectively, through the connection holes 7C formed in the interlayer insulating film 7.

The resistance element R1 is a p + type semiconductor region 6A ₁
Composed of. The p + type semiconductor region 6A ₁ is formed in the element forming region of the main surface of the semiconductor substrate 1 defined by the impurity introduction mask 5A. The resistance element R2 is a p + type semiconductor region 6
It is composed of A ₂ . The p + type semiconductor region 6A ₂ is formed in the element forming region of the main surface of the semiconductor substrate 1 defined by the impurity introduction mask 5A. The resistance element R3 is composed of the p + type semiconductor region 6A ₃ . The p + type semiconductor region 6A ₃ is formed in the element forming region of the main surface of the semiconductor substrate 1 defined by the impurity introduction mask 5A. These p + type semiconductor regions 6A ₁ , p + type semiconductor regions 6A ₂ and p + type semiconductor regions 6A ₃
Are formed by the method for manufacturing the semiconductor integrated circuit device shown in the first embodiment. That is, the p + type semiconductor region 6A
The dimensional accuracy of the region width W ₂ of each of the p ₁ , p + type semiconductor region 6A ₂ and the p + type semiconductor region 6A ₃ is determined by the impurity introduction mask 5A which defines the region width W ₁ of the element forming region of the main surface of the semiconductor substrate 1. It is determined by the dimensional accuracy of.

The p + type semiconductor region 6A ₁ is separated from the p + type semiconductor region 6A ₂ by the impurity introduction mask 5A. The p + type semiconductor region 6A ₂ is separated from the p + type semiconductor region 6A ₃ by the impurity introduction mask 5A. The p + type semiconductor region 6A ₃ is separated from one p + type semiconductor region 6B of the p channel MISFET Qp by the impurity introduction mask 5A. That is, the impurity introduction mask 5A defines the region width W ₂ of the element forming region on the main surface of the semiconductor substrate 1, and at the same time, the semiconductor substrate 1 is formed.
P + type semiconductor region 6A formed in the element forming region of the main surface of
Separate the spaces.

The impurity introducing mask 5A is fixed to the power supply potential so that the channel called MISFET is not formed in the n-type well region 2 immediately below. Since each of the resistance elements R1, R2, and R3 of this embodiment is composed of a p + type semiconductor region, the impurity introduction mask 5A is set to the operating potential.
It is fixed at (Vcc).

As described above, the p + type semiconductor region 6A ₁ , the p + type semiconductor region 6A ₂ and the p + type semiconductor region 6A ₃ are formed by the manufacturing method shown in the first embodiment, and thus the p + type semiconductor region 6A is formed. _Since the dimensional accuracy of the region width W ₂ of each of the p + type semiconductor region 6A ₂ and the p + type semiconductor region 6A ₃ can be improved, the fluctuation of the resistance value of each of the resistance element R1, the resistance element R2, and the resistance element R3 can be improved. Can be suppressed, and the reliability of the semiconductor integrated circuit device can be improved.

The p + type semiconductor region 6A ₁ , the p + type semiconductor region 6A ₂ , the p + type semiconductor region 6A ₃ and the p + type semiconductor region 6 are also included.
By separating each of B by the impurity introduction mask 6A, the occupied area of the separation region can be reduced as compared with the case of separating by the field insulating film 3, so that the integration degree of the semiconductor integrated circuit device can be improved. it can.

(Embodiment 3) Embodiment 3 is a second embodiment of the present invention in which the present invention is applied to a semiconductor integrated circuit device. A schematic configuration of a semiconductor integrated circuit device which is Embodiment 3 of the present invention is shown in FIG. 10 (plan view of relevant parts).

As shown in FIG. 10, the semiconductor integrated circuit device is mainly composed of a semiconductor substrate 1 formed of a p-type semiconductor substrate made of, for example, single crystal silicon. This semiconductor substrate 1
A plurality of resistance elements R are formed on the main surface of.

Each of the plurality of resistance elements R is formed on the main surface of the semiconductor substrate 1 whose periphery is defined by the field insulating film 3. An impurity introduction mask 5A formed in a matrix is formed on the main surface of the semiconductor substrate 1 whose periphery is defined by the field insulating film 3.

Each of the plurality of resistance elements R is composed of a p + type semiconductor region 6A. Each of the p + type semiconductor regions 6A is formed in the element formation region of the main surface of the semiconductor substrate 1 defined by the matrix-shaped impurity introduction mask 5A.
Each of these p + type semiconductor regions 6A is formed by the method of manufacturing the semiconductor integrated circuit device described in the first embodiment. In other words, the dimensional accuracy of the region width W ₂ of each of the p + type semiconductor regions 6A depends on the region width W ₁ of the element forming region on the main surface of the semiconductor substrate _1.
Is determined by the dimensional accuracy of the matrix-shaped impurity introduction mask 5A that defines

As described above, by forming each of the p + type semiconductor regions 6A by the manufacturing method shown in the first embodiment,
Since the dimensional accuracy of the region width W ₂ of each of the p + type semiconductor regions 6A can be increased, it is possible to suppress the variation in the resistance value of each of the plurality of resistance elements, and to improve the reliability of the semiconductor integrated circuit device. it can.

Further, by separating each of the p + type semiconductor regions 6A by the matrix-like impurity introducing mask 6A, the occupied area of the separation region can be reduced as compared with the case of separating by the field insulating film 3. The integration degree of the semiconductor integrated circuit device can be increased.

(Embodiment 4) Embodiment 4 is a fourth embodiment of the present invention in which the present invention is applied to a semiconductor integrated circuit device. A schematic configuration of a semiconductor integrated circuit device according to a fourth embodiment of the present invention is shown in FIG. 11 (plan view of relevant parts), FIG. 12 (cross-sectional view taken along the line D-D shown in FIG. 11) and FIG. (A cross-sectional view taken along the line E-E).

As shown in FIGS. 11, 12 and 13,
The semiconductor integrated circuit device is mainly composed of a semiconductor substrate 1 formed of a p-type semiconductor substrate made of, for example, single crystal silicon. A resistance element R is formed on the main surface of the semiconductor substrate 1. On the main surface of the semiconductor substrate 1 on which the resistance element R is formed, n
The mold well region 2 is formed.

The resistance element R is formed on the main surface of the semiconductor substrate 1 whose periphery is defined by the field insulating film 3. The field insulating film 3 is formed of a silicon oxide film formed by a known selective oxidation method.

A buffer insulating film 4 is formed on the main surface of the semiconductor substrate 1 (n-type well region 2) whose periphery is defined by the field insulating film 3. The buffer insulating film 4 is formed of, for example, a thermal silicon oxide film and has a thickness of, for example, 15 to 25 [n.
The film thickness is about m].

On the main surface of the buffer insulating film 4, an impurity introduction mask 5A for defining the area width W ₁ of the element forming area of the main surface of the semiconductor substrate 1 is formed. Further, on the main surface of the buffer insulating film 4, a mask 5C ₁ used as an impurity introduction mask and as an extraction wiring,
Each of the masks 5C ₂ is formed. Each of the impurity introduction mask 5A, the mask 5B ₁ and the mask 5B ₂ has a uniform film thickness and is patterned by an anisotropic etching technique on a polycrystalline silicon film into which an impurity for reducing a resistance value is introduced. It is formed by applying. That is, the impurity introduction mask 5A, the mask 5B ₁ , and the mask 5B ₂ are formed in the same process.

The resistance element R is a p + type semiconductor region 6A, p +
Each of the type semiconductor regions 9A and the p + type semiconductor regions 9B is formed.

The p + type semiconductor region 6A is formed in the element forming region of the main surface of the semiconductor substrate 1 (n type well region 2) defined by the impurity introducing mask 5A. The p + type semiconductor region 6A is formed by the method for manufacturing the semiconductor integrated circuit device described in the first embodiment. That is, the p + type semiconductor region 6A
The dimensional accuracy of the region width W ₂ of the impurity introduction mask 5 that defines the region width W ₁ of the element formation region of the main surface of the semiconductor substrate 1
It is determined by the dimensional accuracy of A.

Each of the p + type semiconductor region 9A and the p + type semiconductor region 9B is formed in the element forming region of the main surface of the semiconductor substrate 1 defined by the impurity introduction mask 5A. One end of the mask 5C ₁ is electrically connected to the p + type semiconductor region 9A through the connection hole 4A formed in the buffer insulating film 4, and the p + type semiconductor region 9B is connected through the connection hole 4B formed in the buffer insulating film 4. One end of the mask 5C ₂ is electrically connected.

The p + type semiconductor region 9A has a mask 5C ₁
Is formed by diffusing the p-type impurity introduced into the element forming region of the main surface of the semiconductor substrate 1, and is electrically connected to one end side of the p + type semiconductor region 6A. p + type semiconductor region 9
B is formed by diffusing the p-type impurities introduced into the mask 5C ₂ into the element formation region of the main surface of the semiconductor substrate 1, and is electrically connected to the other end side of the p + -type semiconductor region 6A. The diffusion of the p-type impurities introduced into each of the mask 5C ₁ and the mask 5C ₂ is performed by a process of extending and diffusing the p-type impurities introduced by self-alignment with the impurity introduction mask 5A (p + type semiconductor region). 6A forming step).

The other end of the mask 5C ₁ is drawn out from the element forming region of the main surface of the semiconductor substrate 1 onto the field insulating film 3. A wiring 8A is electrically connected to the other end of the mask 5C ₁ through a connection hole 7A formed in the interlayer insulating film 7. That is, one end side of the p + type semiconductor region 6A is electrically connected to the wiring 8A via the p + type semiconductor region 9A and the mask 5C ₁ . The interlayer insulating film 7 is formed of, for example, a silicon oxide film formed by a CVD method and has a film thickness of, for example, about 1 [μm].

The other end of the mask 5C ₂ is the semiconductor substrate 1
Of the main surface of the element formation region on the field insulating film 3. A wiring 8B is electrically connected to the other end of the mask 5C ₂ through a connection hole 7A formed in the interlayer insulating film 7. That is, the other end of the p + type semiconductor region 6A is electrically connected to the wiring 8B via the p + type semiconductor region 9B and the mask 5C ₂ .

The effective resistance length of the resistance element R is the connection hole 4A.
Is defined by the distance L between the contact hole and the connection hole 4B. Connection hole 4
Each of A and the connection hole 4B is formed by patterning the buffer insulating film 4 by an anisotropic etching technique. In this patterning process, the connection holes 4A,
The connection hole 4B is slightly side-etched. The side etching amount increases in proportion to the film thickness of the insulating film forming the connection hole. However, since the connection hole 4A and the connection hole 4B of this embodiment are each formed in the buffer insulating film 4 having a smaller film thickness than the interlayer insulating film 7, the side etching amount during patterning is small. . That is, the connection hole 4 that defines the effective resistance length of the resistance element R
The dimensional accuracy of the distance L between A and the connection hole 4B can be increased.

As described above, by forming the p + type semiconductor region 6A by the method for manufacturing the semiconductor integrated circuit device shown in the first embodiment, the dimensional accuracy of the region width W ₂ of the p + type semiconductor region 6A can be improved. Therefore, fluctuations in the resistance value of the resistance element R can be suppressed, and the reliability of the semiconductor integrated circuit device can be improved.

Further, by forming each of the connection hole 4A and the connection hole 4B which define the substantial resistance length of the resistance element in the buffer insulating film 4, the distance L between the connection hole 4A and the connection hole 4B can be reduced. Since the dimensional accuracy can be improved, fluctuations in the resistance value of the resistance element R can be suppressed, and the reliability of the semiconductor integrated circuit device can be improved.

As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to a semiconductor integrated circuit device composed of a semiconductor substrate in which an epitaxial layer is laminated on the main surface of a semiconductor substrate by an epitaxial growth method.

[0068] Further, the present invention includes a semiconductor substrate main surface on an insulating film interposed in a so-called SOI formed by laminating semiconductor substrate of monocrystalline silicon (S ilicon O n I nsu consisting of a single crystal silicon
The present invention can be applied to a semiconductor integrated circuit device including a semiconductor substrate having a (lator) structure.

[0069]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

In a semiconductor integrated circuit device having a resistance element formed of a semiconductor region formed in the element formation region of the main surface of a semiconductor substrate, fluctuations in the resistance value of the resistance element are suppressed, and the reliability of the semiconductor integrated circuit device is improved. Increase.

[Brief description of drawings]

FIG. 1 is a plan view of a main part of a semiconductor integrated circuit device that is Embodiment 1 of the present invention.

FIG. 2 is a cross-sectional view taken along the line AA shown in FIG.

3 is a cross-sectional view taken along the line BB of FIG.

FIG. 4 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 5 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 6 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 7 is a sectional view for explaining the method for manufacturing the semiconductor integrated circuit device.

FIG. 8 is a plan view of a main portion of a semiconductor integrated circuit device that is Embodiment 2 of the present invention.

9 is a cross-sectional view taken along the line CC of FIG.

FIG. 10 is a plan view of a principal portion of a semiconductor integrated circuit device that is Embodiment 3 of the present invention.

FIG. 11 is a plan view of essential parts of a semiconductor integrated circuit device which is Embodiment 4 of the present invention.

12 is a cross-sectional view taken along the line D-D shown in FIG.

13 is a cross-sectional view taken along the line EE shown in FIG.

[Explanation of symbols]

1 ... Semiconductor substrate, 2 ... N-type well region, 3 ... Field insulating film, 4 ... Buffer insulating film (gate insulating film), 4A, 4
B ... connection hole, 5 ... polycrystalline silicon film, 5A ... impurity introducing mask, 5B ... gate electrode, 5C _1, 5C ₂ ... mask, 6
... p-type impurities, 6A, 6B ... p + type semiconductor region, 7 ... interlayer insulating film, 7A, 7B, 7C ... connection holes, 8A, 8B, 8C
... Wiring, 9A, 9B ... P + type semiconductor region, R ... Resistance element,
Qp ... p channel MISFET.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/265 H01L 21/265 S

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device having a resistance element formed of a semiconductor region formed in an element forming region of a main surface of a semiconductor substrate, wherein a uniform film thickness is provided on the main surface of the semiconductor substrate. A step of forming the formed polycrystalline silicon film, and a mask for introducing impurities for patterning the polycrystalline silicon film by an anisotropic etching technique to define a region width of an element formation region of the main surface of the semiconductor substrate. And a step of introducing impurities into the element formation region of the main surface of the semiconductor substrate in a self-aligned manner with respect to the impurity introduction mask; And a step of forming a semiconductor region in the element forming region. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the semiconductor region is separated from other semiconductor regions by an impurity introduction mask. 3. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the impurity introduction mask is formed in a matrix.