JPH0883662A - Manufacture of super-micro connector - Google Patents

Manufacture of super-micro connector

Info

Publication number
JPH0883662A
JPH0883662A JP28549794A JP28549794A JPH0883662A JP H0883662 A JPH0883662 A JP H0883662A JP 28549794 A JP28549794 A JP 28549794A JP 28549794 A JP28549794 A JP 28549794A JP H0883662 A JPH0883662 A JP H0883662A
Authority
JP
Japan
Prior art keywords
insulator
conductor
wire
exposed
conductive wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28549794A
Other languages
Japanese (ja)
Inventor
Keisuke Furusawa
圭輔 古沢
Hisao Orimo
尚夫 折茂
Takuya Suzuki
卓哉 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP28549794A priority Critical patent/JPH0883662A/en
Publication of JPH0883662A publication Critical patent/JPH0883662A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

Landscapes

  • Manufacturing Of Electrical Connectors (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To provide a method for producing a super-micro connector of high connectability and reliability, allowing good connection state via the restraint of a connection defect with a semiconductor chip or a circuit board electrode. CONSTITUTION: A plurality of conductors 2 substantially arranged in parallel are fixed with an elastic insulator 3 laid in the gap thereof and a complex structure formed out of the conductors 2 and the insulator 3 is thereby prepared. Then, the structure 4 is cut along a plane F orthogonal with the conductors 2 to prepare a plurality of complex chips 5. Thereafter, the insulator 3 is dissolved and removed from at least one of cutout edges of each chip 5 by use of a chemical, thereby exposing the ends of a plurality of the conductors 2 over the prescribed length. Then, a solder bump 6 is formed on the the end of each exposed conductor 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体チップと回路基
板との電極相互を高い信頼性で電気接続し得るスーパー
マイクロコネクタの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a super micro connector which can electrically connect electrodes of a semiconductor chip and a circuit board to each other with high reliability.

【0002】[0002]

【従来の技術】半導体チップには多数の電極がファイン
ピッチで形成されており、この電極数は、回路の高集積
化に伴い増加の一途を辿っている。半導体チップの電極
を外部と電気接続するには、リードフレームを用いたD
IP(Dual Inline Package)が主流であったが、電極数
が増加し多数の電極を格子状や多層に配列するようにな
ると、従来のリードフレームを用いたDIPでは対応す
ることができなくなった。
2. Description of the Related Art A large number of electrodes are formed on a semiconductor chip at a fine pitch, and the number of electrodes is increasing along with the high integration of circuits. To electrically connect the electrodes of the semiconductor chip to the outside, use a lead frame
IP (Dual Inline Package) has been the mainstream, but when the number of electrodes has increased and a large number of electrodes have been arranged in a grid pattern or a multilayer structure, conventional DIP using a lead frame cannot cope with this.

【0003】このため、多数の電極を使用する場合に
は、半導体チップと同数の電極を同じピッチで配列した
回路基板の電極と半導体チップの電極とを半田ボールを
リフローソルダリングすることで、半導体チップを直接
回路基板に搭載するベアチップ実装法(Chip On Board
法又はFlip Chip法とも称される。)が使用されてい
た。
For this reason, when a large number of electrodes are used, the solder balls are reflow-soldered between the electrodes of the circuit board and the electrodes of the semiconductor chip in which the same number of electrodes as the semiconductor chips are arranged at the same pitch, and thereby the semiconductor Bare chip mounting method (Chip On Board)
Also called the Flip Chip method. ) Was used.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このベ
アチップ実装法は、半導体チップの電極と回路基板の電
極とを半田ボールで直接接続する。このため、ベアチッ
プ実装法によって半導体チップを直接搭載した回路基板
は、使用中の温度上昇によって、半導体チップと回路基
板との熱膨張差に起因する熱歪みが生じ、この熱歪みが
半田部分に集中し、半田部分が劣化して接続不良を引き
起こす問題があった。
However, in this bare chip mounting method, the electrodes of the semiconductor chip and the electrodes of the circuit board are directly connected by solder balls. Therefore, a circuit board on which a semiconductor chip is directly mounted by the bare chip mounting method causes thermal strain due to a thermal expansion difference between the semiconductor chip and the circuit board due to a temperature rise during use, and this thermal strain is concentrated on the solder portion. However, there is a problem that the solder portion deteriorates and causes a connection failure.

【0005】本発明は上記の点に鑑みてなされたもの
で、半導体チップや回路基板の電極との間における接続
不良の発生を抑えて良好に接続することが可能な接続性
に優れ、信頼性の高いスーパーマイクロコネクタ(以
下、「SMC]という)の製造方法を提供することを目
的とする。
The present invention has been made in view of the above points, and has excellent connectivity and reliability that suppresses the occurrence of poor connection between the semiconductor chip and the electrodes of the circuit board and enables good connection. It is an object of the present invention to provide a method for manufacturing a high-performance super micro connector (hereinafter referred to as "SMC").

【0006】[0006]

【課題を解決するための手段】この目的を達成するた
め、請求項1のSMCの製造方法は、実質的に平行に配
列した複数の導線を、これらの間に介在させた弾性を有
する絶縁体で固定して導線と絶縁体からなる複合体を作
製する工程、この複合体を前記導線と直交する面で切断
して複数の複合体チップを作製する工程、前記各複合体
チップの少なくとも一方の切断面から前記絶縁体を薬剤
にて溶解除去し、前記複数の導線の端部を所定長さ露出
させる工程、露出した前記各導線の端部に半田バンプを
形成する工程を備えた構成としたのである。
In order to achieve this object, a method of manufacturing an SMC according to a first aspect of the present invention is directed to an elastic insulator in which a plurality of conductive wires arranged substantially in parallel are interposed therebetween. A step of producing a composite body which is fixed by a conductor and an insulator, a step of producing a plurality of composite chips by cutting the composite body at a plane orthogonal to the conductor wire, and at least one of the composite chips The insulator was dissolved and removed from the cut surface with a chemical agent, and a step of exposing the end portions of the plurality of conductive wires by a predetermined length, and a step of forming solder bumps on the exposed end portions of each conductive wire were adopted. Of.

【0007】以下に、本発明のSMCの製造方法を図1
を参照して具体的に説明する。先ず、高寸法精度の金属
製の角パイプ1に、多数本の導線2を角パイプ1の軸と
実質的に平行に所定のパターンで張り渡し、角パイプ1
内に液状の絶縁体3を注入して固化させる。これによ
り、実質的に平行な多数本の導線2が絶縁体3で固定さ
れた複合体4が形成される(図1(a))。
The method of manufacturing the SMC of the present invention will be described below with reference to FIG.
It will be specifically described with reference to. First, a large number of conductive wires 2 are stretched over a square pipe 1 made of metal with high dimensional accuracy in a predetermined pattern substantially in parallel with the axis of the square pipe 1.
A liquid insulator 3 is injected into the inside and solidified. As a result, a composite body 4 in which a large number of substantially parallel conducting wires 2 are fixed by the insulator 3 is formed (FIG. 1 (a)).

【0008】次に、複合体4を角パイプ1から抜き出し
(図1(b))、複合体4を導線2と直交する面Fで所定
厚さに切断して薄板状の複合体チップ5とする(図1
(c))。次いで、複合体チップ5の切断面5a,5bか
ら絶縁体3を薬剤で溶解除去し、多数の導線2の端部を
それぞれ所定長さ露出させる(図1(d))。
Next, the composite body 4 is extracted from the square pipe 1 (FIG. 1 (b)), and the composite body 4 is cut to a predetermined thickness at a plane F orthogonal to the conducting wire 2 to form a thin plate-shaped composite body chip 5. Yes (Fig. 1
(c)). Next, the insulator 3 is dissolved and removed from the cut surfaces 5a and 5b of the composite chip 5 with a chemical agent to expose the end portions of the multiple conductive wires 2 by a predetermined length (FIG. 1 (d)).

【0009】そして、露出した多数の導線2の一方の端
部に略球状の半田バンプ6を一括形成してSMC10を製
造する(図1(e))。尚、図1(c)〜図1(f)において
は、図面を簡単に表現するために多数本の導線2を4本
に省略した。また、後述する図5,図6,図7及び図8
においても、同様の目的から多数本の導線2を省略して
表現した。
Then, the substantially spherical solder bumps 6 are collectively formed on one end of the exposed large number of conductors 2 to manufacture the SMC 10 (FIG. 1 (e)). 1 (c) to 1 (f), a large number of conductor wires 2 are omitted to be four in order to simplify the drawing. Also, FIGS. 5, 6, 7, and 8 described later.
Also, in the above description, a large number of conducting wires 2 are omitted for the same purpose.

【0010】請求項1の方法では、熱膨張率が半導体チ
ップと回路基板との中間の絶縁体を用いることが好まし
い。このような絶縁体は、半導体チップ又は回路基板と
の間の熱膨張率差に起因する熱歪みが半田バンプに生
じ、電気的接続性を悪化させることを防止する。請求項
2の発明は、露出した前記各導線の端部に半田バンプを
形成する工程の後に、前記半田バンプを形成した側の前
記絶縁体を薬剤にて更に溶解除去し、前記半田バンプと
前記絶縁体の間に前記複数の導線を所定長さ露出させる
工程を備えたSMCの製造方法である。
In the method of the first aspect, it is preferable to use an insulator whose coefficient of thermal expansion is intermediate between the semiconductor chip and the circuit board. Such an insulator prevents the solder bumps from suffering thermal strain due to the difference in coefficient of thermal expansion from the semiconductor chip or the circuit board and deteriorating the electrical connectivity. According to a second aspect of the present invention, after the step of forming solder bumps on the exposed ends of each of the conductive wires, the insulator on the side on which the solder bumps are formed is further dissolved and removed with a chemical agent to remove the solder bumps and the solder bumps. It is a manufacturing method of SMC provided with the process of exposing the above-mentioned plurality of conducting wires for a predetermined length between insulators.

【0011】請求項2の方法では、図1(e)に示したS
MC10から、半田バンプ6を形成した側の絶縁体3を更
に薬剤にて除去し、導線2を露出させたSMC11が製造
される(図1(f))。請求項2の方法で製造されるSM
C11は、半田バンプ6と絶縁体3との間に導線2が所定
長さ露出している。従って、このSMC11は、半導体チ
ップや回路基板の電極相互間を半田で接続したときに、
絶縁体と半導体チップ又は回路基板との間の熱膨張率差
に起因する熱歪みが発生しても、導線の露出部分が変形
することにより熱歪みが吸収されるうえ、導線が露出し
ているので放熱性も向上する。
According to the method of claim 2, S shown in FIG.
The insulator 3 on the side where the solder bumps 6 are formed is further removed from the MC 10 with a chemical agent, and the SMC 11 with the conductor 2 exposed is manufactured (FIG. 1 (f)). SM manufactured by the method of claim 2.
In C11, the conductor 2 is exposed between the solder bump 6 and the insulator 3 for a predetermined length. Therefore, this SMC11, when the electrodes of the semiconductor chip and the circuit board are connected by soldering,
Even if thermal strain occurs due to the difference in thermal expansion coefficient between the insulator and the semiconductor chip or the circuit board, the exposed portion of the conductor is deformed to absorb the thermal strain and the conductor is exposed. Therefore, heat dissipation is also improved.

【0012】本発明方法において、導線間に介在させる
絶縁体に、弾性を有する絶縁体を用いる理由は、SMC
と半導体チップや回路基板の電極との半田付け時の熱応
力が前記絶縁体の弾性変形で吸収されるので、電極間距
離の変化や熱膨張による導線の変形が阻害され難く、従
って、電極との間に高い接続性が維持されるためであ
る。
In the method of the present invention, the reason why the elastic insulator is used as the insulator interposed between the conductors is that SMC is used.
Since the thermal stress at the time of soldering with the electrodes of the semiconductor chip and the circuit board is absorbed by the elastic deformation of the insulator, the deformation of the conductive wire due to the change in the distance between the electrodes and the thermal expansion is less likely to be hindered. This is because high connectivity is maintained during the period.

【0013】弾性を有する絶縁体としては、シリコーン
ゴムや高分子エラストマ等が好適である。特に、発泡シ
リコーンゴムは、熱膨張による変形量が小さい。このた
め、半導体チップと回路基板の間にコネクタを挟み、半
導体チップと回路基板の各々の電極とコネクタの導線と
を位置合わせしたのち、加熱によって半田接合する際
に、電極と導線とが位置ずれを起こさず好ましい。
As the elastic insulator, silicone rubber, polymer elastomer, etc. are suitable. In particular, foamed silicone rubber has a small amount of deformation due to thermal expansion. For this reason, the connector is sandwiched between the semiconductor chip and the circuit board, the electrodes of the semiconductor chip and the circuit board are aligned with the lead wires of the connector, and then the electrodes and the lead wires are misaligned when soldered by heating. It does not occur and is preferable.

【0014】半田バンプの大きさは、複合体チップの少
なくとも一方の切断面から露出させる導線の長さによっ
て決まる。露出させた導線の端部に半田バンプを形成す
るには、半田浴に浸漬するか、半田ペーストを刷毛で塗
布する等の通常の方法により行う。半田バンプの形成後
に、半田バンプと絶縁体との間に更に露出させる導線の
長さは、露出する導線と半導体チップ間、又は前記導線
と回路基板間の半田等による接続が容易になし得る長さ
であり、用いる材質により種々に変化させる。
The size of the solder bump is determined by the length of the conductive wire exposed from at least one cut surface of the composite chip. To form the solder bumps on the exposed ends of the conductive wires, the solder bumps are dipped in a solder bath, or the solder paste is applied with a brush. After the formation of the solder bumps, the length of the conductor wire that is further exposed between the solder bump and the insulator is such that the exposed conductor wire and the semiconductor chip or the conductor wire and the circuit board can be easily connected by soldering or the like. That is, it is variously changed depending on the material used.

【0015】ここで、絶縁体から露出させる導線の長さ
は、半田バンプの形成前にあっては0.02〜0.1mmが好
ましい。導線の露出長が、0.02mmより短いと十分な大
きさの半田バンプを形成することができない。一方、導
線の露出長が0.1mmを越えると略球状の適正な形状の半
田バンプを形成することができない。これに対し、半田
バンプの形成後、更に導体を露出させる場合にあって
は、導線の露出長は、0.2mm以上が好ましい。露出させ
た導線の長さが0.2mmより短いと、半導体チップや回路
基板と半田付けするときに位置決め治具を使用するため
のスペースを確保することができず半田付け作業がし難
くなると共に、半導体チップや回路基板に対する位置決
め精度が悪くなる。
Here, the length of the conductive wire exposed from the insulator is preferably 0.02 to 0.1 mm before the formation of the solder bump. If the exposed length of the conductive wire is shorter than 0.02 mm, a solder bump having a sufficient size cannot be formed. On the other hand, if the exposed length of the conductive wire exceeds 0.1 mm, it is impossible to form a substantially spherical solder bump having an appropriate shape. On the other hand, when the conductor is further exposed after the solder bump is formed, the exposed length of the conductive wire is preferably 0.2 mm or more. If the length of the exposed conductor wire is shorter than 0.2 mm, the space for using the positioning jig cannot be secured when soldering with the semiconductor chip or the circuit board, and the soldering work becomes difficult. However, the positioning accuracy with respect to the semiconductor chip or the circuit board deteriorates.

【0016】前記バンプの形成に用いる半田としては、
通常使用されるSn−Pb系半田、純Sn等の他、Bi
−In系,InあるいはBi−Sn系等の低温用半田を
使用してもよい。但し、絶縁体としてシリコーンゴムを
使用する場合は、シリコーンゴムの耐熱性の点から融点
が320℃以上の半田は使用できない。前記絶縁体を溶
解除去する薬剤には、通常市販の薬剤が使用される。例
えば、絶縁体がシリコーンゴムの場合には、溶解量と時
間経過との間に略一次関数の関係が成立し、絶縁体の除
去量を時間によって容易に制御できる2−メトキシエタ
ノール系溶剤が使用される。
As the solder used for forming the bumps,
Other than commonly used Sn-Pb type solder, pure Sn, etc., Bi
You may use low temperature solder, such as -In type | system | group, In, or Bi-Sn type | system | group. However, when silicone rubber is used as the insulator, solder having a melting point of 320 ° C. or higher cannot be used because of the heat resistance of the silicone rubber. A commercially available drug is usually used as a drug for dissolving and removing the insulator. For example, when the insulator is a silicone rubber, a 2-methoxyethanol-based solvent is used, which has a substantially linear relationship between the amount of dissolution and the passage of time, and the amount of insulator removed can be easily controlled by time. To be done.

【0017】本発明方法で用いる導線には、導電性を有
する任意の材料が適用される。具体的には、リン青銅、
Cu−Be系合金、洋白、コルソン合金等の銅合金材料
が好適である。導線の形状は、例えば、図2(a)に示す
丸線の他、角線、これらの撚線、異型線等任意である。
絶縁体にシリコーンゴムを用いた場合、導線を構成する
金属材料の熱膨張係数が10〜20×10-6/℃であるのに対
し、シリコーンゴムのそれは 200〜300 ×10-6/℃と大
きい。このため、シリコーンゴムが、半田バンプを形成
する際の温度上昇で熱膨張し、導線から剥離した状態と
なり易い。この結果、シリコーンゴムが導線を把持する
力が弱まり、SMCの製造に際して導線がシリコーンゴ
ムから抜け易くなる。このような事態を避けるには、導
線の形状を絶縁体と剥離し難い形状にすることが好適で
ある。
Any material having conductivity is applied to the conductive wire used in the method of the present invention. Specifically, phosphor bronze,
Copper alloy materials such as Cu-Be alloys, nickel silver and Corson alloy are suitable. The shape of the conducting wire is arbitrary, for example, in addition to the round wire shown in FIG. 2 (a), a square wire, a twisted wire thereof, a modified wire, or the like.
When silicone rubber is used as the insulator, the thermal expansion coefficient of the metal material that constitutes the conductor is 10 to 20 x 10-6 / ° C, whereas that of silicone rubber is 200 to 300 x 10-6 / ° C. large. Therefore, the silicone rubber thermally expands due to the temperature rise when forming the solder bumps, and is likely to be separated from the conductor. As a result, the force with which the silicone rubber grips the conducting wire is weakened, and the conducting wire is likely to come off from the silicone rubber during the production of SMC. In order to avoid such a situation, it is preferable to make the shape of the conductor wire into a shape that is difficult to separate from the insulator.

【0018】絶縁体と剥離し難い導線の形状としては、
図2(b)に示した導線2のように、開口部の幅が狭く内
部の幅が広い凹溝2aを表面に所要数設けた異型線があ
る。この異型線によれば、絶縁体が凹溝2aの中に入り
込んで導線との間の接触面積が大きく、SMC使用中の
温度上昇に際し、絶縁体が膨張して凹溝2aの内外に絶
縁体が締まり付くようになる。この異型線に捩じりを入
れ、凹溝2aを螺旋状に形成すると、絶縁体内での導線
の上下方向への変位が抑えられる。
As the shape of the conductor wire which is difficult to peel off from the insulator,
There is a modified wire having a required number of recessed grooves 2a having a narrow opening and a wide inner width, such as the conducting wire 2 shown in FIG. 2B. According to this atypical wire, the insulator enters into the groove 2a and has a large contact area with the conductor wire, and when the temperature rises during use of the SMC, the insulator expands and the insulator is formed inside and outside the groove 2a. Will be tightened. By twisting this irregular wire and forming the concave groove 2a in a spiral shape, the vertical displacement of the conductor in the insulator can be suppressed.

【0019】また、図2(c)に示した撚線からなる導線
2でも、絶縁体との接触面積が大きくとれるうえ、撚線
は上下方向に捩れているので、導線の上下方向の変位も
抑えられる。更に、図2(d)に示した角線を表面に凹凸
が形成されるように集合し接合させた導線2は、通常の
図2(c)に示した撚線に比べて接触面積が大きくなり、
導線の動きがより強く抑制される。
Also, in the conductor 2 composed of the twisted wire shown in FIG. 2C, the contact area with the insulator can be made large and the twisted wire is twisted in the vertical direction, so that the conductor is also displaced in the vertical direction. It can be suppressed. Furthermore, the conductor wire 2 in which the square wires shown in FIG. 2 (d) are assembled and joined so that the surface has irregularities, has a larger contact area than the ordinary twisted wire shown in FIG. 2 (c). Becomes
The movement of the conductor wire is more strongly suppressed.

【0020】このとき、絶縁体と導線とを接着剤で接着
しておくと導線の変位がより確実に抑制できる。このよ
うな接着剤としては、金属材料とシリコーンゴム等とを
強力に接着できるプライマーが望ましく、絶縁体と導線
との接着に際して予め導線にプライマーを塗布してお
く。本発明方法において、半田バンプを所定形状に安定
して形成するには、図3に示した導線2が好適である。
導線2は、所定の腐食液により浸食される材料を芯材2
bとし、非浸食性の材料を被覆材2cにして構成した複
合線で(図3(a))、この導線の端部を所定の腐食液に
浸漬すると、芯材2bが浸食され頂部がカップ状に凹ん
だ凹部2dが形成される(図3(b))。この頂部を半田
浴に浸漬すると、半田はこのカップ状の凹部2d内に凝
固する。凹部2dの形状は、腐食条件により任意に制御
できる。
At this time, if the insulator and the conductive wire are bonded with an adhesive, the displacement of the conductive wire can be suppressed more reliably. As such an adhesive, a primer capable of strongly adhering a metal material to silicone rubber or the like is desirable, and the conductor is preliminarily coated with the primer when the insulator and the conductor are adhered. In the method of the present invention, the conductive wire 2 shown in FIG. 3 is suitable for stably forming the solder bump in a predetermined shape.
The conductor 2 is made of a material that is corroded by a predetermined corrosive liquid.
b and a composite wire composed of a non-erodible material and a coating material 2c (FIG. 3 (a)). When the end of this wire is dipped in a predetermined corrosive liquid, the core material 2b is eroded and the top is cupped. A concave portion 2d that is concave is formed (FIG. 3B). When the top is dipped in the solder bath, the solder is solidified in the cup-shaped recess 2d. The shape of the recess 2d can be arbitrarily controlled depending on the corrosion conditions.

【0021】請求項8の発明は、実質的に平行に配列し
た複数の導線を、これらの間に介在させた弾性を有する
絶縁体で固定して導線と絶縁体からなる複合体を作製す
る工程において、V溝を所定ピッチで複数形成した高さ
が異なる複数の部材により、前記複数の導線を張力を付
与した状態で所定間隔をおいて複数の平行導線列に積層
形成するSMCの製造方法である。
According to an eighth aspect of the invention, a process of fixing a plurality of conducting wires arranged substantially in parallel with an elastic insulator interposed between them to produce a composite of the conducting wires and the insulator. In the method of manufacturing an SMC, a plurality of V-grooves are formed at a predetermined pitch and have different heights, and the plurality of conductors are stacked and formed in a plurality of parallel conductor rows at a predetermined interval in a tensioned state. is there.

【0022】請求項8の製造方法は、複数の導線の位置
決めをV溝を利用して行うので作業が容易である。複数
の導線の配列方向の位置決めは、V溝を所定ピッチで形
成した鉄製ブロックを直角に切断研削したV溝駒を用い
ることにより精度よく行うことができる。このとき、各
導線に張力を付与するには、導線の端部に取り付けた錘
によって引張る方法が簡便で良い。また、複数の平行導
線列の積層間隔は、平行導線列の間に介在させるスペー
サーにより高精度に調整できる。
In the manufacturing method of the eighth aspect, since the positioning of the plurality of conducting wires is performed by using the V groove, the work is easy. Positioning of the plurality of conducting wires in the arrangement direction can be performed accurately by using a V-groove piece obtained by cutting and grinding an iron block in which V-grooves are formed at a predetermined pitch at a right angle. At this time, in order to apply tension to each conductor, a method of pulling with a weight attached to the end of the conductor may be simple. Further, the stacking interval of the plurality of parallel conductor lines can be adjusted with high accuracy by a spacer interposed between the parallel conductor lines.

【0023】請求項11の発明は、弾性を有する絶縁体
に、縮合型シリコーンゴムを用いるSMCの製造方法で
ある。シリコーンゴムは、耐熱性及び耐フラックス性に
優れるので、半田付け時の環境に十分耐えられる。ま
た、シリコーンゴムは薬剤に比較的安定して溶解するの
で、導線の露出長さを一定にできる。シリコーンゴムの
中では、重合度の高い付加型シリコーンゴムは、溶解に
長時間を要し、又溶解時に膨潤して形状が崩れることが
ある。これに対し、重合密度が低く、フィラー量の比較
的多い縮合型シリコーンゴムは、短時間に溶解し、且つ
均一に溶解するので絶縁体として好適である。
The invention of claim 11 is a method for producing an SMC, wherein condensed silicone rubber is used as an insulator having elasticity. Since silicone rubber has excellent heat resistance and flux resistance, it can sufficiently withstand the environment during soldering. Further, since the silicone rubber dissolves in the drug relatively stably, the exposed length of the conductive wire can be made constant. Among the silicone rubbers, the addition type silicone rubber having a high degree of polymerization takes a long time to dissolve, and may swell and lose its shape when dissolved. On the other hand, a condensation type silicone rubber having a low polymerization density and a relatively large amount of filler dissolves in a short time and uniformly dissolves, and is therefore suitable as an insulator.

【0024】請求項12の発明は、各複合体チップの少な
くとも一方の切断面から前記絶縁体を薬剤にて溶解除去
し、複数の導線の端部を所定長さ露出させる工程及び露
出した前記各導線に半田バンプを形成する工程におい
て、前記各複合体チップの両切断面に前記複数の導線の
端部を露出させ、一方の切断面に露出した前記複数の導
線を電極用金属板と電気的に接続し、他方の切断面に露
出した前記複数の導線に半田バンプを電気めっきで形成
するSMCの製造方法である。
According to a twelfth aspect of the present invention, the step of dissolving and removing the insulating material with a chemical from at least one cut surface of each composite chip to expose the end portions of a plurality of conductive wires by a predetermined length, and the exposed each In the step of forming solder bumps on the conductive wire, the ends of the plurality of conductive wires are exposed on both cut surfaces of each composite chip, and the plurality of conductive wires exposed on one cut surface are electrically connected to the metal plate for electrodes. And a solder bump is formed on the plurality of conductive wires exposed on the other cut surface by electroplating.

【0025】複合体チップから露出させた導線の端部に
は、半田バンプを形成して半導体チップ又は回路基板を
接続する。半田バンプは、ホットディップ法で形成する
と、大きく形成することが難しい。しかし、半田バンプ
は、電気めっき法を用いると、任意の大きさを均一な形
状に形成できる。
Solder bumps are formed on the ends of the lead wires exposed from the composite chip to connect the semiconductor chip or the circuit board. If the solder bumps are formed by the hot dip method, it is difficult to make them large. However, the solder bump can be formed in an arbitrary size and a uniform shape by using the electroplating method.

【0026】請求項13の発明は、前記複合体チップの一
方の切断面に、露出した前記複数の導線も含めて導電性
ペーストを塗布し、該ペースト表面を絶縁被覆した後、
一方の切断面に露出した前記複数の導線及び前記導電性
ペーストを電源と接続した導体に接触させて給電するこ
とにより、他方の切断面に露出した前記複数の導線に半
田バンプを電気めっきで形成するSMCの製造方法であ
る。
According to a thirteenth aspect of the present invention, a conductive paste including the exposed plurality of conductive wires is applied to one cut surface of the composite chip, and the paste surface is insulation-coated,
Forming solder bumps on the plurality of conductors exposed on the other cut surface by electroplating by feeding the plurality of conductors exposed on one cut surface and the conductive paste to a conductor connected to a power source to supply power. It is a manufacturing method of SMC.

【0027】導電性ペーストには、例えば樹脂ペースト
に銅粉や銀粉を分散させたものが用いられる。導電性ペ
ーストを乾燥固化させて導体に接触させると、給電時の
作業性が改善される。半田めっきが不要の個所はマニキ
ュア等で絶縁して、半田バンプの形状がより正確に形成
されるようにすることが好ましい。図8は、複合体チッ
プ5の複数の導線2に半田バンプ6を電気めっきする状
況を示す断面図である。複合体チップ5の一方の切断面
に露出した導線2は、導電性ペースト20が塗布され、導
電性ペースト20に電極板22が電気的に接続されている。
導電性ペースト20及び電極板22は、マニキュア層21(又
は絶縁フイルム等)により絶縁されている。
As the conductive paste, for example, a resin paste in which copper powder or silver powder is dispersed is used. When the conductive paste is dried and solidified and brought into contact with the conductor, workability during power feeding is improved. It is preferable to insulate the portions where solder plating is not necessary with nail polish or the like so that the shape of the solder bumps can be formed more accurately. FIG. 8 is a cross-sectional view showing a state where the solder bumps 6 are electroplated on the plurality of conductive wires 2 of the composite chip 5. A conductive paste 20 is applied to the conductive wire 2 exposed on one cut surface of the composite chip 5, and an electrode plate 22 is electrically connected to the conductive paste 20.
The conductive paste 20 and the electrode plate 22 are insulated by the nail polish layer 21 (or an insulating film or the like).

【0028】このように、給電する側の導線2に導電性
ペースト20を塗布し、導電性ペースト20を電源に接続し
た電極板22に接触させることにより、導線2と電極板22
との接続を完全なものにできる。このためには、給電す
る側の導線2の露出長さは十分に長くし、ペースト7と
露出した導線2との接触を確実なものとすることが好ま
しい。導電性ペースト20は、乾燥固化させたものであっ
ても、半田めっき後、溶媒に溶かしたり又は化学的方法
で容易に除去できる。
In this way, by applying the conductive paste 20 to the conducting wire 2 on the side of supplying power and bringing the conductive paste 20 into contact with the electrode plate 22 connected to the power source, the conducting wire 2 and the electrode plate 22 are connected.
The connection with can be perfect. For this purpose, it is preferable that the exposed length of the conducting wire 2 on the power feeding side be sufficiently long to ensure contact between the paste 7 and the exposed conducting wire 2. Even if the conductive paste 20 is dried and solidified, it can be dissolved in a solvent after solder plating or can be easily removed by a chemical method.

【0029】従って、請求項13のSMCの製造方法によ
れば、数百〜数千本の導線の各端部に任意の大きさの半
田バンプを均一、且つ容易に形成することができる。請
求項14の発明は、複数の導線が金線又は金被覆導線であ
るSMCの製造方法である。導線には半導体チップや回
路基板の電極が接続される。このため、導線には良好な
半田付性が要求される。金線又は金被覆導線は、表面が
酸化し難く耐環境性に優れ接触抵抗が小さいため、給電
が露出した導線の各々に均等になされる。従って、多数
の露出導線の各々に均一な大きさの半田バンプが電気め
っきされる。
Therefore, according to the SMC manufacturing method of the thirteenth aspect, it is possible to uniformly and easily form solder bumps of an arbitrary size at each end of several hundreds to several thousands of conductive wires. The invention of claim 14 is the method of manufacturing an SMC, wherein the plurality of conductive wires are gold wires or gold-coated conductive wires. Electrodes on a semiconductor chip or a circuit board are connected to the conductors. Therefore, the conductor is required to have good solderability. Since the surface of the gold wire or the gold-coated conductor is not easily oxidized, the environment resistance is excellent, and the contact resistance is small, the power supply is evenly performed on each exposed conductor. Therefore, solder bumps of uniform size are electroplated on each of the multiple exposed conductors.

【0030】また、金線又は金被覆導線は、In と非反
応性であるため、給電側の露出導線群にIn系の低融点
半田を付着させ、このIn系半田に電極用金属板を直接
接続して給電をより確実に行うことができる。更に、金
線又は金被覆導線は耐酸性に優れるため、半田めっき終
了後のIn 系半田の溶融除去と酸による洗浄が容易に行
え、導線を傷つけることもない。
Further, since the gold wire or the gold-coated conductive wire is non-reactive with In, a low melting point solder of In series is attached to the exposed conductive wire group on the power feeding side, and the metal plate for electrodes is directly attached to this In series solder. Power can be supplied more reliably by connecting. Further, since the gold wire or the gold-coated conductive wire has excellent acid resistance, the In-based solder can be easily melted and removed after the completion of solder plating and washed with an acid, and the conductive wire is not damaged.

【0031】請求項15の発明は、複数の導線の表面が電
解処理又は化学的エッチングにより粗面に形成されてい
るSMCの製造方法である。複合体チップにおける導線
と絶縁体の固着力は、絶縁体の弾性力によるものと、導
線の形状的固着力によるものとがあるが、導線表面を粗
面にすることにより導線と絶縁体との接触面積が増加し
て固着力が向上し、コネクタとしての信頼性が高まる。
A fifteenth aspect of the present invention is a method for manufacturing an SMC in which the surfaces of a plurality of conducting wires are roughened by electrolytic treatment or chemical etching. The fixing force between the conductor and the insulator in the composite chip may be due to the elastic force of the insulator or due to the shape fixing force of the conductor. However, by roughening the conductor surface, the conductor and the insulator are The contact area is increased, the fixing force is improved, and the reliability as a connector is improved.

【0032】[0032]

【作用】本発明方法では、(1) 実質的に平行に配列した
複数の導線を、これらの間に介在させた弾性を有する絶
縁体で固定して導線と絶縁体からなる複合体を作製し、
この複合体を導線と直交する面で切断して複数の複合体
チップとすると、高精度の複合体チップを量産できる。
In the method of the present invention, (1) a plurality of conducting wires arranged substantially in parallel are fixed by an elastic insulator interposed between them to prepare a composite of the conducting wire and the insulator. ,
By cutting this composite into a plurality of composite chips by cutting the composite along a plane orthogonal to the conducting wire, it is possible to mass-produce high-precision composite chips.

【0033】(2) 複合体チップから導線を露出させるの
に絶縁体を薬剤にて溶解除去すると、導線の露出長さを
任意に制御できる。従って、露出した前記各導線には所
定形状の半田バンプを安定して形成できる。 (3) 複合体チップから露出した導線に半田バンプを形成
するので、半田バンプの形状や大きさを制御できる。
(2) If the insulator is dissolved and removed with a chemical agent to expose the conductor wire from the composite chip, the exposed length of the conductor wire can be arbitrarily controlled. Therefore, solder bumps having a predetermined shape can be stably formed on each exposed conductor. (3) Since the solder bump is formed on the conductive wire exposed from the composite chip, the shape and size of the solder bump can be controlled.

【0034】(4) 半田バンプと絶縁体との間の導線を所
定長さ露出させるので、半導体チップと半田付けする
際、位置決め治具が使用でき、位置決め精度が向上す
る。 (5) 上記導線の露出により、回路基板との半田付け作業
等が容易になり、強固な接続が得られる。 (6) 導線間に弾性を有する絶縁体を介在させると、半田
付け時の熱応力は前記絶縁体の変形で吸収され、電極と
導体間で位置ずれが起きない。
(4) Since the conductive wire between the solder bump and the insulator is exposed for a predetermined length, a positioning jig can be used when soldering with the semiconductor chip, and the positioning accuracy is improved. (5) By exposing the conductive wire, soldering work with a circuit board is facilitated, and a strong connection is obtained. (6) If an insulating material having elasticity is interposed between the conductors, thermal stress during soldering is absorbed by the deformation of the insulating material, and no positional displacement occurs between the electrode and the conductor.

【0035】また、本発明では、(7) 多数の極細導線の
実質的な平行配列を、V溝を設けた駒を用いることによ
り容易に行える。 (8) 駒のV溝に配置した導線は、導線端部に重りを付け
て引張ることにより、容易にその配列精度を高められ
る。 (9) 駒のV溝に配置した導線の配列(幅)方向の位置
は、所定ピッチで形成されたV溝内に導線を配置するこ
とにより精度よく決められる。また、複数の平行導線列
の積層間隔は、平行導線列間にスペーサーを介在させる
ことにより容易に調節できる。
Further, according to the present invention, (7) a substantial parallel arrangement of a large number of fine conductor wires can be easily performed by using a piece provided with a V groove. (8) The lead wires arranged in the V-grooves of the bridge can be easily increased in alignment accuracy by weighting the lead wire ends and pulling. (9) The position in the arrangement (width) direction of the conductor wires arranged in the V-grooves of the piece is accurately determined by disposing the conductor wires in the V-grooves formed at a predetermined pitch. Further, the stacking interval of the plurality of parallel conductive wire rows can be easily adjusted by interposing a spacer between the parallel conductive wire rows.

【0036】(10)弾性体に、重合密度が低くフィラー量
の比較的多い縮合型シリコーンゴムを用いると、導線を
短時間で均一な長さに露出させることができる。 (11)半田バンプを電気めっき法により形成すると、任意
の大きさの半田バンプを均一な形状に形成できる。 (12)電気めっきのための給電は、複合体チップの一方の
切断面に、露出した前記複数の導線と共に導電性ペース
トを塗布して絶縁被覆した後、多数の導線及びこのペー
ストを電源と接続した導体に電気的に接続することによ
り容易に行える。
(10) If a condensation type silicone rubber having a low polymerization density and a relatively large amount of filler is used for the elastic body, the conductive wire can be exposed to a uniform length in a short time. (11) By forming the solder bumps by the electroplating method, it is possible to form the solder bumps of any size in a uniform shape. (12) The power supply for electroplating is performed by applying a conductive paste together with the exposed plurality of conductive wires to one cut surface of the composite chip to insulate and then connecting a large number of conductive wires and this paste to a power source. This can be easily done by electrically connecting to the conductor.

【0037】(13)表面が酸化し難く耐環境性が良好な金
線又は金被覆導線を導線として用いると、露出した多数
の導線に形状均一な半田バンプを電気めっきできる。 (14)導線の表面を電解処理又は化学的エッチングにより
粗面に形成すると、導線と絶縁体との接触面積が増加し
て両者の固着力が向上する。
(13) When a gold wire or a gold-coated conductor wire having a surface that is hard to oxidize and has good environment resistance is used as a conductor wire, solder bumps having a uniform shape can be electroplated on a large number of exposed conductor wires. (14) When the surface of the conductive wire is formed into a rough surface by electrolytic treatment or chemical etching, the contact area between the conductive wire and the insulator is increased, and the adhesion force between both is improved.

【0038】[0038]

【実施例】以下に本発明を実施例により詳細に説明す
る。 (実施例1)図1に示した工程に従ってSMC10を製造
した。長さ 500mm、一辺が15±0.01mmの低炭素鋼からな
る角パイプ1内に、リン青銅(Cu,8wt%Sn,0.13wt
% P)からなる金めっきした導線2(直径0.08mm)を0.
25mmピッチで1,600 本、軸方向に実質的に平行に張り渡
し、パイプ1内に絶縁体3として液状のシリコーンゴム
を注入し固化させて導線2及び絶縁体3からなる複合体
4を形成した(図1(a))。
The present invention will be described below in detail with reference to examples. Example 1 SMC10 was manufactured according to the steps shown in FIG. Phosphor bronze (Cu, 8wt% Sn, 0.13wt) is placed in a square pipe 1 made of low carbon steel with a length of 500mm and a side of 15 ± 0.01mm.
% P) of gold-plated conductor 2 (0.08 mm diameter)
1,600 pieces were stretched at a pitch of 25 mm substantially parallel to the axial direction, and liquid silicone rubber was injected into the pipe 1 as an insulator 3 and solidified to form a composite body 4 composed of a conductor 2 and an insulator 3 ( Figure 1 (a)).

【0039】次に、複合体4を角パイプ1から抜き出し
(図1(b))、これを導線2と直交する面Fで厚さ 1.5
mmに切断して複合体チップ5とした(図1(c))。絶縁
体3には、重合密度の高い付加型シリコーンゴムを用い
た。次いで、複合体チップ5を2−メトキシエタノール
の中に浸漬し、切断面5a,5bから絶縁体3を溶解除
去し、多数の導線2の端部をそれぞれ0.02mmの長さ露出
させた(図1(d))。
Next, the composite body 4 was extracted from the square pipe 1 (FIG. 1 (b)), and the thickness of the composite body 4 on the plane F orthogonal to the conducting wire 2 was 1.5.
The composite chip 5 was cut into mm (FIG. 1 (c)). For the insulator 3, an addition type silicone rubber having a high polymerization density was used. Next, the composite chip 5 was immersed in 2-methoxyethanol to dissolve and remove the insulator 3 from the cut surfaces 5a and 5b, exposing the end portions of the multiple conductors 2 to a length of 0.02 mm (Fig. 1 (d)).

【0040】その後、露出した多数の導線2の一端側を
半田浴に浸漬し、各々の導線2の一端に半田バンプ6を
形成し、15mm×15mm×1.5 mmの図1(e)に示すSMC10
を製造した。半田浴には、90wt%Pb,10wt%Snからな
る融点が280〜300℃のSn−Pb系高温半田を用いた。
Thereafter, one end side of the exposed large number of conductors 2 is immersed in a solder bath to form solder bumps 6 on one end of each conductor 2, and the SMC 10 of 15 mm × 15 mm × 1.5 mm shown in FIG. 1 (e) is formed.
Was manufactured. For the solder bath, Sn-Pb type high temperature solder composed of 90 wt% Pb and 10 wt% Sn and having a melting point of 280 to 300 ° C. was used.

【0041】尚、上記導線を0.25 mmピッチで実質的に
平行に張り渡すには、合計1,600本の直径0.083 mmの孔
を上下左右方向に、0.25mmのピッチで設けた2枚の目板
を500mmの間隔を開けて前記パイプの両端に設置し、前
記目板の各々の孔に導線を1本づつ通して行った。 (実施例2)絶縁体に発泡シリコーンゴムを用いた他
は、実施例1と同じ方法により15mm×15mm×1.5 mmの図
1(e)に示すSMC10を製造した。 (実施例3)実施例1で製造した図1(e)に示すSMC
10を、半田バンプ6を形成した側を再び前記薬剤に浸漬
して絶縁体3を更に溶解除去し、半田バンプ6と絶縁体
3との間に導線2を0.25 mm露出させ、15mm×15mm×1.5
mmの図1(f)に示すSMC11を製造した。 (実施例4)絶縁体に発泡シリコーンゴムを用いた他
は、実施例1,3と同じ方法により15mm×15mm×1.5 mm
の図1(f)に示すSMC11を製造した。 (実施例5)図2(b)に示した凹溝2aを形成した直径
0.08mmの導線2を用い、孔の直径が0.083 mmの目板を用
いた他は、実施例1,3と同じ方法により15mm×15mm×
1.5mmの図1(f)に示すSMC11を製造した。 (実施例6)導線2として図2(c)に示した撚線(リン
青銅線の7本撚線,直径0.08mm)を用い、孔の直径が0.
083 mmの目板を用いた他は、実施例1,3と同じ方法に
より15mm×15mm×1.5 mmの図1(f)に示すSMC11を製
造した。
In order to stretch the above-mentioned conductive wires substantially in parallel at a pitch of 0.25 mm, a total of 1,600 holes having a diameter of 0.083 mm are provided in the vertical and horizontal directions at two pitches of 0.25 mm. It was installed at both ends of the pipe with an interval of 500 mm, and one conductor was passed through each hole of the eye plate. Example 2 An SMC 10 of 15 mm × 15 mm × 1.5 mm shown in FIG. 1 (e) was manufactured by the same method as in Example 1 except that foamed silicone rubber was used as the insulator. (Example 3) The SMC manufactured in Example 1 and shown in FIG.
The side on which the solder bumps 6 are formed is again immersed in the above chemical to dissolve and remove the insulator 3, and the conductor wire 2 is exposed between the solder bumps 6 and the insulator 3 by 0.25 mm, 15 mm × 15 mm × 1.5
mm of SMC11 shown in FIG. 1 (f) was manufactured. (Example 4) 15 mm x 15 mm x 1.5 mm in the same manner as in Examples 1 and 3 except that foamed silicone rubber was used for the insulator.
SMC11 shown in FIG. 1 (f) was manufactured. (Embodiment 5) Diameter in which the concave groove 2a shown in FIG. 2 (b) is formed
15 mm x 15 mm x in the same manner as in Examples 1 and 3 except that the conductor wire 2 having a diameter of 0.08 mm was used and the eye plate having a hole diameter of 0.083 mm was used.
A 1.5 mm SMC 11 shown in FIG. 1 (f) was manufactured. (Example 6) As the conductor 2, the twisted wire shown in FIG. 2 (c) (7 twisted wires of phosphor bronze wire, diameter 0.08 mm) was used, and the diameter of the hole was 0.
The SMC11 shown in FIG. 1 (f) having a size of 15 mm × 15 mm × 1.5 mm was manufactured by the same method as in Examples 1 and 3 except that a 083 mm eye plate was used.

【0042】実施例1〜6で製造したSMC10,11をそ
れぞれ1,000個用意し、これらを用いて半導体チップと
回路基板の電極をそれぞれ対応する導線で接続した。接
続は図5(a)〜図5(f)に示した手順に従った。ここ
で、図5は、SMC11を用いて半導体チップと回路基板
の電極をそれぞれ対応する導線で接続する場合の図であ
る。しかし、図5に示した手順は、SMC10の場合でも
使用できるので、以下においてはSMC11の場合につい
て説明し、SMC10の場合の説明を省略する。
1,000 SMCs 10 and 11 produced in Examples 1 to 6 were prepared, and using these, the semiconductor chip and the electrodes of the circuit board were connected by the corresponding conductors. The connection followed the procedure shown in FIGS. 5 (a) to 5 (f). Here, FIG. 5 is a diagram in the case where the electrodes of the semiconductor chip and the circuit board are connected by corresponding conductors using the SMC 11. However, since the procedure shown in FIG. 5 can be used even in the case of SMC10, the case of SMC11 will be described below, and the description of the case of SMC10 will be omitted.

【0043】また、図5に示す半導体チップ30と回路基
板32は、それぞれ1,600 個の電極30a,32aがSMC11
の多数の導線2と同じパターンに形成されている。先
ず、SMC11の各導線2に形成された半田バンプ6をそ
れぞれ半導体チップ30の対応する電極30a側に配置した
(図5(a))。次に、SMC11の各半田バンプ6をリフ
ローソルダリングにより半導体チップ30の対応する電極
30aに接続した(図5(b))。
Further, in the semiconductor chip 30 and the circuit board 32 shown in FIG. 5, 1,600 electrodes 30a and 32a are provided in the SMC11.
Are formed in the same pattern as the large number of conducting wires 2. First, the solder bumps 6 formed on the conductors 2 of the SMC 11 were arranged on the corresponding electrodes 30a side of the semiconductor chip 30 (FIG. 5 (a)). Next, the solder bumps 6 of the SMC 11 are connected to the corresponding electrodes of the semiconductor chip 30 by reflow soldering.
It was connected to 30a (Fig. 5 (b)).

【0044】次いで、SMC11の他側に露出した導線2
に半田バンプ6より融点の低い半田バンプ7を形成した
(図5(c))。しかる後、半田バンプ7側の絶縁体3を
薬剤の中に浸漬して表層を溶解除去することにより、半
田バンプ7側の導線2を0.25mm露出させた(図5
(d))。次に、回路基板32の各電極32a上に、対応する
導線2の半田バンプ7を位置させ(図5(e))、半田バン
プ7を半田バンプ6が溶けない温度でリフローソルダリ
ングして、半導体チップ30と回路基板32をSMC11を介
して接続した(図5(f))。
Next, the conductor 2 exposed on the other side of the SMC 11
A solder bump 7 having a melting point lower than that of the solder bump 6 was formed on the surface of the solder bump 6 (FIG. 5C). Then, the insulator 3 on the solder bump 7 side is immersed in a chemical to dissolve and remove the surface layer to expose the conductor wire 2 on the solder bump 7 side by 0.25 mm (FIG. 5).
(d)). Next, the solder bumps 7 of the corresponding conductive wire 2 are positioned on each electrode 32a of the circuit board 32 (FIG. 5 (e)), and the solder bumps 7 are reflow-soldered at a temperature at which the solder bumps 6 do not melt, The semiconductor chip 30 and the circuit board 32 were connected via the SMC 11 (FIG. 5 (f)).

【0045】ここで、半田バンプ6は前述のようにSn
−Pb系高温半田を、半田バンプ7は38 wt%Pb,62 w
t%Snからなる融点が183 ℃のSn−Pb系低温(共
晶)半田を用いた。そして、断続通電によるSMC10,1
1の各導線2と電極30a,32aとの接続部における長期劣
化試験を行い、SMC10,11 の各導線2と半導体チップ
30の電極30aや回路基板32の電極32aとの間で導通不良
を起こしたSMC10,11の個数(1,000個あたり)を調べ
た。結果を表1に示した。 (実施例7)Cu−1%Cr合金を芯材2bとし、Nb
金属(0.4 μm厚さ)を被覆材2cとした直径0.08mmの
複合線からなる1,600 本の導線2(図3(a)参照)を用
い、実施例1と同様にして図1(c)に示す複合体チップ
5を製造した。
Here, the solder bump 6 is Sn as described above.
-Pb-based high temperature solder, solder bump 7 is 38 wt% Pb, 62 w
A Sn-Pb-based low temperature (eutectic) solder having a melting point of 183 [deg.] C. made of t% Sn was used. And SMC10,1 by intermittent energization
A long-term deterioration test was conducted on the connection between each conductor 2 of 1 and the electrodes 30a, 32a, and each conductor 2 of SMC10, 11 and the semiconductor chip
The number (per 1,000 pieces) of the SMCs 10 and 11 that failed in conduction with the electrode 30a of 30 and the electrode 32a of the circuit board 32 was examined. The results are shown in Table 1. (Example 7) Cu-1% Cr alloy was used as the core material 2b, and Nb was used.
Using 1,600 conducting wires 2 (see FIG. 3 (a)) made of a composite wire having a diameter of 0.08 mm and a coating material 2c made of metal (0.4 μm thickness), the same procedure as in Example 1 was applied to FIG. 1 (c). The composite chip 5 shown was manufactured.

【0046】次に、複合体チップ5の切断面5a,5b
から絶縁体3を2−メトキシエタノールで溶解除去して
各導線2を0.02 mm長さ露出させた(図1(d))。次い
で、絶縁体3の一方の側に露出した導線2を硝酸水溶液
に浸漬して、芯材2bのみを浸食して導線の先端面に最
大深さ70μmの凹部2d(図3(b)参照)を形成した。
Next, the cut surfaces 5a and 5b of the composite chip 5
Then, the insulator 3 was dissolved and removed with 2-methoxyethanol to expose each conductor wire 2 by a length of 0.02 mm (FIG. 1 (d)). Then, the conductor 2 exposed on one side of the insulator 3 is immersed in a nitric acid aqueous solution to erode only the core material 2b to form a recess 2d having a maximum depth of 70 μm on the tip surface of the conductor (see FIG. 3 (b)). Was formed.

【0047】しかる後、実施例1で用いたSn−Pb系
高温半田により、凹部2dに図1(e)に示すように半田
バンプ6を形成した。そして、実施例3と同様に、半田
バンプ6を形成した側を再び前記薬剤に浸漬して絶縁体
3を更に溶解除去し、半田バンプ6と絶縁体3との間に
導線2を0.25mm露出させ、15mm×15mm×1.5 mmの図1
(f)に示すSMC11を製造した。
Thereafter, the solder bumps 6 as shown in FIG. 1 (e) were formed in the recess 2d by the Sn-Pb type high temperature solder used in the first embodiment. Then, in the same manner as in Example 3, the side on which the solder bumps 6 were formed was again immersed in the chemical to further dissolve and remove the insulator 3, and the conductor wire 2 was exposed between the solder bumps 6 and the insulator 3 by 0.25 mm. 15mm x 15mm x 1.5mm Figure 1
The SMC11 shown in (f) was manufactured.

【0048】製造したSMC11においては、半田バンプ
6が各々の導線2の先端面上に略球状に形成され、その
形状は導線毎に同じ形状であった。このSMC11を半導
体チップと接続したところ、図4に示したように、Nb
からなる被覆材2cの上部が花ビラ状に開いた状態とな
り、各導線2と半導体チップ30の対応する電極30aとの
間が半田バンプ6の半田により良好に半田付けされてい
た。
In the manufactured SMC 11, the solder bumps 6 were formed in a substantially spherical shape on the tip surface of each conductor wire 2, and the shape was the same for each conductor wire. When this SMC11 was connected to a semiconductor chip, as shown in FIG.
The upper part of the covering material 2c made of the above was opened in a flower-villa shape, and the conductors 2 and the corresponding electrodes 30a of the semiconductor chip 30 were well soldered by the solder bumps 6.

【0049】更に、製造したSMC11を1,000 個用意
し、これらを用いて図5(a)〜図5(f)に示した手順に
より半導体チップ30と回路基板32の電極30a,32aをそ
れぞれ対応する導線2で接続した。そして、断続通電に
よる前記と同様の長期劣化試験を行い、各導線2と電極
30a,32aとの接続部における導通不良を起こしたSM
C11の個数を調べた。その結果を表1に併せて示した。 (実施例8)実施例1〜7において使用した低炭素鋼パ
イプに代えて、断面U字型の上方が開放された容器を用
いてSMCを製造した。
Further, 1,000 manufactured SMCs 11 are prepared and the electrodes 30a and 32a of the semiconductor chip 30 and the circuit board 32 are made to correspond to each other by using the prepared SMCs 11 by the procedure shown in FIGS. 5 (a) to 5 (f). Connected with a lead wire 2. Then, a long-term deterioration test similar to the above is performed by intermittent energization, and each conductor 2 and electrode
SM with poor continuity at the connection with 30a, 32a
The number of C11 was examined. The results are also shown in Table 1. (Example 8) An SMC was manufactured using a container having a U-shaped cross section and having an open upper portion, instead of the low carbon steel pipes used in Examples 1 to 7.

【0050】先ず、V溝を所定ピッチで複数形成した高
さが異なる複数のV溝駒25,26により、実施例1で使用
した直径0.08mmのリン青銅からなる複数の導線2を張力
を付与した状態で所定間隔をおいて複数の平行導線列A
W1,AW2,AW3…………に40列積層形成した。即ち、図
7(a)に示すように、溝底部の高さがh1(図7(b)参
照)のV溝25aを0.25mm間隔に40個高寸法精度に形成し
た2個のV溝駒25を所定間隔を開けて設置した。そし
て、対応する各V溝25a内に導線2を配置し、両端に取
り付けた200 gの錘27で導線2に張力を付与して平行導
線列AW1を形成した。
First, a plurality of V-groove pieces 25 and 26 having a plurality of V-grooves formed at a predetermined pitch and having different heights apply tension to the plurality of conductor wires 2 made of phosphor bronze having a diameter of 0.08 mm used in the first embodiment. A plurality of parallel conductor lines A at predetermined intervals
40 rows were laminated on W1, AW2, AW3 .... That is, as shown in FIG. 7 (a), two V-groove pieces with 40 dimensionally high V-grooves 25a having a groove bottom height of h1 (see FIG. 7 (b)) are formed at 0.25 mm intervals. Twenty-five were placed at a predetermined interval. Then, the conductor wire 2 was placed in each corresponding V groove 25a, and tension was applied to the conductor wire 2 by the weights 27 of 200 g attached to both ends to form the parallel conductor wire row AW1.

【0051】次に、図7(b)に示すように、V溝駒25の
外側にV溝26aが0.25mm間隔で40個高寸法精度に形成さ
れたV溝駒26を2個設置した。そして、対応する各V溝
26a内に導線2を配置し、両端に取り付けた200 gの錘
27で導線2に張力を付与して平行導線列AW1の上方に平
行導線列AW2を形成した。このとき、各V溝26aは、溝
底部の高さh2がV溝駒25の溝底部の高さh1より0.25mm
高く形成したので、平行導線列AW1と平行導線列AW2と
の積層間隔は0.25mmであった。
Next, as shown in FIG. 7B, two V-groove pieces 26 each having 40 V-grooves 26a formed at 0.25 mm intervals with high dimensional accuracy were set outside the V-groove pieces 25. And each corresponding V groove
A 200 g weight attached to both ends by placing the conductor 2 inside the 26a.
At 27, tension is applied to the conductor 2 to form the parallel conductor row AW2 above the parallel conductor row AW1. At this time, in each V groove 26a, the height h2 of the groove bottom is 0.25 mm higher than the height h1 of the groove bottom of the V groove piece 25.
Since they were formed high, the stacking interval between the parallel conductive wire row AW1 and the parallel conductive wire row AW2 was 0.25 mm.

【0052】以下、同様にして複数の平行導線列AW1,
AW2,AW3…………を0.25mm間隔で40列積層形成した。
このとき、複数の導線2は、V溝駒25,26の高寸法精度
に形成したV溝25a,26a内に配置したので配列方向に
精度良く位置決めできた。また、複数の平行導線列AW
1,AW2,AW3…………の積層間隔は、図7(b)に示し
たように、これらの間にスペーサー28,29を所要数介在
させて調整した。その結果、複数の導線2は、配列間隔
及び積層間隔のいずれも、250 μm±10μmの誤差内で
実質的に平行に配列させることができた。
Similarly, a plurality of parallel conducting wire rows AW1,
40 rows of AW2, AW3 ......... were formed at 0.25 mm intervals.
At this time, since the plurality of conductors 2 are arranged in the V grooves 25a, 26a formed with high dimensional accuracy of the V groove pieces 25, 26, the conductor wires 2 can be accurately positioned in the arrangement direction. Also, a plurality of parallel conductor lines AW
The stacking interval of 1, AW2, AW3, ... Was adjusted by interposing a required number of spacers 28, 29 between them as shown in FIG. 7 (b). As a result, the plurality of conductive wires 2 could be arranged substantially in parallel within the error of 250 μm ± 10 μm in both the arrangement interval and the lamination interval.

【0053】この状態で、前記容器内に絶縁体3として
液状のシリコーンゴムを流し込み、固化させて導線2及
び絶縁体3からなる図1(a)に示す複合体4を形成し
た。次に、複合体4を前記容器から抜き出し(図1
(b))、これを厚さ1.5 mmに切断して複合体チップ5と
した(同(c))。絶縁体3には、重合密度の高い付加型
シリコーンゴムを用いた。従って、複合体チップ5は、
合計1,600 本の互いに平行な導線2が厚さ方向に等間隔
に配列されている。
In this state, liquid silicone rubber was poured as an insulator 3 into the container and solidified to form a composite body 4 shown in FIG. 1 (a) consisting of the conductor 2 and the insulator 3. Next, the composite 4 is extracted from the container (see FIG.
(b)), which was cut to a thickness of 1.5 mm to obtain a composite chip 5 (the same (c)). For the insulator 3, an addition type silicone rubber having a high polymerization density was used. Therefore, the composite chip 5 is
A total of 1,600 parallel conductor wires 2 are arranged at equal intervals in the thickness direction.

【0054】次いで、複合体チップ5を2−メトキシエ
タノールの中に浸漬し、切断面5a,5bから絶縁体3
を溶解除去し、多数の導線2の端部をそれぞれ0.02mmの
長さ露出させた(図1(d))。その後、露出した多数の
導線2の一端側を半田浴に浸漬し、各々の導線2の一端
に半田バンプ6を形成し、15mm×15mm×1.5 mmの図1
(e)に示すSMC10を製造した。
Next, the composite chip 5 is dipped in 2-methoxyethanol, and the insulating surfaces 3 are cut from the cut surfaces 5a and 5b.
Was removed by dissolution, and the end portions of the many conductors 2 were exposed to a length of 0.02 mm (FIG. 1 (d)). After that, one end side of the exposed large number of conductors 2 is immersed in a solder bath to form solder bumps 6 on one end of each conductor 2, and the solder bumps 6 of 15 mm × 15 mm × 1.5 mm are formed.
The SMC10 shown in (e) was manufactured.

【0055】半田浴には、90wt%Pb,10wt%Snからな
る融点が280〜300℃のSn−Pb系高温半田を用いた。
尚、前記容器の両端面には、導線の直径と同じ寸法を有
する間隙を複数の導線と同じピッチで上下方向に設けた
くし歯を設置して、シリコーンゴムが両端面から流失す
るのを防止した。
For the solder bath, Sn-Pb type high temperature solder composed of 90 wt% Pb and 10 wt% Sn and having a melting point of 280 to 300 ° C. was used.
In addition, on both end faces of the container, comb teeth provided with gaps having the same size as the diameter of the conductor wire in the vertical direction at the same pitch as the plurality of conductor wires were installed to prevent silicone rubber from flowing off from both end faces. .

【0056】このようにして製造したSMC10を1,000
個用意し、これらを用いて図5(a)〜図5(f)に示した
前記手順により、半導体チップ30の電極30aと回路基板
32の電極32aとの間をそれぞれ対応する導線2で接続し
た。そして、実施例1〜7と同じ長期劣化試験を行い、
各導線2と電極30a,32aとの接続部における導通不良
を起こしたSMC10の個数を調べた。その結果を表1に
併せて示した。 (実施例9)絶縁体に発泡シリコーンゴムを用いた他
は、実施例8と同じ方法により15mm×15mm×1.5 mmの図
1(e)に示すSMC10を製造した。
The SMC10 produced in this way is 1,000
Individually prepared, and using these, the electrode 30a of the semiconductor chip 30 and the circuit board are obtained by the procedure shown in FIGS. 5 (a) to 5 (f).
The 32 electrodes 32a were connected to each other by corresponding conductors 2. Then, the same long-term deterioration test as in Examples 1 to 7 is performed,
The number of SMCs 10 having a conduction failure at the connection between each conductor 2 and the electrodes 30a and 32a was examined. The results are also shown in Table 1. (Example 9) An SMC 10 of 15 mm x 15 mm x 1.5 mm shown in Fig. 1 (e) was manufactured by the same method as in Example 8 except that foamed silicone rubber was used as the insulator.

【0057】このようにして製造したSMC10を1,000
個用意し、実施例8と同じ構造の半導体チップと回路基
板の電極をそれぞれ対応する導線で図5(a)〜図5(f)
に示した前記手順により接続し、実施例8と同様にして
導通不良を起こしたSMC10の個数を調べた。その結果
を表1に併せて示した。 (実施例10)実施例8で製造した図1(e)に示すSMC
10の半田バンプ6を形成した側を再び前記薬剤に浸漬し
て絶縁体3を更に溶解除去し、半田バンプ6と絶縁体3
との間に導線2を0.25mm露出させ、15mm×15mm×1.5 mm
の図1(f)に示すSMC11を製造した。
The SMC10 produced in this way is 1,000
5A to 5F are prepared by individually preparing semiconductor chips having the same structure as that of the eighth embodiment and electrodes of the circuit board with corresponding conductive wires.
The number of SMC10s that were connected according to the procedure shown in FIG. The results are also shown in Table 1. (Example 10) The SMC manufactured in Example 8 and shown in FIG.
The side on which the solder bumps 6 are formed of 10 is again immersed in the above chemical to further dissolve and remove the insulator 3, and the solder bumps 6 and the insulator 3 are removed.
Expose 0.25mm of conductor 2 between and, 15mm × 15mm × 1.5mm
SMC11 shown in FIG. 1 (f) was manufactured.

【0058】このようにして製造したSMC11を1,000
個用意し、半導体チップと回路基板の電極をそれぞれ対
応する導線で接続した。接続は図5(a)〜図5(f)に示
した手順に従った。そして、断続通電によるSMC11の
各導線2と電極30a,32aとの接続部における長期劣化
試験を行い、SMC11の各導線2と半導体チップ30の電
極30aや回路基板32の電極32aとの間で導通不良を起こ
したSMC11の個数を調べた。その結果を表1に併せて
示した。 (実施例11)絶縁体に発泡シリコーンゴムを用いた他
は、実施例10と同じ方法により図1(f)に示す15mm×15
mm×1.5mmのSMC11製造した。
The SMC11 produced in this manner is used for 1,000
Individual pieces were prepared and the electrodes of the semiconductor chip and the circuit board were connected by corresponding conductors. The connection followed the procedure shown in FIGS. 5 (a) to 5 (f). Then, a long-term deterioration test is performed on the connection between each conductor 2 of the SMC 11 and the electrodes 30a, 32a due to intermittent energization, and conduction is established between each conductor 2 of the SMC 11 and the electrode 30a of the semiconductor chip 30 or the electrode 32a of the circuit board 32. The number of defective SMC11 was examined. The results are also shown in Table 1. (Example 11) 15 mm × 15 shown in FIG. 1 (f) by the same method as in Example 10 except that foamed silicone rubber was used for the insulator.
mm × 1.5 mm SMC11 was manufactured.

【0059】このようにして製造したSMC11を1,000
個用意し、実施例10と同様にして半導体チップ30と回路
基板32の電極30a,32aをそれぞれ対応する導線2で接
続した。そして、実施例10と同様にして導通不良を起こ
したSMC11の個数を調べ、結果を表1に示した。 (実施例12)図2(b)に示した凹溝2aを形成した直径
0.08mmの導線2を用いた他は、実施例10と同じ方法で図
1(f)に示す15mm×15mm×1.5mmのSMC11を製造し
た。
The SMC11 produced in this manner is used for 1,000
Individual pieces were prepared, and in the same manner as in Example 10, the semiconductor chip 30 and the electrodes 30a, 32a of the circuit board 32 were connected by corresponding conductors 2. Then, in the same manner as in Example 10, the number of SMCs 11 in which conduction failure occurred was examined, and the results are shown in Table 1. (Embodiment 12) Diameter in which the concave groove 2a shown in FIG. 2 (b) is formed
A 15 mm × 15 mm × 1.5 mm SMC 11 shown in FIG. 1 (f) was manufactured in the same manner as in Example 10 except that the conductor wire 2 of 0.08 mm was used.

【0060】このようにして製造したSMC11を1,000
個用意し、実施例10と同様にして半
The SMC11 produced in this manner is used for 1,000
Separately prepared, half as in Example 10.

【0061】[0061]

【表1】 [Table 1]

【0062】導体チップ30の電極30aと回路基板32の電
極32aとの間をそれぞれ対応する導線2で接続した。
The electrodes 30a of the conductor chip 30 and the electrodes 32a of the circuit board 32 were connected by corresponding conductors 2.

【0063】そして、実施例10と同様にして導通不良を
起こしたSMC11の個数を調べ、果を表1に示した。 (実施例13)導線2として図2(c)に示した撚線(リン
青銅線の7本撚線,直径0.08mm)用いた他は、実施例10
と同じ方法で図1(f)に示す15mm×15mm×1.5 mmのSM
C11を製造した。
Then, in the same manner as in Example 10, the number of SMCs 11 in which conduction failure occurred was examined, and the results are shown in Table 1. Example 13 Example 10 was repeated except that the twisted wire shown in FIG. 2C (7 twisted wires of phosphor bronze wire, diameter 0.08 mm) was used as the conductor wire 2.
15mm × 15mm × 1.5mm SM shown in Fig. 1 (f) in the same way as
C11 was produced.

【0064】このようにして製造したSMC11を1,000
個用意し、実施例10と同様にして、半導体チップ30の電
極30aと回路基板32の電極32aとの間をそれぞれ対応す
る導線2で接続し、導通不良を起こしたSMC11の個数
を調べた。その結果を表1に示した。 (実施例14)図3(a)に示した直径0.08mmの複合線から
なる導線2を用いた他は、実施例10と同じ方法で図1
(f)に示す15mm×15mm×1.5mmのSMC11を製造した。
The SMC11 produced in this way is 1,000
Individual pieces were prepared, and in the same manner as in Example 10, the electrodes 30a of the semiconductor chip 30 and the electrodes 32a of the circuit board 32 were connected by corresponding conductors 2, and the number of SMCs 11 in which conduction failure occurred was examined. The results are shown in Table 1. (Example 14) The same method as in Example 10 was used except that the conducting wire 2 made of the composite wire having a diameter of 0.08 mm shown in Fig. 3 (a) was used.
The SMC11 of 15 mm × 15 mm × 1.5 mm shown in (f) was manufactured.

【0065】このようにして製造したSMC11を1,000
個用意し、実施例10と同様にして、半導体チップ30の電
極30aと回路基板32の電極32aとの間をそれぞれ対応す
る導線2で接続し、導通不良を起こしたSMC11の個数
を調べた。その結果を表1に示した。 (比較例1)それぞれ1,600 個の電極を有する前記各実
施例で使用した半導体チップ30と回路基板32とをそれぞ
れ1,000 個用意し、本発明方法で製造されたSMCを使
用することなく半田ボールにより対応する電極30a,32
a相互を直接接続した。
The SMC11 produced in this manner is 1,000
Individual pieces were prepared, and in the same manner as in Example 10, the electrodes 30a of the semiconductor chip 30 and the electrodes 32a of the circuit board 32 were connected by corresponding conductors 2, and the number of SMCs 11 in which conduction failure occurred was examined. The results are shown in Table 1. (Comparative Example 1) 1,000 semiconductor chips 30 and circuit boards 32 each having 1,600 electrodes were used and solder balls were used without using the SMC manufactured by the method of the present invention. Corresponding electrodes 30a, 32
a Directly connected to each other.

【0066】直接接続した半導体チップ30と回路基板32
とについて、断続通電による電極30a,32a相互の接続
部の長期劣化試験を行ない、導通不良を起こした半導体
チップ30と回路基板32との組数を調べた。結果を表1に
併せて示した。表1より明らかなように、本発明方法に
よって製造したコネクタは導通不良を起こしたものが少
なかった。特に、導線と絶縁体との接触面積が大きい実
施例5,6及び実施例12,13のSMC、導線の先端面を凹状
に形成して半田バンプの形状を一定にした実施例7,14の
SMC、絶縁体に発泡シリコーンゴムを用いた実施例2,
4,9,11のSMCは導通不良を起こした個数が少なく、優
れた接続特性を示した。
Directly connected semiconductor chip 30 and circuit board 32
With respect to and, a long-term deterioration test of the connection between the electrodes 30a and 32a due to intermittent energization was performed, and the number of sets of the semiconductor chip 30 and the circuit board 32 in which conduction failure occurred was examined. The results are also shown in Table 1. As is clear from Table 1, the connectors manufactured by the method of the present invention were found to have few conduction defects. In particular, the SMCs of Examples 5 and 6 and Examples 12 and 13 in which the contact area between the conductor and the insulator is large, and the solder bumps of Example 7 and 14 in which the tip end surface of the conductor is formed in a concave shape Example 2, in which foamed silicone rubber was used for the SMC and insulator,
The SMCs of 4,9,11 showed few connection failures and showed excellent connection characteristics.

【0067】これに対し、比較例1の半導体チップと回
路基板においては、導通不良を起こしたものが17個あっ
た。これは半導体チップの電極と回路基板の電極とを導
線を介さずに、半田ボールで直接接続したために、半田
部分に熱歪みが加わり、半田部分が劣化し剥離したため
である。尚、導線の張り渡し方法としては、V溝駒を用
いた場合(実施例8〜14)の方がスペーサーによる積層
間隔の調整が行えたので、目板を用いた場合(実施例1
〜7)より幾分導通不良個数が減少した。
On the other hand, in the semiconductor chip and the circuit board of Comparative Example 1, there were 17 in which conduction failure occurred. This is because the electrodes of the semiconductor chip and the electrodes of the circuit board are directly connected by the solder balls without the intermediary of conducting wires, so that thermal distortion is applied to the solder portions and the solder portions are deteriorated and peeled off. As for the method of laying the conducting wires, when the V-groove piece was used (Examples 8 to 14), the stacking interval could be adjusted by the spacers, so when the eye plate was used (Example 1)
~ 7), the number of defective conduction was reduced to some extent.

【0068】前述の実施例1〜14では、半導体チップと
回路基板の導体相互をSMCで電気接続するにあたり、
融点の異なる2種の半田を用い、半田付けを2回に分け
て行ったが、同じ融点の半田を用いて1回の半田付け操
作で半導体チップと回路基板の電極相互をSMCで電気
接続することも可能である。この場合、SMCは、図6
に示したSMC12のように、絶縁体3の両面から所定長
さ(例えば、0.25mm)露出した導線2の両端に半田バン
プ6がそれぞれ形成されたものを使用する。 (実施例15)導線を張り渡すのに断面U字型の容器とV
溝駒を用い、絶縁体として重合密度が低く、比較的フィ
ラー量の多い縮合型シリコーンゴムを用いた他は、実施
例3と同じ方法によりSMCを製造した。
In Examples 1 to 14 described above, when electrically connecting the conductors of the semiconductor chip and the circuit board to each other by SMC,
Although two kinds of solders having different melting points were used and the soldering was divided into two times, the electrodes of the semiconductor chip and the circuit board were electrically connected to each other by SMC by one soldering operation using the solder having the same melting point. It is also possible. In this case, SMC is shown in FIG.
As the SMC 12 shown in FIG. 2, the conductor 3 having the solder bumps 6 formed on both ends of the conductor 2 exposed by a predetermined length (for example, 0.25 mm) from both surfaces of the insulator 3 is used. (Embodiment 15) A container having a U-shaped cross section and a V for stretching the conductor wire
An SMC was produced by the same method as in Example 3, except that a grooved piece was used and a condensation type silicone rubber having a low polymerization density and a relatively large amount of filler was used as an insulator.

【0069】導線の張り渡しに要した時間は、目板を用
いた場合に比較して大幅に短縮され、また導線を絶縁体
から露出させる時間も、実施例3で用いた付加型シリコ
ーンゴムの約半分の時間であった。得られたSMCにつ
いて、実施例3の場合と同様にして、半導体チップ及び
回路基板の電極との間の導通性を調査した。その結果、
導通不良が発生した個数は1,000 個当たり1個であり、
発泡シリコーンゴム並みの好結果が得られた。これは、
縮合型シリコーンゴムが均一に溶解除去されたためであ
る。 (実施例16)導線を張り渡すのに断面U字型の容器とV
溝駒を用い、図8に示したように、複合体チップ5の両
面から導線2の端部を露出させ、一端面に露出した導線
2を導電性ペースト20を介して電極用の電極板22と電気
的に接続し、他端面に露出した導線2の端部に半田バン
プ6を電気めっきした他は、実施例3と同じ方法により
SMCを製造した。
The time required for laying the conductor wire is significantly shortened as compared with the case where the eye plate is used, and the time for exposing the conductor wire from the insulator is the same as that of the addition type silicone rubber used in Example 3. It was about half the time. Regarding the obtained SMC, the conductivity between the semiconductor chip and the electrodes of the circuit board was investigated in the same manner as in Example 3. as a result,
One out of every 1,000 defective connections occurs,
Good results were obtained, comparable to those of foamed silicone rubber. this is,
This is because the condensed silicone rubber was uniformly dissolved and removed. (Example 16) A container having a U-shaped cross section and a V for stretching the conductor wire
As shown in FIG. 8, a groove piece is used to expose the ends of the conductor wire 2 from both surfaces of the composite chip 5, and the conductor wire 2 exposed on one end surface is connected to the electrode plate 22 for electrodes through the conductive paste 20. SMC was manufactured by the same method as in Example 3 except that the solder bump 6 was electrically plated on the end of the conductive wire 2 exposed on the other end surface.

【0070】このとき、半田バンプ6を形成した側の導
線2の露出長さは 0.1mm、給電側の導線2の露出長さは
0.25mmとした。また、給電側の露出導線群には樹脂ペー
ストに銅粉を分散させた導電性ペースト20を塗布し、こ
のペースト20を乾燥固化した後、各導線2を電極板22と
接続した。次いで、ペースト20及び電極板22をマニキュ
ア層21で絶縁した後、露出した導線群の端部を半田電解
浴に浸漬し、陽極との間に所定の電圧を付与して半田バ
ンプ6を電気めっきした。
At this time, the exposed length of the conductor 2 on the side where the solder bumps 6 are formed is 0.1 mm, and the exposed length of the conductor 2 on the power supply side is
It was 0.25 mm. Further, a conductive paste 20 in which copper powder was dispersed in a resin paste was applied to the exposed conductive wire group on the power feeding side, and after this paste 20 was dried and solidified, each conductive wire 2 was connected to an electrode plate 22. Next, after the paste 20 and the electrode plate 22 are insulated by the nail polish layer 21, the exposed end portions of the lead wire group are immersed in a solder electrolytic bath, and a predetermined voltage is applied between the anode and the anode to electroplate the solder bumps 6. did.

【0071】得られたSMCの半田バンプ6の大きさと
バラツキを調査した。半田バンプ6は、全数が略球状で
あった。100 個の半田バンプを無作為に選び出し、その
直径を測定した。その結果、半田バンプ100 個当たりの
平均値は 120μm、標準偏差は 0.6μmであった。ま
た、実施例3の方法で製造したSMC100 個に関して同
様の測定を行った。その結果、実施例3で製造したSM
C11では、半田バンプ6の形状は大半が略球状であった
が、その直径は80〜100 μmと小さく、標準偏差は 2.7
μmと大きかった。 (実施例17)給電側の露出導線群(Auめっきしたりん
青銅線)に、導電性ペーストの代わりに、In 系半田を
付着させ、このIn 系半田に電極用金属板を直接接続し
た他は、実施例16と同じ方法により半田バンプを電気め
っきした。電気めっき終了後In 系半田を加熱して溶解
除去し、In 残差を硝酸で洗い流した。
The size and variation of the solder bumps 6 of the obtained SMC were investigated. All the solder bumps 6 were substantially spherical. We randomly selected 100 solder bumps and measured their diameters. As a result, the average value per 100 solder bumps was 120 μm, and the standard deviation was 0.6 μm. In addition, the same measurement was performed on 100 SMCs manufactured by the method of Example 3. As a result, the SM produced in Example 3
In C11, most of the solder bumps 6 had a substantially spherical shape, but the diameter was small at 80 to 100 μm, and the standard deviation was 2.7.
It was as large as μm. (Example 17) An In-based solder was adhered to the exposed conducting wire group (Au-plated phosphor bronze wire) on the power feeding side instead of the conductive paste, and the metal plate for electrodes was directly connected to this In-based solder. The solder bumps were electroplated by the same method as in Example 16. After the electroplating was completed, the In-based solder was heated and removed by melting, and the residual In was washed out with nitric acid.

【0072】得られたSMCの半田バンプは略球状で、
径が 120μmあり、標準偏差は0.45μmと実施例16の値
を下回った。また、導通試験を行ったところ不良品は皆
無であった。尚、導線の金めっき層に損傷は認められな
かった。
The obtained solder bumps of SMC are substantially spherical,
The diameter was 120 μm, and the standard deviation was 0.45 μm, which was smaller than the value of Example 16. In addition, when a continuity test was conducted, no defective products were found. No damage was found in the gold plating layer of the conductor.

【0073】[0073]

【発明の効果】以上の説明で明らかなように、本発明方
法によれば、導線に形成される半田バンプの形状が一定
し、電極と導線との接合強度が高く、使用中の熱歪みを
吸収でき、従って、半導体チップや回路基板の電極との
接続性に優れ、信頼性の高いスーパーマイクロコネクタ
が製造でき、工業上優れた効果を奏する。
As is apparent from the above description, according to the method of the present invention, the shape of the solder bump formed on the conductive wire is constant, the bonding strength between the electrode and the conductive wire is high, and the thermal strain during use is reduced. Therefore, it is possible to manufacture a highly reliable super micro connector which can be absorbed and therefore has excellent connectivity with electrodes of a semiconductor chip or a circuit board, and has an excellent industrial effect.

【0074】このとき、請求項2の方法によれば、絶縁
体と半導体チップ又は回路基板との間の熱膨張率差に起
因する熱歪みが発生しても、導線の露出部分が変形する
ことにより熱歪みが吸収されるうえ、導線が露出してい
るので放熱性も向上する。請求項3の方法によれば、絶
縁体の熱膨張による変形量を小さくでき、半導体チップ
と回路基板の各々の電極とスーパーマイクロコネクタの
導線とを半田接合する際に、電極と導線との間の位置ず
れを防止できる。
At this time, according to the method of claim 2, even if thermal strain occurs due to the difference in thermal expansion coefficient between the insulator and the semiconductor chip or the circuit board, the exposed portion of the conductive wire is deformed. Absorbs thermal strain, and since the conductor wire is exposed, heat dissipation is also improved. According to the method of claim 3, the amount of deformation due to thermal expansion of the insulator can be reduced, and when the electrodes of the semiconductor chip and the circuit board and the conductive wire of the super micro connector are soldered, the gap between the electrode and the conductive wire is reduced. Can be prevented from being displaced.

【0075】請求項4及び請求項5の方法によれば、ス
ーパーマイクロコネクタ使用中の温度上昇で絶縁体が熱
膨張しても、絶縁体が導線から剥離し難くなる。請求項
6の方法によれば、スーパーマイクロコネクタの導線に
半田バンプを所定形状に安定して形成することができ
る。請求項7の方法によれば、スーパーマイクロコネク
タ使用中の温度上昇による導線の変位をより確実に抑制
できる。
According to the methods of claims 4 and 5, even if the insulator thermally expands due to temperature rise during use of the supermicro connector, the insulator is less likely to be peeled off from the conductor wire. According to the method of claim 6, the solder bump can be stably formed in a predetermined shape on the conductor wire of the super micro connector. According to the method of claim 7, it is possible to more reliably suppress the displacement of the conductive wire due to the temperature rise during the use of the super micro connector.

【0076】請求項8の方法によれば、複数の導線の位
置決めをV溝を利用して行うので作業が容易で、複数の
導線を精度よく位置決めすることができる。請求項9の
方法によれば、各導線に張力を簡便に付与することがで
きる。請求項10の方法によれば、複数の平行導線列の積
層間隔を高精度に調整できる。
According to the method of claim 8, the V-grooves are used to position the plurality of conductors, so that the work is easy and the plurality of conductors can be accurately positioned. According to the method of claim 9, tension can be easily applied to each conductor. According to the method of claim 10, the stacking interval of the plurality of parallel conductor lines can be adjusted with high accuracy.

【0077】請求項11の方法によれば、絶縁体が薬剤に
比較的安定して短時間で均一に溶解するので、スーパー
マイクロコネクタから導線を一定の長さに露出させるこ
とができる。請求項12の方法によれば、スーパーマイク
ロコネクタに任意の大きさで均一な形状の半田バンプを
形成できる。
According to the method of claim 11, since the insulator is relatively stable and uniformly dissolved in the drug in a short time, the conductor wire can be exposed to a certain length from the super micro connector. According to the method of claim 12, solder bumps of arbitrary size and uniform shape can be formed on the super micro connector.

【0078】請求項13の方法によれば、スーパーマイク
ロコネクタの複数の導線の各端部に任意の大きさの半田
バンプを均一、且つ容易に形成することができる。請求
項14の方法によれば、スーパーマイクロコネクタの複数
の導線への給電を均等に行うことができる。請求項15の
方法によれば、導線と絶縁体との接触面積が増加して固
着力が向上し、スーパーマイクロコネクタの信頼性を高
めることができる。
According to the method of claim 13, solder bumps of any size can be uniformly and easily formed at each end of the plurality of conductors of the supermicro connector. According to the method of claim 14, it is possible to uniformly supply power to the plurality of conductive wires of the supermicro connector. According to the method of claim 15, the contact area between the conductor and the insulator is increased, the fixing force is improved, and the reliability of the super micro connector can be enhanced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のスーパーマイクロコネクタの製造方法
を概略的に説明する工程図である。
FIG. 1 is a process diagram schematically illustrating a method for manufacturing a super micro connector of the present invention.

【図2】本発明方法で用いる導線の形状を示す斜視図で
ある。
FIG. 2 is a perspective view showing the shape of a conductive wire used in the method of the present invention.

【図3】本発明方法で用いる導線の端部を腐食剤で浸食
した状態を示す斜視図である。
FIG. 3 is a perspective view showing a state in which an end portion of a conductive wire used in the method of the present invention is corroded with a corrosive agent.

【図4】図3に示した導線を用いたスーパーマイクロコ
ネクタの半田付け後の状態を示す縦断面図である。
FIG. 4 is a vertical cross-sectional view showing a state after soldering of a super micro connector using the conductor wire shown in FIG.

【図5】本発明方法で製造したスーパーマイクロコネク
タを用いて半導体チップと回路基板とを接続するときの
工程図である。
FIG. 5 is a process diagram for connecting a semiconductor chip and a circuit board using a super micro connector manufactured by the method of the present invention.

【図6】本発明方法で製造したスーパーマイクロコネク
タの他の態様を示す正面図である。
FIG. 6 is a front view showing another embodiment of the super micro connector manufactured by the method of the present invention.

【図7】複数の導線をV溝駒を用いて張り渡す状態を示
す説明図である。
FIG. 7 is an explanatory diagram showing a state in which a plurality of conducting wires are stretched using a V-groove piece.

【図8】複合体チップの複数の導線に半田バンプを電気
めっきする状況を示す断面図である。
FIG. 8 is a cross-sectional view showing a situation in which solder bumps are electroplated on a plurality of conductive wires of a composite chip.

【符号の説明】[Explanation of symbols]

1 角パイプ 2 導線 2a 凹溝 2b 芯材 2c 被覆材 2d 凹部 3 絶縁体 4 複合体 5 複合体チップ 6,7 半田バンプ 10,11,12 スーパーマイクロコネクタ(SM
C) 20 導電性ペースト 21 マニキュア層 22 電極板 25,26 V溝駒 25a,26a V溝 27 錘 28,29 スペーサ 30 半導体チップ 30a 電極 32 回路基板 32a 電極 AW1,AW2 平行導線列
1 Square pipe 2 Conductive wire 2a Groove 2b Core material 2c Covering material 2d Recess 3 Insulator 4 Composite 5 Composite chip 6,7 Solder bump 10,11,12 Super micro connector (SM
C) 20 Conductive paste 21 Manicure layer 22 Electrode plate 25,26 V-groove piece 25a, 26a V-groove 27 Weight 28,29 Spacer 30 Semiconductor chip 30a Electrode 32 Circuit board 32a Electrode AW1, AW2 Parallel conducting wire row

Claims (15)

【特許請求の範囲】[Claims] 【請求項1】 実質的に平行に配列した複数の導線を、
これらの間に介在させた弾性を有する絶縁体で固定して
導線と絶縁体からなる複合体を作製する工程、 この複合体を前記導線と直交する面で切断して複数の複
合体チップを作製する工程、前記各複合体チップの少な
くとも一方の切断面から前記絶縁体を薬剤にて溶解除去
し、前記複数の導線の端部を所定長さ露出させる工程、 露出した前記各導線の端部に半田バンプを形成する工程
を備えたことを特徴とするスーパーマイクロコネクタの
製造方法。
1. A plurality of conductive wires arranged substantially in parallel,
A step of producing a composite body composed of a conductor and an insulator by fixing it with an elastic insulator interposed therebetween, and producing a plurality of composite chips by cutting the composite body in a plane orthogonal to the conductor wire. The step of dissolving and removing the insulator with a chemical from at least one cut surface of each of the composite chips, and exposing the end portions of the plurality of conductive wires to a predetermined length, at the exposed end portions of each conductive wire. A method for manufacturing a super micro connector, comprising a step of forming solder bumps.
【請求項2】 露出した前記各導線の端部に半田バンプ
を形成する工程の後に、前記半田バンプを形成した側の
前記絶縁体を薬剤にて更に溶解除去し、前記半田バンプ
と前記絶縁体の間に前記複数の導線を所定長さ露出させ
る工程を備えた、請求項1のスーパーマイクロコネクタ
の製造方法。
2. After the step of forming solder bumps on the exposed ends of each of the conductive wires, the insulator on the side on which the solder bumps are formed is further dissolved and removed with a chemical agent to remove the solder bumps and the insulator. The method for manufacturing a super micro connector according to claim 1, further comprising the step of exposing the plurality of conductive wires for a predetermined length between the two.
【請求項3】 弾性を有する絶縁体が発泡シリコーンゴ
ムである、請求項1又は2のスーパーマイクロコネクタ
の製造方法。
3. The method for producing a super micro connector according to claim 1, wherein the elastic insulator is foamed silicone rubber.
【請求項4】 導線の表面に、開口部の幅が狭く内部の
幅が広い凹溝を所要数、直線状又は螺旋状に形成する、
請求項1乃至3いずれかのスーパーマイクロコネクタの
製造方法。
4. A required number of recessed grooves having a narrow opening and a wide inner width are formed on the surface of the conductor wire in a linear or spiral shape.
A method for manufacturing a super micro connector according to claim 1.
【請求項5】 導線に、撚線又は複数本の線材を表面に
凹凸が形成されるように集合し接合した複合線を用い
る、請求項1乃至3いずれかのスーパーマイクロコネク
タの製造方法。
5. The method for producing a super micro connector according to claim 1, wherein a twisted wire or a composite wire obtained by assembling and joining a plurality of wire rods so that unevenness is formed on the surface is used as the conductive wire.
【請求項6】 導線に、所定の腐食剤に浸食される芯材
と、前記腐食剤に対して非浸食性の被覆材からなる複合
線を用いる、請求項1乃至3いずれかのスーパーマイク
ロコネクタの製造方法。
6. The supermicro connector according to claim 1, wherein a composite wire comprising a core material that is corroded by a predetermined corrosive agent and a coating material that is non-corrosive to the corrosive agent is used as the conductive wire. Manufacturing method.
【請求項7】 弾性を有する絶縁体に導線を接着剤によ
り接着する、請求項1乃至6いずれかのスーパーマイク
ロコネクタの製造方法。
7. The method for manufacturing a super micro connector according to claim 1, wherein the conductor is adhered to an elastic insulator with an adhesive.
【請求項8】 実質的に平行に配列した複数の導線を、
これらの間に介在させた弾性を有する絶縁体で固定して
導線と絶縁体からなる複合体を作製する工程において、 V溝を所定ピッチで複数形成した高さが異なる複数の部
材により、前記複数の導線を張力を付与した状態で所定
間隔をおいて複数の平行導線列に積層形成する、請求項
1乃至3いずれかのスーパーマイクロコネクタの製造方
法。
8. A plurality of wires arranged substantially in parallel,
In the step of producing a composite body composed of a conductor and an insulator by fixing it with an insulating material having elasticity interposed between these, the plurality of V grooves are formed at a predetermined pitch, 4. The method for manufacturing a super micro connector according to claim 1, wherein the conductor wire is laminated on a plurality of parallel conductor wire rows at a predetermined interval in a tensioned state.
【請求項9】 前記各導線は、端部に取り付けた錘によ
り張力が付与される、請求項8のスーパーマイクロコネ
クタの製造方法。
9. The method for manufacturing a super micro connector according to claim 8, wherein tension is applied to each of the conductive wires by a weight attached to an end thereof.
【請求項10】 前記平行導線列の積層間隔を、前記平
行導線列間に介在させるスペーサーにより調整する、請
求項8又は9のスーパーマイクロコネクタの製造方法。
10. The method for manufacturing a supermicro connector according to claim 8, wherein a stacking interval of the parallel conductor lines is adjusted by a spacer interposed between the parallel conductor lines.
【請求項11】 弾性を有する絶縁体として縮合型シリ
コーンゴムを用いる、請求項1又は2のスーパーマイク
ロコネクタの製造方法。
11. The method for producing a super micro connector according to claim 1, wherein a condensation type silicone rubber is used as the elastic insulator.
【請求項12】 前記各複合体チップの少なくとも一方
の切断面から前記絶縁体を薬剤にて溶解除去し、前記複
数の導線の端部を所定長さ露出させる工程及び露出した
前記各導線に半田バンプを形成する工程において、 前記各複合体チップの両切断面に前記複数の導線の端部
を露出させ、一方の切断面に露出した前記複数の導線を
電極用金属板と電気的に接続し、他方の切断面に露出し
た前記複数の導線に半田バンプを電気めっきで形成す
る、請求項1乃至3いずれかのスーパーマイクロコネク
タの製造方法。
12. A step of dissolving and removing the insulator with a chemical from at least one cut surface of each of the composite chips to expose end portions of the plurality of conductive wires by a predetermined length, and soldering to each of the exposed conductive wires. In the step of forming a bump, the ends of the plurality of conductive wires are exposed on both cut surfaces of each composite chip, and the plurality of conductive wires exposed on one cut surface are electrically connected to a metal plate for electrode. The method for manufacturing a super micro connector according to claim 1, wherein solder bumps are formed on the plurality of conductive wires exposed on the other cut surface by electroplating.
【請求項13】 前記複合体チップの一方の切断面に、
露出した前記複数の導線も含めて導電性ペーストを塗布
し、該ペースト表面を絶縁被覆した後、一方の切断面に
露出した前記複数の導線及び前記導電性ペーストを電源
と接続した導体に接触させて給電することにより、他方
の切断面に露出した前記複数の導線に半田バンプを電気
めっきで形成する、請求項12のスーパーマイクロコネク
タの製造方法。
13. On one cut surface of the composite chip,
A conductive paste including the exposed plurality of conductive wires is applied, and the paste surface is insulation-coated, and then the conductive wires and the conductive paste exposed on one cut surface are brought into contact with a conductor connected to a power source. 13. The method for manufacturing a super micro connector according to claim 12, wherein solder bumps are formed by electroplating on the plurality of conductive wires exposed on the other cut surface by supplying electric power.
【請求項14】 前記複数の導線が金線又は金被覆導線
である、請求項1乃至3いずれかのスーパーマイクロコ
ネクタの製造方法。
14. The method for manufacturing a super micro connector according to claim 1, wherein the plurality of conductive wires are gold wires or gold-coated conductive wires.
【請求項15】 前記複数の導線の表面が電解処理又は
化学的エッチングにより粗面に形成されている、請求項
1乃至3いずれかのスーパーマイクロコネクタの製造方
法。
15. The method for manufacturing a super micro connector according to claim 1, wherein the surfaces of the plurality of conductive wires are roughened by electrolytic treatment or chemical etching.
JP28549794A 1994-01-13 1994-11-18 Manufacture of super-micro connector Pending JPH0883662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28549794A JPH0883662A (en) 1994-01-13 1994-11-18 Manufacture of super-micro connector

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP1588394 1994-01-13
JP16172894 1994-07-14
JP6-161728 1994-07-14
JP6-15883 1994-07-14
JP28549794A JPH0883662A (en) 1994-01-13 1994-11-18 Manufacture of super-micro connector

Publications (1)

Publication Number Publication Date
JPH0883662A true JPH0883662A (en) 1996-03-26

Family

ID=27281176

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28549794A Pending JPH0883662A (en) 1994-01-13 1994-11-18 Manufacture of super-micro connector

Country Status (1)

Country Link
JP (1) JPH0883662A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100473311B1 (en) * 1996-10-10 2006-04-28
JP2009224682A (en) * 2008-03-18 2009-10-01 Fujitsu Ltd Semiconductor device
JP2019161024A (en) * 2018-03-14 2019-09-19 日本電気株式会社 Bonding material, bonding structure, forming method, and manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100473311B1 (en) * 1996-10-10 2006-04-28
JP2009224682A (en) * 2008-03-18 2009-10-01 Fujitsu Ltd Semiconductor device
JP2019161024A (en) * 2018-03-14 2019-09-19 日本電気株式会社 Bonding material, bonding structure, forming method, and manufacturing method

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