JPH0878604A - Lead frame for semiconductor device - Google Patents

Abstract

PURPOSE: To easily obtain an end point of an inner lead having higher position accuracy without increasing man-hours to provide a higher yield in the wire bonding process. CONSTITUTION: An internal stress at the end point is equally distributed to prevent deformation of an inner lead 1 due to distortion and improve the yield in the connecting process of a fine metal lead by executing the coining so that an external boundary surface of the coining area 3 at the end part of the inner lead 1 is located perpendicular to the center axis in the longitudinal direction of inner lead 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device lead frame, and more particularly to a semiconductor device lead frame having a coining area at the inner lead tips.

[0002]

2. Description of the Related Art Conventionally, this kind of semiconductor device lead frame (hereinafter referred to as L / F) has a plurality of leads and a semiconductor element mounting portion formed by a punching die, and then has electrodes of the semiconductor element and inner leads. In order to improve the yield of the connecting process of the thin metal wires that connect to each other, coining (flat pressing) is performed to widen the width and maintain flatness to form a coining area. As a coining method, as shown in FIG.
The tip ends of the plurality of inner leads 1 are provided with a length of about 0.5 to 1.0 mm so that the outer boundaries of the coining areas 3 are parallel to the respective sides of the semiconductor element mounting portion 2.

However, in this type of L / F, the outer boundary of the coining area 3 is uniformly parallel to each side of the semiconductor element mounting portion 2 regardless of the shape of each inner lead 1. Since the inner lead 1 is formed, the inner lead 1 is distorted due to the internal stress caused by the coining performed on the inner lead 1, and the positional accuracy in the height direction of the tip portion greatly varies. There was a problem that the yield rate was poor.
Specifically, in the 160-pin QFP L / F, the variation in the height direction of the tip portion is 180 μm at maximum in the (+) direction, (−)
Direction, the maximum defect rate was 150 μm, and the defective rate per 10,000 wires was about 2%.

To solve this problem, Japanese Patent Laid-Open No. 4-5
In the 7347 publication, the inner ends of a large number of inner leads are provided in the vicinity of the inner end part including the connecting part of the L / F inner end where a plurality of inner leads are integrally connected, or the connecting part of the L / F inner end. Is coined on the inner lead coining area 3 defined by the outer position on the outer side and the outer position on the outer side, and the coining is performed after the L / F is coined. It proposes a method for manufacturing an L / F that eliminates the internal stress at the time.

[0005]

The above-mentioned L / F is annealed after coining, so that the entire L / F is softened, so that the L / F can be handled during the subsequent plating process and connection part cutting process and during transportation. There is a problem that deformation of F is likely to occur.

Further, an additional annealing step is required, and L /
There is also a problem that man-hours for heating and cooling F are increased.

An object of the present invention is to easily obtain a tip portion of an inner lead having high positional accuracy without increasing man-hours.
An object of the present invention is to provide a lead frame for a semiconductor device, which can obtain a high yield in the wire bonding process.

[0008]

SUMMARY OF THE INVENTION According to the present invention, a planar rectangular semiconductor element mounting portion on which a semiconductor element is mounted, hanging pins for supporting the semiconductor element mounting portion at four corners, and a space around the semiconductor element mounting portion are provided. In a lead frame for a semiconductor device having a plurality of inner leads arranged with a plurality of inner leads and coining areas formed at respective tip portions of the plurality of inner leads, an outer boundary of the coining area is a longitudinal direction of the inner leads. It is formed perpendicular to the central axis of the direction.

[0009]

Embodiments of the present invention will now be described with reference to the drawings.

FIGS. 1 (a) and 1 (b) are a plan view of a main part of an embodiment of the present invention and a partially enlarged perspective view of a coining area thereof. In the present embodiment, as shown in FIGS. 1 (a) and 1 (b), first, a semiconductor element mounting portion 2 for mounting a semiconductor element having a planar rectangular shape is punched by an L / F punching die, and a plurality of semiconductor element mounting portions 2 are provided around the semiconductor element mounting portion 2. The inner lead 1 is formed. The semiconductor element mounting portion 2 is supported by suspension pins 4 at the four corners. Next, coining is performed on the coining area 3 at the tip of the inner lead 1 to widen the width of the inner lead 1 in order to improve the yield in the process of connecting the metal wire between the electrode of the semiconductor element and the inner lead 1 and to maintain the flatness. Give. The coining is performed so that the outer boundary surface of the coining area 3 is perpendicular to the central axis of the inner lead 1 in the longitudinal direction.

By forming the coining area 3 in this way, the internal stress at the tip end portion due to the coining is evenly distributed with respect to the central axis in the longitudinal direction, and the deformation of the tip end portion of the inner lead 1 due to strain is reduced, and the 160 pin L for QFP
In the case of / F, the variation in the height direction of the tip was 180 μm at maximum in the (+) direction and 150 μm in the (−) direction to 90 μm at maximum in the (+) direction and 60 μm in the (−) direction.
The defect rate of about 2% per 10,000 wires can be drastically reduced to about 0.05%.

[0012]

As described above, according to the present invention, the tip of the inner lead is coined so that the outer boundary surface of the coining area is perpendicular to the longitudinal center axis of the inner lead. There is an effect that the internal stress is evenly distributed to prevent the inner leads from being deformed due to strain and to improve the yield of the metal thin wire connection process.

[Brief description of drawings]

1A and 1B are a plan view of a main part of an embodiment of the present invention and a partially enlarged perspective view of a coining area thereof.

2A and 2B are a plan view of a main part of an example of a conventional L / F and a partially enlarged perspective view of a coining area thereof.

[Explanation of symbols]

 1 Inner lead 2 Semiconductor element mounting part 3 Coining area 4 Hanging pin

Claims (1)

[Claims] 1. A flat rectangular semiconductor element mounting portion on which a semiconductor element is mounted, suspension pins for supporting the semiconductor element mounting portion at four corners, and a plurality of spacing pins arranged around the semiconductor element mounting portion at intervals. In a lead frame for a semiconductor device having an inner lead and a coining area formed at each tip of the plurality of inner leads,
A lead frame for a semiconductor device, wherein an outer boundary of the coining area is formed perpendicularly to a central axis in a longitudinal direction of the inner lead.