JPH0876731A - Frame memory writing control circuit and its method - Google Patents

Abstract

PURPOSE: To greatly simplify a circuit for forming the perpendicular direction address of a frame memory necessary at the time of writing interlace signals into the frame memory. CONSTITUTION: This frame memory writing control circuit has an H address forming circuit which forms and outputs the address in the horizontal direction of the frame memory in order to write the interlace signals thinned with a prescribed thinning rate into the frame memory and a V address forming circuit which forms and outputs the address in the vertical direction. The V address forming circuit has a ROM 3 in which an address table having the vertical direction address corresponding to the thinning rate is stored. The vertical direction address of the frame memory is formed and outputted by referencing to this address table.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video device for synthesizing a non-interlaced video signal and an interlaced video signal and outputting the non-interlaced video signal to a monitor as the non-interlaced video signal. The present invention relates to a frame memory write control circuit and its method for writing the interlaced video signal in a frame memory in order to convert the interlaced video signal into the frame memory.

[0002]

2. Description of the Related Art In a conventional frame memory write control circuit, in order to convert an interlaced video signal into a non-interlaced video signal, when writing the interlaced video signal into the frame memory, the vertical address of the frame memory is written. Required a complex logic circuit to generate.

In order to display a video screen on a personal computer screen on a monitor, this conventional frame memory write control circuit is an analog R which is a non-interlaced video signal.
When applied to a video device with a superimpose function that synthesizes a GB signal (output from a personal computer, etc.) and an NTSC signal (video output) that is an interlaced video signal after thinning and outputs it as a non-interlaced signal on a monitor Will be described with reference to FIG.

FIG. 5 is a block diagram showing the configuration of a general video apparatus with a superimpose function. The sync separation circuit 4 extracts a sync signal which is a reference of control timing from the NTSC signal. The extracted sync signals are the vertical sync signal Vs and the horizontal sync signal Hs, which represent the start positions of the video signals of one field and one line, respectively.
Further, the sync separation circuit 4 is provided with a clock generation means and generates a dot clock DCK which is also a sync signal for each dot.

The field determination circuit 5 is a sync separation circuit 4
Based on the synchronization signals Vs and Hs output from
Field of TSC signal is ODD (odd number) or EVEN
(Even number) is determined. An interlaced signal such as an NTSC signal has one frame (one screen) including an ODD field and an EVEN field, and the ODD field is
It is composed of video signals of odd lines of 1, 3, 5, ... Of one screen, and the EVEN field is 2, 4, 6, ...
・ It is composed of video signals of even lines.

The A / D converter 6 receives the input NTS
The C signal is converted into a digital signal (hereinafter referred to as NTSC signal data) according to the sampling clock WCK output from the thinning clock generation circuit 7.

Fifo (First in first)
out) The memory 8 is written with NTSC signal data according to the write clock WCK output from the thinning clock generation circuit 7, and is sequentially read out according to the read clock (not shown) output from the thinning clock generation circuit 7 on a first-in first-out basis. Be done. Then, inside the Fifo memory 8, the NTSC signal data is thinned according to the write clock WCK output from the thinning clock generation circuit 7 at the time when the NTSC signal data is written into the Fifo memory 8, and the lines and E constituting the ODD field and
The lines forming the VEN field are clearly separated from each other.

The thinning clock generation circuit 7 outputs the NSC signal data N before it is written in the Fifo memory 8.
Thinning processing is performed on the TSC signal data at a preset thinning rate. For example, in the case of thinning to 1/3, the frequency of the write clock WCK is 1 / th of that in the case where thinning is not performed.
By setting it to 3, the NTSC signal data is thinned out in the horizontal direction at a rate of 1/3. In the vertical direction, O
In each of the DD field and the EVEN field, thinning can be performed by applying the write clock WCK only to the line to be written in the Fifo memory 8.

The frame memory write control circuit 9 uses Fif
o NTSC signal data in the memory 8 is transferred to the frame memory 1
An H address (horizontal address) and a V address (vertical address) for writing 0 are generated.

The frame memory 10 is a Fifo memory 8
The NTSC signal data read from is written by the write clock WE output from the frame memory write control circuit 9 and read by the read clock RE output from the read control circuit 11. Here, the write clock WE and the read clock RE may be asynchronous.
Also, in the frame memory 10, the NTSC to be written
The signal data is managed by the H address and V address output from the frame memory write control circuit 9.

The read control circuit 11 extracts a sync signal from the input analog RGB signal, and generates and outputs a read clock RE synchronized with the sync signal. That is, the NTSC signal data in the frame memory 10 is read by the read clock RE, but the read timing at that time must be synchronized with the analog RGB signal.

The D / A converter 12 converts the NTSC signal data read from the frame memory 10 into an analog signal.

The switching control circuit 13 inputs the analog RGB signals and the N signals read from the frame memory 10.
The TSC signal is switched and controlled so that the NTSC signal is displayed in a predetermined rectangular area in the analog RGB screen on the monitor.

In the video device with the superimposing function having such a configuration, the NTSC signal data thinned by the write clock WCK output from the thinning clock generation circuit 7 at the preset thinning rate is stored in the frame memory. It is written in the frame memory 10 according to the H address and the V address output from the write control circuit 9. The NTSC signal data written in the frame memory 10 is read by the read clock RE output from the read control circuit 11 and converted into an analog signal by the D / A converter 12, and then the switching control circuit 13
Is displayed in a predetermined rectangular area on the analog RGB screen.

Next, the configuration of the thinned clock generation circuit will be described with reference to FIGS. 5 and 6.

The decimation clock generation circuit decimates the NTSC signal data output from the A / D converter 6 at a preset decimation rate and writes it in the Fifo memory 8 so as to determine the fetch timing of the NTSC signal data. The clock WCK is output.

FIG. 6 is a block diagram showing the configuration of the thinned-out clock generating circuit. The ternary counter 14 and the quaternary counter 15 count up in accordance with the timing of the horizontal synchronizing signal Hs, and the count value thereof is determined by the logic circuit 16.
Output to. Here, the ternary counter 14 is used when the preset thinning rate is 1/3 or 2/3.
The advance counter 15 is used when the preset thinning rate is 1 / 2n.

Based on the count value output from the ternary counter 14 or the quaternary counter 15, the logic circuit 16 has timing corresponding to whether the data to be written in the Fifo memory 8 is the ODD field or the EVEN field. Outputs a write clock in the vertical direction.

Further, the ternary counter 17 and the quaternary counter 18 count up in accordance with the timing of the dot clock DCK, and the count values are counted by the logic circuit 19
Output to. Ternary counter 17 or quaternary counter 18
Which of these is used is as described above.

The logic circuit 19 outputs a horizontal write clock based on the count value output from the ternary counter 17 or the quaternary counter 18.

The AND gate 20 receives the write clock in the vertical direction and the write clock in the horizontal direction, and the write clock WCK for thinning out the NTSC signal data output from the A / D converter 6 at a predetermined thinning rate. Is output.

Next, a method of thinning out NTSC signal data will be described with reference to FIGS.

FIG. 7 is a diagram showing an overall image of an NTSC signal for one frame. 8 and 9 show Fif
It is a figure which shows the NTSC signal data after thinning which was written in the o memory. 10 and 11 are diagrams for explaining the output timing of the write clock WCK in the ODD field and the EVEN field, respectively.

First, vertical thinning will be described.

Since the NTSC signal is an interlaced signal, it is input to the A / D converter 6 in the order of the lines forming the ODD field and the lines forming the EVEN field. That is, in FIG. 7, A to V each represent NTSC signal data for one line,
First, the lines A, C, ... Constituting the ODD field
, U are input, and then the lines B, D, ..., V that make up the EVEN field are input. And
For example, when thinning out NTSC signal data output from the A / D converter 6 at a decimation rate of 1/3 or 2/3, the lines indicated by ○ are taken in and the lines indicated by × are discarded. It will be. When the NTSC signal data decimated in this way is written in the Fifo memory 8, as shown in FIG. 8 or 9, the lines forming the ODD field are first stored, and then the lines forming the EVEN field are stored.

Here, if the thinning rate is set to 1/3, the lines forming the ODD field input first are in the order of A, C, E ...
, The lines to be captured are A, G, M and S. That is, as shown in FIG. 10, when both the upper bit and the lower bit of the count value output from the ternary counter 14 of the thinning clock generation circuit become 0, if the write clock WCK is output, the lines A and G are output. , M, S will be taken in. Similarly, in the case of the EVEN field, as shown in FIG. 11, if the write clock WCK is output at the timing when the count value output from the ternary counter 14 is 0 for the upper bit and 1 for the lower bit, the line D, J, P, V will be taken in.

Regarding thinning in dot units, that is, horizontal thinning, for example, when the thinning rate is set to 1/3, both the upper bit and the lower bit of the ternary counter 17 are 0. The write clock may be output at the following timing.

Next, an H address generating circuit and a V address generating circuit forming the conventional frame memory write control circuit will be described with reference to FIGS. 12 and 13.

The H address generation circuit outputs the H address for managing the NTSC signal data in dot units, that is, the horizontal direction when writing the NTSC signal data to the frame memory 10, and the V address generation circuit , When outputting the NTSC signal data to the frame memory 10, it outputs a V address for managing the vertical NTSC signal data.

NTSC written in Fifo memory 8
As described above, in the signal data, the line forming the ODD field and the line forming the EVEN field are completely separated, and the frame memory 1 is kept in this order.
If the NTSC signal data is transmitted to 0, the image is not restored. That is, as shown in FIG. 3 or FIG. 4, the NTSC signal data must be written in the frame memory 10 so that the lines forming the ODD field and the lines forming the EVEN field are alternately arranged like the original NTSC signal. . But horizontally (in dots)
It is not necessary to rearrange the NTSC signal data of, and the NTSC signal data may be written in the frame memory 10 in the order saved in the Fifo memory 8.

FIG. 12 is a block diagram showing the structure of an H address generation circuit for outputting an H address for horizontally managing the NTSC signal data written in the frame memory. The counter 21 is driven from 0 to 1 by the dot clock DCK. The H address is output to the frame memory 10 while counting up to 2, ... The count value, that is, the H address is also output to the clear control circuit 22, and the clear control circuit 22 outputs a clear signal to the counter 21 when the count value reaches a predetermined value. Upon receiving the clear signal, the counter 21 returns the count value to 0.

For example, when transferring an image of 100 × 100 dots to the frame memory 10, the counter 21 is set to 0.
Counting 100 dots from 1 to 99, that is, outputting the H address, is cleared to 0 again by the clear control circuit 22. Here, the H address generation circuit outputs a count up signal for incrementing the V address to the V address generation circuit in order to transfer the image of the next line to the frame memory 10 when the count value is cleared. To do. Here, the thinning rate signal is input to set the number of dots in the horizontal direction.

As described above, the H address can be realized by a simple counter increment operation.
A complicated operation is required for the V address. For example, when the thinning rate is set to 2/3, the lines A, E, G, which form the ODD field in the Fifo memory 8
K ... are V addresses 0, 3 of the frame memory 10,
Must be transferred to 4, 7 ... E
The lines composing the VEN field must be rearranged in the same manner.

FIG. 13 is a block diagram showing the configuration of the V address generation circuit. The switching circuit 23 is based on the field type and the preset thinning rate based on the ODD / EVEN determination signal output from the field determination circuit. Then, the switching signal is output to the address addition circuit 24 in synchronization with the count-up signal output from the H address generation circuit. The address addition circuit 24 selects the number of additions to be added to the V address based on the switching signal output from the switching circuit 23, and outputs it to the addition circuit 25. The addition circuit 25 adds the number of additions output from the address addition circuit 24 in synchronization with the count-up signal output from the H address generation circuit, and outputs the added value as a V address. The clear control circuit 26 counts the number of lines according to the thinning rate and then clears the added value in the adding circuit 25.

Next, the operation of the V address generation circuit is shown in FIG.
Will be described with reference to.

When the thinning rate is set to 2/3, ODD
In the field, first, the first line A is written in the position of V address 0 of the frame memory 10.
Next, the switching circuit 23 outputs a switching signal in synchronization with the count-up signal output from the H address generation circuit, and switches the number of additions to be added to the V address in the address addition circuit 24 to 3. Then, in the adder circuit 25, the addition value 3 obtained by adding the addition number 3 to the V address 0 in which the line A is written is generated as the V address, and the line E is written in the position of the V address 3 in the frame memory 10. Next, the switching circuit 23 outputs the switching signal again in synchronization with the count-up signal, and the address adding circuit 24
The number of additions to be added to the V address at is switched to 1. Then, in the adder circuit 25, an addition value 4 obtained by adding the addition number 1 to the V address 3 in which the line E is written is generated as a V address, and the line G is written in the position of the V address 4 in the frame memory 10. In this way, by switching the number of additions in the address addition circuit 24 to 3, 1, 3, 1, 3, ... By the switching signal output from the switching circuit 23, the data of the ODD field becomes a desired V address. Written.

In addition, when the lines forming the EVEN field are written in the frame memory 10, the number of additions in the address adder circuit 24 is set to 1, 3, 1, 3, 1 ,. .. can be written to a desired V address by switching to.

When the thinning rate is set to 1/3, O
When writing the lines forming the DD field and the lines forming the EVEN field in the frame memory 10, the number of additions in the address adding circuit 24 may be fixed to 2 and the same operation as described above may be performed.

In this way, the data sequence for converting the NTSC signal, which is an interlaced signal, into a non-interlaced signal is rearranged according to the H address and V address output from the frame memory write control circuit. .

[0040]

In the conventional frame memory write control circuit, when the vertical address (V address) for managing the image data in the frame memory is generated, it corresponds to the preset thinning rate. There is a problem that a complicated logic circuit is required.

[0041]

In order to solve the above problems, the present invention writes the interlaced signals decimated at a predetermined decimation rate into a frame memory by changing the horizontal address of the frame memory. In a frame memory write control circuit including an H address generating circuit for generating and outputting and a V address generating circuit for generating and outputting a vertical address, the V address generating circuit is an address having a vertical address corresponding to a thinning rate. The storage means for storing the table is provided, and the vertical address of the frame memory is generated and output by referring to the address table.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, one embodiment of the present invention will be described in detail with reference to the drawings.

The difference between the frame memory write control circuit of the present embodiment and the conventional frame memory write control circuit is that the V address generation circuit for generating the V address is preset in the conventional frame memory write control circuit. However, the V address generation circuit in the frame memory write control circuit of the present embodiment has an address table having V addresses for each thinning rate in advance. A storage means such as a stored ROM is provided, and when a V address is generated, it can be easily generated by referring to this address table. Therefore, other configurations are the same, and the description of the overlapping parts will be omitted.

Next, the V address generating circuit of this embodiment will be described with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of the V address generating circuit of this embodiment, and FIG. 2 is a diagram showing the internal configuration of the ROM.

In FIG. 1, the counter 1 sequentially counts from 0 to 1, 2, ... In response to the count-up signal output from the H address generation circuit shown in FIG. The clear control circuit 2 clears the count value of the counter 1 after counting the number of lines according to the thinning rate. The ROM 3 stores in advance an address table having V addresses for each thinning rate, and outputs V addresses based on the preset thinning rate and the count value output from the counter 1.

Next, the operation of the V address generation circuit will be described. From the H address generation circuit shown in FIG.
As described above, the count-up signal for incrementing the V address is output to the V address generation circuit every time the H address of one line is generated.
In the V address generation circuit, the count-up signal is counted by the counter 1, and this count value is stored in the ROM.
3 is output. Then, the address table to be referred to is determined based on the preset thinning rate, and based on the count value output from the counter 1, which V address in the address table should be output is determined.

That is, the ROM 3 stores an address table having V addresses for each thinning rate set in advance, but a three-digit address table itself is designated to read V addresses from a plurality of address tables. The address of is specified. Of these three-digit addresses, the upper address is determined by a preset thinning rate and specifies the address table. The lower address is determined by the count value output from the counter 1 and specifies each V address in each address table.

Next, the operation of this embodiment will be described, for example, when the thinning rate is set to 2/3.

As shown in FIG. 2, by setting the thinning rate to 2/3, the upper address in the ROM 3 becomes 1, and the address table corresponding to the thinning rate 2/3 is designated. Then, as described in the section of the prior art (see FIG. 4), the lines A, E, G, K, ... Of the ODD field in the Fifo memory have the V addresses 0, 3, 4, 7, ... .. will be sorted and written respectively. Initially, since the counter value of the counter 1 which constitutes the V address generation circuit is 0, the lower address in the ROM 3 is 00. Therefore, line A is
It will be written to the V address 0 designated by the 3-digit address 100. Next, the count-up signal output from the H address generation circuit causes the count value of the counter 1 constituting the V address generation circuit to become 1. That is, the lower address in the ROM 3 is 01, and the line E is written to the V address 3 designated by the 3-digit address 101. Similarly, line G has V address 4
At the same time, line K is written to V address 7.

By performing the same operation for the EVEN field data, the data can be written at the desired V address position.

The frame memory write control circuit of this embodiment having the H address generation circuit shown in FIG. 12 and the V address generation circuit shown in FIG. 1 is provided with the superimpose function described in the section of the prior art. By applying it to the video device (see FIG. 5), the configuration of the device can be simplified.

[0053]

As described above, in the frame memory write control circuit of the present invention, the vertical address is generated by referring to the address table storing the vertical address of the frame memory for each thinning rate. Therefore, the generation of the vertical address can be realized by an extremely simple circuit. Therefore, when the frame memory write control circuit is applied to various video devices, the device configuration can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a V address generation circuit in a frame memory writing circuit of the present invention.

FIG. 2 is a diagram showing an internal configuration of a ROM in FIG.

FIG. 3 is a diagram showing how NTSC signal data is written to a frame memory when the thinning rate is 1/3.

FIG. 4 is a diagram showing how NTSC signal data is written to a frame memory when the thinning rate is 2/3.

FIG. 5 is a block diagram showing the configuration of a general video device with a superimpose function.

6 is a block diagram showing a general configuration of a thinned clock generation circuit in FIG.

FIG. 7 is a diagram showing an overall image of an NTSC signal of one frame and a thinning method thereof.

FIG. 8 is a diagram showing a state of data written in the Fifo memory when the thinning rate is 1/3.

FIG. 9 is a diagram showing a state of data written in a Fifo memory when a thinning rate is 2/3.

10 is a diagram for explaining the operation of the thinning clock generation circuit shown in FIG. 6 when the thinning rate is 1/3.

FIG. 11 is a diagram for explaining the operation of the thinning clock generation circuit shown in FIG. 6 when the thinning rate is 1/3.

FIG. 12 is a diagram showing a configuration of a general H address generation circuit in a frame memory write control circuit.

FIG. 13 is a diagram showing a configuration of a conventional V address generation circuit.

[Explanation of symbols]

 1 counter 2 clear control circuit 3 ROM 4 synchronization separation circuit 5 field determination circuit 6 A / D converter 7 thinning clock generation circuit 8 Fifo memory 9 frame memory write control circuit 10 frame memory 11 read control circuit 12 D / A converter 13 switching Control circuit 21 Counter 22 Clear control circuit

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[Procedure amendment]

[Submission date] September 8, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

FIG. 6 is a block diagram showing the configuration of the thinned-out clock generating circuit. The ternary counter 14 and the quaternary counter 15 count up in accordance with the timing of the horizontal synchronizing signal Hs, and the count value thereof is determined by the logic circuit 16.
Output to. Here, the ternary counter 14 is used when the preset thinning rate is 1/3 or 2/3.
The advance counter 15 is used when the preset thinning rate is 1/2 ⁿ .

Claims (4)

[Claims] 1. An H for generating and outputting a horizontal address of a frame memory in order to write an interlaced signal thinned by a predetermined thinning rate into the frame memory.
A frame memory write control circuit comprising an address generation circuit and a V address generation circuit for generating and outputting a vertical address of the frame memory, wherein the V address generation circuit has a vertical address corresponding to a thinning rate. A frame memory write control circuit comprising storage means for storing an address table and generating and outputting a vertical direction address of the frame memory by referring to the address table. 2. The frame according to claim 1, wherein the V address generation circuit refers to the address table in accordance with a count value that counts up for each line and a decimation rate of interlaced signals. Memory write control circuit. 3. The storage means stores in advance a plurality of address tables each having a vertical address for each of a plurality of decimation rates, and according to a decimation rate of a preset interlace signal,
The address table to be referred to is specified, and the vertical address to be output in the specified address table is specified by the count value obtained by counting the count-up signal output from the H address generation circuit. The frame memory write control circuit according to claim 2, wherein 4. A horizontal address and a vertical address of a frame memory are generated and output, and a vertical address is generated and output to generate an interlaced signal thinned at a predetermined thinning rate. According to the method, a frame memory write control method for writing to the frame memory according to the above is stored in advance in a storage means, and a plurality of address tables having vertical addresses of the frame memory for a plurality of decimation rates are stored in advance. An address table to be referred to in the storage means is designated based on the thinning rate of the interlaced signal, and a designated address table in the designated address table is designated based on the count value counted up for each line of the frame memory. The vertical address to be output is specified, and The frame memory writing control method and outputting a vertical address.