JPH0875803A - Voltage fall detection trigger generation device - Google Patents

Voltage fall detection trigger generation device

Info

Publication number
JPH0875803A
JPH0875803A JP24206194A JP24206194A JPH0875803A JP H0875803 A JPH0875803 A JP H0875803A JP 24206194 A JP24206194 A JP 24206194A JP 24206194 A JP24206194 A JP 24206194A JP H0875803 A JPH0875803 A JP H0875803A
Authority
JP
Japan
Prior art keywords
level
output
voltage
detection
trigger
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24206194A
Other languages
Japanese (ja)
Other versions
JP3400141B2 (en
Inventor
Masanobu Machida
正信 町田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hioki EE Corp
Original Assignee
Hioki EE Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hioki EE Corp filed Critical Hioki EE Corp
Priority to JP24206194A priority Critical patent/JP3400141B2/en
Publication of JPH0875803A publication Critical patent/JPH0875803A/en
Application granted granted Critical
Publication of JP3400141B2 publication Critical patent/JP3400141B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE: To make the response speed faster, and reduce influence of an external noise, so as to enable any voltage fall to be precisely detected by providing an AND circuit, etc., for outputting a logical product of a detection unit output. CONSTITUTION: The voltage level of an input waveform is adjusted by means of a waveform level adjuster 26 and then sent to detection units 28 and 30. The detection unit 28 generates a first output which reaches Hi or Lo level respectively when the positive direction voltage of the input waveform is smaller or greater than a first detection level. The detection unit 30 generates a second output which reaches Hi or Lo level respectively when the positive direction voltage of the input waveform is smaller or greater than a second detection level. When a voltage falls, both first and second outputs remain in Hi level status. The logical product of the first and second outputs is obtained by means of an AND circuit 32 and sent to a timer unit 34. Then, the output of the timer unit 34 varies and falls, and trigger is output from a trigger output unit 36 by means of this falling edge. Thereby, trigger can be applied within a time longer than a voltage fall latter half period.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は被測定電圧、電流、電力
等の波形等を画面上に表示し、紙上に記録する波形記録
計等に備える商用電源電圧等の電圧降下検出トリガ発生
装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage drop detection trigger generator for commercial power supply voltage or the like, which is provided in a waveform recorder for displaying waveforms of measured voltage, current, power, etc. on a screen and recording them on paper. .

【0002】[0002]

【従来の技術】従来、商用電源電圧等の電圧降下を監視
するため、電圧降下検出トリガ発生装置付きの波形記録
計を使用し、入力波形の電圧レベルが所定レベルより落
ち込んだ場合等にトリガを掛け、そのトリガ後或いはト
リガの前後に取り込んだ入力波形等を一定の時間に亘っ
て画面上に表示し、紙上に記録させて観測を行なってい
る。この電圧降下検出トリガ発生装置は図4に示すよう
な入力端子10、全波整流器12、平滑コンデンサ1
4、AMP(アンプ)16、比較器18等からなる。そ
れ故、入力端子10に入る商用電源電圧等の交流電圧波
形を全波整流して平滑した後、AMP16に入れると、
そのAMP16で電圧レベルを調節できる。そこで、更
にレベル調節済みの電圧を比較器18の一方の端子に入
れ、他方の端子に印加されている電圧降下検出レベルを
示す基準電源20の直流電圧Vrefと比較すると、入
力波形の電圧降下を検出してトリガ信号を発生できる。
2. Description of the Related Art Conventionally, a waveform recorder equipped with a voltage drop detection trigger generator is used to monitor a voltage drop such as a commercial power supply voltage, and a trigger is generated when the voltage level of an input waveform falls below a predetermined level. After the trigger, the input waveform or the like captured after the trigger or before and after the trigger is displayed on the screen for a certain period of time and recorded on paper for observation. This voltage drop detection trigger generator includes an input terminal 10, a full-wave rectifier 12, a smoothing capacitor 1 as shown in FIG.
4, an AMP (amplifier) 16, a comparator 18, and the like. Therefore, if the AC voltage waveform such as the commercial power supply voltage that enters the input terminal 10 is full-wave rectified and smoothed, and then put into the AMP 16,
The voltage level can be adjusted by the AMP 16. Therefore, when the level-adjusted voltage is input to one terminal of the comparator 18 and compared with the DC voltage Vref of the reference power source 20 indicating the voltage drop detection level applied to the other terminal, the voltage drop of the input waveform is found. It can detect and generate a trigger signal.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、このよ
うな電圧降下検出トリガ発生装置はコンデンサ14の平
滑作用を利用するため、入力波形の電圧降下状態が何周
期か続かないとトリガが掛からない。それ故、応答速度
が遅く、電圧降下を正確に検出できない。しかも、入力
波形に外来ノズルが乗ってくると、電圧降下してトリガ
が掛かったりするため、外来ノズルの影響を受け易く問
題がある。
However, since such a voltage drop detection trigger generator uses the smoothing action of the capacitor 14, the trigger is not applied unless the voltage drop state of the input waveform continues for several cycles. Therefore, the response speed is slow and the voltage drop cannot be accurately detected. In addition, when the foreign nozzle is placed on the input waveform, the voltage drops and triggers. Therefore, there is a problem that the foreign nozzle is easily affected.

【0004】本発明はこのような従来の問題点に着目し
てなされたものであり、応答速度が速く、外来ノズルの
影響を受け難く、電圧降下を正確に検出できる電圧降下
検出トリガ発生装置を提供することを目的とする。
The present invention has been made in view of such conventional problems, and provides a voltage drop detection trigger generator which has a high response speed, is hardly affected by an external nozzle, and can accurately detect a voltage drop. The purpose is to provide.

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明による電圧降下検出トリガ発生装置22では
前段に入力波形の電圧レベルを調節する波形レベル調節
器26を備え、中段にそのレベル調節済み入力波形の+
方向電圧が+方向に設定した第1検出レベルより小さい
時にHiレベルで、大きい時にLoレベルとなる第1出
力を発生する第1検出部28と、そのレベル調節済み入
力波形の−方向電圧が第1検出レベルと大きさが等し
く、極性が反対の−方向に設定した第2検出レベルより
大きい時にHiレベルで、小さい時にLoレベルとなる
第2出力を発生する第2検出部30と、それ等の第1、
第2出力の論理積を出力するAND回路32とを備え、
後段にその論理積出力の立ち上がりエッジ或いは立ち下
がりエッジの一方によって入力波形の半周期強に相当す
る幅を有するパルスを出力するタイマ部34と、そのタ
イマ部34の出力の立ち下がりエッジによってトリガを
出力するトリガ出力部36とを備える。
In order to achieve the above object, a voltage drop detection trigger generator 22 according to the present invention is provided with a waveform level adjuster 26 for adjusting the voltage level of an input waveform in the preceding stage and its level in the middle stage. + Of adjusted input waveform
When the directional voltage is lower than the first detection level set in the + direction, the first detection unit 28 generates a first output that is at the Hi level and when the directional voltage is higher than the first detection level, and when the voltage is at the higher level, the − direction voltage of the level-adjusted input waveform is the A second detection unit 30 that generates a second output that has a Hi level when the detection level is equal to that of the first detection level and is greater than the second detection level set in the negative direction of the opposite polarity, and becomes a Lo level when the polarity is smaller, and the like. The first of
An AND circuit 32 that outputs a logical product of the second outputs,
A timer unit 34 that outputs a pulse having a width corresponding to a little more than a half cycle of the input waveform at one of the rising edge and the falling edge of the logical product output in the subsequent stage, and a trigger by the falling edge of the output of the timer unit 34 And a trigger output unit 36 for outputting.

【0006】そして、前段にある波形レベル調節器42
と中段にある第1、第2の両検出部44、46との間
に、レベル調節済み入力波形をアナログ値からデジタル
値に変換するA−Dコンバータ48を介在すると好まし
くなる。
Then, the waveform level adjuster 42 in the preceding stage
It is preferable to interpose an AD converter 48 for converting the level-adjusted input waveform from an analog value to a digital value between the first and second detection sections 44 and 46 in the middle stage.

【0007】[0007]

【作用】上記のように構成し、入力波形の電圧レベルを
波形レベル調節器26で調節した後、第1、第2検出部
28、30に与える。すると、第1検出部28はそのレ
ベル調節済み入力波形の+方向電圧が+方向に設定した
第1検出レベルより小さい時にHiレベルで、大きい時
にLoレベルとなる第1出力を発生し、第2検出部30
はそのレベル調節済み入力波形の−方向電圧が第1検出
レベルと大きさが等しく、極性が反対の−方向に設定し
た第2検出レベルより大きい時にHiレベルで、小さい
時にLoレベルとなる第2出力を発生する。それ故、商
用電源電圧等の電圧が所定の値で安定している場合に
は、第1出力、第2出力共にHiレベル、Loレベルを
交互に規則正しく繰返し発生するのに対し、電圧が降下
すると、第1出力、第2出力共にLoレベルにならず、
Hiレベル状態のままになる。そこで、AND回路32
により第1、第2出力の論理積を求め、タイマ部34に
与える。
With the above configuration, the voltage level of the input waveform is adjusted by the waveform level adjuster 26 and then applied to the first and second detectors 28 and 30. Then, the first detection unit 28 generates a first output that is at the Hi level when the + direction voltage of the level-adjusted input waveform is smaller than the first detection level set in the + direction, and at the Lo level when the voltage is larger than the first detection level, the second output. Detection unit 30
Is a Hi level when the − direction voltage of the level-adjusted input waveform is equal in magnitude to the first detection level and is higher than a second detection level set in the − direction of the opposite polarity, and is a Lo level when the voltage is lower than the second detection level. Generate output. Therefore, when the commercial power supply voltage or the like is stable at a predetermined value, Hi level and Lo level are alternately and regularly generated in both the first output and the second output, while the voltage drops. , The first output and the second output do not become Lo level,
It remains in the Hi level state. Therefore, the AND circuit 32
The logical product of the first output and the second output is obtained by and is given to the timer unit 34.

【0008】すると、タイマ部34はその論理積出力の
立ち上がりエッジ或いは立ち下がりエッジの一方によっ
て入力波形の半周期強に相当する幅を有するパルスを出
力する。それ故、論理積出力の立ち上がり或いは立ち下
がり後における入力波形の半周期強に相当する時間内
に、次の論理積出力の立ち上がり或いは立ち下がりがあ
ると、タイマ部34の出力は継続してHiレベル状態の
ままである。しかし、次の論理積出力の立ち上がり或い
は立ち下がりがないと、その時間経過時にタイマ部34
の出力が変化して立ち下がる。すると、この立ち下がり
エッジによってトリガ出力部36からトリガが出る。
Then, the timer section 34 outputs a pulse having a width corresponding to a little more than a half cycle of the input waveform by one of the rising edge and the falling edge of the logical product output. Therefore, when the next rising or falling of the logical product output occurs within a time period corresponding to a little more than a half cycle of the input waveform after the rising or falling of the logical product output, the output of the timer unit 34 continues to be Hi. Remains leveled. However, if the next logical product output does not rise or fall, the timer unit 34
Output changes and falls. Then, the trigger is output from the trigger output unit 36 by this falling edge.

【0009】そして、波形レベル調節器42と第1、第
2の両検出部44、46との間に、レベル調節済み入力
波形をアナログ値からデジタル値に変換するA−Dコン
バータ48を介在しておくと、レベル調節済み入力波形
の±方向電圧をそれぞれデジタル値に変換した後、第
1、第2検出部44、46にそれぞれ与えることができ
る。それ故、デジタル値によって第1検出部44では第
1検出レベルとの比較を行ない、第2検出部46では第
2検出レベルとの比較を行なえる。
An A-D converter 48 for converting the level-adjusted input waveform from an analog value to a digital value is interposed between the waveform level adjuster 42 and the first and second detectors 44 and 46. In other words, the ± direction voltages of the level-adjusted input waveform can be converted into digital values and then applied to the first and second detectors 44 and 46, respectively. Therefore, the first detection unit 44 can perform comparison with the first detection level and the second detection unit 46 can perform comparison with the second detection level based on the digital value.

【0010】[0010]

【実施例】以下、添付図面に基づいて、本発明の実施例
を説明する。図1は本発明を適用した波形記録計用電圧
降下検出トリガ発生装置の構成を示す回路図である。図
中、22は波形記録計用電圧降下検出トリガ発生装置、
24はそのアース付き入力端子、26はAMP(アン
プ)、28は第1検出部、30は第2検出部、32はA
ND(アンド)回路、34はタイマ部、36はトリガ出
力部である。このAMP26は端子24に入る商用電源
電圧等の入力波形の電圧レベルを増幅し或いは減衰して
調節する波形レベル調節器である。それ故、AMP26
に接続する第1検出部28と第2検出部30にレベル調
節済み入力波形がそれぞれ入る。
Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing the configuration of a voltage drop detection trigger generator for a waveform recorder to which the present invention is applied. In the figure, 22 is a voltage drop detection trigger generator for a waveform recorder,
24 is the grounded input terminal, 26 is an AMP (amplifier), 28 is the first detector, 30 is the second detector, and 32 is A.
An ND (and) circuit, 34 is a timer section, and 36 is a trigger output section. The AMP 26 is a waveform level adjuster for amplifying or attenuating the voltage level of the input waveform such as the commercial power supply voltage which is input to the terminal 24. Therefore, AMP26
The level-adjusted input waveforms are respectively input to the first detection unit 28 and the second detection unit 30 connected to.

【0011】レベル調節済み入力波形が入ると、第1検
出部28はその入力波形の+方向電圧が+方向に設定し
た第1(電圧降下)検出レベルより小さい時にHiレベ
ルで、大きい時にLoレベルとなる第1出力を発生し、
第2検出部30は入力波形の−方向電圧が第1検出レベ
ルと大きさが等しく、極性が反対の−方向に設定した第
2(電圧降下)検出レベルより大きい時にHiレベル
で、小さい時にLoレベルとなる第2出力を発生する。
それ故、商用電源電圧等の電圧が所定の値で安定してい
る場合には、第1出力、第2出力共にHiレベル、Lo
レベルを交互に規則正しく繰返し発生するのに対し、電
圧が降下すると、第1出力、第2出力共にLoレベルに
ならず、Hiレベル状態のままになる。そこで、AND
回路32により第1、第2出力の論理積を求め、タイマ
部34に与える。
When the level-adjusted input waveform is input, the first detector 28 is at the Hi level when the + direction voltage of the input waveform is smaller than the first (voltage drop) detection level set in the + direction, and is at the Lo level when it is larger. Produces the first output
The second detection unit 30 is at the Hi level when the − direction voltage of the input waveform has the same magnitude as the first detection level and is larger than the second (voltage drop) detection level set in the − direction of the opposite polarity, and is Lo level when the voltage is smaller. It produces a second output that is level.
Therefore, when the voltage such as the commercial power supply voltage is stable at a predetermined value, both the first output and the second output are at the Hi level and Lo level.
Levels are generated alternately and regularly, but when the voltage drops, neither the first output nor the second output goes to the Lo level, and the Hi level remains. So AND
The circuit 32 obtains the logical product of the first and second outputs and supplies the logical product to the timer unit 34.

【0012】すると、タイマ部34はその論理積出力の
LoレベルからHiレベルに立ち上がるエッジ或いはH
iレベルからLoレベルに立ち下がるエッジの一方によ
って入力波形の半周期強に相当する幅を有するパルスを
出力する。それ故、論理積出力の立ち上がり或いは立ち
下がり後における入力波形の半周期強に相当する時間内
に、次の論理積出力の立ち上がり或いは立ち下がりがあ
ると、タイマ部34の出力は継続してHiレベル状態の
ままである。しかし、次の論理積出力の立ち上がり或い
は立ち下がりがないと、その時間経過時にタイマ部34
の出力が変化して立ち下がる。すると、トリガ出力部3
6はタイマ部出力の立ち下がりエッジによってトリガを
出す。これ等の動作を行なわせる際、基準となるクロッ
クがその出力ライン38より第1、第2検出部28、3
0、タイマ部34、トリガ出力部36に与えられる。な
お、第1、第2検出部28、30、タイマ部34、トリ
ガ出力部36等はいずれも専用に作られたICを使用
し、或いは汎用のICを組み合わせて作る。
Then, the timer unit 34 raises the edge of the logical product output from the Lo level to the Hi level or the H level.
A pulse having a width corresponding to a little more than a half cycle of the input waveform is output by one of the edges falling from the i level to the Lo level. Therefore, when the next rising or falling of the logical product output occurs within a time period corresponding to a little more than a half cycle of the input waveform after the rising or falling of the logical product output, the output of the timer unit 34 continues to be Hi. Remains leveled. However, if the next logical product output does not rise or fall, the timer unit 34
Output changes and falls. Then, the trigger output unit 3
6 issues a trigger at the falling edge of the timer section output. When these operations are performed, the reference clock is output from the output line 38 of the first and second detection units 28, 3
0, the timer unit 34, and the trigger output unit 36. Each of the first and second detection units 28 and 30, the timer unit 34, the trigger output unit 36, and the like uses a specially made IC or a combination of general-purpose ICs.

【0013】このような一連の動作のタイミングを示す
と、図2のようになる。図ではAND出力の立ち上がり
により、タイマ部34の出力として両端矢印付きの直線
の長さで幅を示した正論理によるパルスが発生し、入力
波形の電圧レベルが所定の値で安定している時には前回
のパルス出力中(Hiレベル)の時に次の立ち上がりエ
ッジの入力が入り、その時点から再び半周期強のパルス
が続けて出ることを示している。なお、入力波形の周波
数が50Hzなら、1周期は1/50=20msとなる
ため、パルス幅は10msとなる。このようにして、入
力波形を半周期毎にチェックして電圧降下を検出する
と、その電圧降下後半周期強の時間以内でトリガを掛け
ることが可能になり、応答速度を速く、電圧降下を正確
に検出することができる。
The timing of such a series of operations is shown in FIG. In the figure, when the AND output rises, a positive logic pulse whose width is indicated by the length of a straight line with double-ended arrows is generated as the output of the timer unit 34, and when the voltage level of the input waveform is stable at a predetermined value. This indicates that the input of the next rising edge is input during the previous pulse output (Hi level), and a pulse of a little more than a half cycle is continuously output again from that point. If the frequency of the input waveform is 50 Hz, 1 cycle is 1/50 = 20 ms, so the pulse width is 10 ms. In this way, if the input waveform is checked every half cycle and a voltage drop is detected, it is possible to trigger within the time of the latter half cycle of the voltage drop, the response speed is fast, and the voltage drop is accurate. Can be detected.

【0014】図3は本発明を適用した他の波形記録計用
電圧降下検出トリガ発生装置の構成を示す回路図であ
る。この電圧降下検出トリガ発生装置40ではAMP4
2と第1、第2の両検出部44、46との間にA−Dコ
ンバータ48を介在する。それ故、端子50に入る入力
波形はAMP26で電圧レベルの調節を受けた後にA−
Dコンバータ48に入る。すると、レベル調節済みの入
力波形の±方向電圧をそれぞれA−Dコンバータ48で
アナログ値からデジタル値に変換できる。このようにし
て、レベル調節済みの入力波形をデジタル値に変換した
後に第1、第2検出部44、46に入れ、デジタル値に
よって第1検出部44では第1検出レベルとの比較を行
ない、第2検出部46では第2検出レベルとの比較を行
なった後、更にAND回路52、タイマ部54、トリガ
出力部56等によって、先の実施例における各対応部分
と同様の動作をそれぞれ行なわせる。すると、入力波形
に外来ノイズが乗って来ても、その影響を受け難くな
り、誤動作によるトリガの発生がなくなる。但し、CL
K(クロック)信号ライン58からA−Dコンバータ4
8、第1、第2検出部44、46、タイマ部54、トリ
ガ出力部56等にクロックパルスを入れる。なお、第
1、第2検出部44、46にはデジタルICを使用す
る。
FIG. 3 is a circuit diagram showing the configuration of another voltage drop detection trigger generator for a waveform recorder to which the present invention is applied. In the voltage drop detection trigger generator 40, the AMP4
An A-D converter 48 is interposed between the second and the first and second detection units 44 and 46. Therefore, the input waveform entering the terminal 50 is A- after being adjusted in voltage level by the AMP 26.
Enter the D converter 48. Then, the ± direction voltage of the input waveform whose level has been adjusted can be converted from an analog value to a digital value by the AD converter 48. In this way, the level-adjusted input waveform is converted into a digital value and then input into the first and second detection units 44 and 46, and the first detection unit 44 compares the digital value with the first detection level, After the second detection section 46 makes a comparison with the second detection level, the AND circuit 52, the timer section 54, the trigger output section 56 and the like are caused to perform the same operations as the corresponding portions in the previous embodiment. . Then, even if external noise is added to the input waveform, it is less likely to be affected by the noise, and triggers due to malfunction are eliminated. However, CL
From the K (clock) signal line 58 to the AD converter 4
8, clock pulses are input to the first and second detection units 44 and 46, the timer unit 54, the trigger output unit 56, and the like. A digital IC is used for the first and second detectors 44 and 46.

【0015】[0015]

【発明の効果】以上説明した本発明によれば、請求項1
では入力波形の電圧レベルを波形レベル調節器で調節し
た後、第1、第2検出部で入力波形の電圧レベルを半周
期毎に第1、第2検出レベルと比較してチェックし、入
力波形の電圧降下をAND回路とタイマ部で検出し、ト
リガ出力部によってその電圧降下後の半周期強の時間以
内でトリガを掛けることができる。それ故、応答速度が
速く、電圧降下を正確に検出できる。
According to the present invention described above, claim 1
Then, after adjusting the voltage level of the input waveform with the waveform level adjuster, the voltage level of the input waveform is checked by comparing the input waveform voltage level with the first and second detection levels every half cycle in the first and second detection units. The AND circuit and the timer section detect the voltage drop of and the trigger output section can trigger the voltage within a little more than a half cycle after the voltage drop. Therefore, the response speed is fast and the voltage drop can be accurately detected.

【0016】請求項2ではレベル調節済みの入力波形の
±方向電圧をそれぞれA−Dコンバータでアナログ値か
らデジタル値に変換した後、第1、第2検出部に入れて
それ以降の処理を行なうため、応答速度が速いばかりで
なく、外来ノイズの影響を受け難くなるので誤動作によ
るトリガの発生もなく、電圧降下を更に正確に検出でき
る。
According to a second aspect of the present invention, the ± direction voltage of the level-adjusted input waveform is converted from an analog value to a digital value by the AD converter, and then the voltage is put into the first and second detection sections and the subsequent processing is performed. Therefore, not only is the response speed fast, but it is also less susceptible to the influence of external noise, so that a trigger due to malfunction does not occur, and the voltage drop can be detected more accurately.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を適用した波形記録計用電圧降下検出ト
リガ発生装置の構成を示す回路図である。
FIG. 1 is a circuit diagram showing a configuration of a voltage drop detection trigger generator for a waveform recorder to which the present invention is applied.

【図2】同電圧降下検出トリガ発生装置の各部の動作を
示すタイミングチャートである。
FIG. 2 is a timing chart showing an operation of each unit of the same voltage drop detection trigger generator.

【図3】本発明を適用した他の波形記録計用電圧降下検
出トリガ発生装置の構成を示す回路図である。
FIG. 3 is a circuit diagram showing a configuration of another voltage drop detection trigger generator for a waveform recorder to which the present invention is applied.

【図4】従来の波形記録計用電圧降下検出トリガ発生装
置の構成を示す回路図である。
FIG. 4 is a circuit diagram showing a configuration of a conventional voltage drop detection trigger generator for a waveform recorder.

【符号の説明】[Explanation of symbols]

22、40…波形記録計用検出トリガ発生装置 24、
50…入力端子 26、42…AMP 28、44…第
1検出部 30、46…第2検出部 32、52…AN
D回路 34、54…タイマ部 36、56…トリガ出
力部 48…A−Dコンバータ
22, 40 ... Detection trigger generator for waveform recorder 24,
50 ... Input terminals 26, 42 ... AMP 28, 44 ... 1st detection part 30, 46 ... 2nd detection part 32, 52 ... AN
D circuit 34, 54 ... Timer unit 36, 56 ... Trigger output unit 48 ... A-D converter

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 入力波形の電圧レベルを調節する波形レ
ベル調節器と、そのレベル調節済み入力波形の+方向電
圧が+方向に設定した第1検出レベルより小さい時にH
iレベルで、大きい時にLoレベルとなる第1出力を発
生する第1検出部と、そのレベル調節済み入力波形の−
方向電圧が第1検出レベルと大きさが等しく、極性が反
対の−方向に設定した第2検出レベルより大きい時にH
iレベルで、小さい時にLoレベルとなる第2出力を発
生する第2検出部と、それ等の第1、第2出力の論理積
を出力するAND回路と、その論理積出力の立ち上がり
エッジ或いは立ち下がりエッジの一方によって入力波形
の半周期強に相当する幅を有するパルスを出力するタイ
マ部と、そのタイマ部出力の立ち下がりエッジによって
トリガを出力するトリガ出力部とを備えることを特徴と
する電圧降下検出トリガ発生装置。
1. A waveform level adjuster for adjusting a voltage level of an input waveform, and H when a + direction voltage of the level-adjusted input waveform is smaller than a first detection level set in the + direction.
At the i level, a first detection unit that generates a first output that becomes a Lo level when the i level is large and a −
When the direction voltage has the same magnitude as the first detection level and the polarity is larger than the second detection level set in the negative-direction, H
At the i level, a second detection unit that generates a second output that becomes Lo level when small, an AND circuit that outputs a logical product of the first and second outputs thereof, and a rising edge or a rising edge of the logical product output. A voltage comprising a timer unit that outputs a pulse having a width corresponding to a little more than a half cycle of an input waveform by one of the falling edges, and a trigger output unit that outputs a trigger by the falling edge of the output of the timer unit. Drop detection trigger generator.
【請求項2】 波形レベル調節器と第1、第2の両検出
部との間に、レベル調節済み入力波形をアナログ値から
デジタル値に変換するA−Dコンバータを介在すること
を特徴とする請求項1記載の電圧降下検出トリガ発生装
置。
2. An A-D converter for converting a level-adjusted input waveform from an analog value to a digital value is interposed between the waveform level adjuster and both the first and second detectors. The voltage drop detection trigger generation device according to claim 1.
JP24206194A 1994-09-09 1994-09-09 Voltage drop detection trigger generator Expired - Lifetime JP3400141B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24206194A JP3400141B2 (en) 1994-09-09 1994-09-09 Voltage drop detection trigger generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24206194A JP3400141B2 (en) 1994-09-09 1994-09-09 Voltage drop detection trigger generator

Publications (2)

Publication Number Publication Date
JPH0875803A true JPH0875803A (en) 1996-03-22
JP3400141B2 JP3400141B2 (en) 2003-04-28

Family

ID=17083706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24206194A Expired - Lifetime JP3400141B2 (en) 1994-09-09 1994-09-09 Voltage drop detection trigger generator

Country Status (1)

Country Link
JP (1) JP3400141B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011043334A (en) * 2009-08-19 2011-03-03 Tabuchi Electric Co Ltd Ac input monitoring circuit and power supply device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011043334A (en) * 2009-08-19 2011-03-03 Tabuchi Electric Co Ltd Ac input monitoring circuit and power supply device

Also Published As

Publication number Publication date
JP3400141B2 (en) 2003-04-28

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